Datasheet GS9035ACTJ, GS9035ACPJ Datasheet (Gennum Corporation)

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

Revision Date: November 2000 Document No. 522 - 41- 04

DATA SHEET

GS9035A

FEATURES

• adjustment-free operation

• auto-rate selection for 5 SMPTE data rates: 143, 177,
270, 360, 540Mb/s

• data rate indication output

• serial data output mute when PLL is not locked

• immune to harmonic locking

• operation independent of SAV/EAV sync signals

• low jitter , low power

• single external VCO resistor for operation with five
input data rates

• large input jitter tolerance: typically 0.45 UI beyond
loop bandwidth

• power savings mode (output serial clock disable)

• system friendly: serial clock remains active when data
outputs muted

• robust lock detect

APPLICATIONS

The GS9035A is used for Clock and Data recovery, and
Jitter elimination for all high speed serial digital interface
applications involving SMPTE 259M and other data
standards.

DESCRIPTION

The GS9035A is a high performance clock and data
recovery IC designed for serial digital data. The GS9035A
receives either single-ended or differential PECL data and
outputs differential PECL clock and retimed data signals.

The GS9035A can operate in either auto or manual rate
selection mode. In auto mode the GS9035A is ideal for
multi-rate serial data protocols such as SMPTE 259M. In this
mode the GS9035A automatically detects and locks onto
the incoming data signal. For single rate data systems, the
GS9035A can be configured to operate in manual mode. In
both modes, the GS9035A requires only one external
resistor to set the VCO centre frequency and provides
adjustment free operation.

The GS9035A has dedicated pins to indicate LOCK and
data rate. In addition, an internal muting function forces the
serial data outputs to a static state when input data is not
present or when the PLL is not locked. The serial clock
outputs can also be disabled resulting in a 10% power
savings.

The GS9035A is packaged in a 28 pin PLCC and operates
from a single +5 or -5 Volt power supply.

BLOCK DIAGRAM

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS9035ACPJ 28 pin PLCC 0°C to 70°C

GS9035ACTJ 28 pin PLCC Tape 0°C to 70°C

DDI/DDI

LF+ LFS LF- CBG R

VCO

CARRIER DETECT

PHASELOCK

HARMONIC

FREQUENCY

ACQUISITION

VCO

DIVISION

3 BIT

COUNTER

LOCK

SDO

SDO

CLK_EN

SCO

SCO

SMPTE

AUTO/MAN

SSO
SS1

SS2

COSC

2

PHASE

DETECTOR

CHARGE

PUMP

DECODER

LOGIC

GENLINX

™

II

GS9035A

Serial Digital Reclocker

GENNUM CORPORATION

522 - 41- 04

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GS9035A

Fig. 1 Jitter Measurement Test Setup

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage (V

S

) 5.5V

Input Voltage Range (any input) V

CC

+ 0.5 to VEE - 0.5V

Operating Temperature Range 0°C ≤ T

A

≤ 70°C

Storage Temperature Range -65°C ≤ T

S

≤ 150°C

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, VEE = 0V, TA = 25° unless otherwise stated, RLF = 1.8K, C

LF1

= 15nF, C

LF2

= 3.3pF.

PARAMETER CONDITION MIN

TYPICAL

1

MAX UNITS NOTES

TEST

LEVEL

Supply Voltage 4.75 5.00 5.25 V 1

Supply Current CLK_EN = 0 - 90 110 mA 1

CLK_EN = 1 - 105 120 mA

DDI/DDI

Common Mode Input

Voltage Range

V

EE

+ (V

DIFF

/2) 0.4 to 4.6 V

CC

- (V

DIFF

/2) V 2 1

DDI/DDI

Differential Input Drive 200 800 2000 mV 1

AUTO/MAN

, SMPTE,

SS[2:0] Input Voltage

High 2.0 - - V 1

Low - - 0.8

CLK_EN Input Voltage High 2.5 - - V 1

Low - - 0.8

LOCK Output Sink Current 500 - - µA 3 1

SS[2:0] Output Voltage High 4.4 4.7 - V 1

Low - 0.2 0.4

SS[2:0] Source Current Auto Mode 180 300 - µA 1

SS[2:0] Sink Current Auto Mode 0.6 1 - mA

SS[2:0] Source Current Manual Mode - 0 - µA 4 1

SS[2:0] Sink Current Manual Mode - 0.8 5 µA

CLK_EN Source Current Low - 26 55 µA 1

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands
for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands
for supply and temperature ranges using correlated test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

NOTES

1. TYPICAL - measured on EB-RD35A board,
T

A

= 25°C.

2. V

DIFF

is the differential input signal swing.

3. LOCK is an open collector output and
requires an external pullup resistor.

4. Pins SS[2:0] are outputs in AUTO mode and
inputs in MANUAL mode.

PATTERN 223-1

CLK DATA

DI
DI

SDO

CH-1 TRIG

TEKTRONIX

GIGABERT 1400

GENNUM

TEST BOARD

TEKTRONIX

CSA803

GENNUM CORPORATION

522 - 41- 04

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GS9035A

AC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8K, C

LF1

= 15nF, C

LF2

= 3.3pF

PARAMETER CONDITION MIN

TYPICAL

1

MAX UNITS NOTES

TEST

LEVEL

Serial Data Rate SDI 143 - 540 Mb/s 1

Intrinsic Jitter

Psuedorandom (2

23

- 1)

270Mb/s - 185 See Figure 6 ps p-p 2 4

540Mb/s - 164

Intrinsic Jitter
Pathological

(SDI checkfield)

270Mb/s - 462 See Figure 7 ps p-p 2 1

360Mb/s - 308

540Mb/s - 260

Input Jitter Tolerance 270Mb/s 0.40 0.56 - UI p-p 3 1

540Mb/s 0.35 0.43 -

Lock Time Synchronous
Switch

t

SWITCH

< 0.5µs, 270Mb/s - 1 - µs 4 7

0.5µs < t

SWITCH

< 10ms - 1 - ms

t

SWITCH

> 10ms - 4 - ms

Lock Time
Asynchronous Switch

Loop Bandwidth = 6MHz at 540 Mb/s - 10 - ms 5 7

Carrier Loss Time R

LOCK

= 10k, C

LOAD

=5pF 0.5 1 2 µs 6 7

SDO to SCO
Synchronization

-200 0 200 ps 7

SDO, SCO Output Signal
Swing

75Ω DC load 600 800 1000 mV p-p 1

SDO, SCO Rise and Fall
Times

20% - 80% 200 300 400 ps 7

NOTES

1. TYPICAL - measured on EB-RD35A board, T

A

= 25°C.

2. Characterized 6 sigma rms.

3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz).

4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie: line 10
switching for component NTSC).

5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate.

6. Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is
removed.

TEST LEVEL

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

GENNUM CORPORATION

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GS9035A

PIN CONNECTIONS

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1,7,8,11,27 V

EE

I Most negative power supply connection.

2 COSC I Timing control capacitor for internal system clock.

3 LOCK O Lock indication. When HIGH, the GS9035A is locked. LOCK is an open collector output and

requires an external 10k pullup resistor.

4 SMPTE I SMPTE/Other rate select.

5, 6 DDI/DDI

I Digital data input (Differential ECL/PECL).

9V

CC1

I Most positive power supply connection.

10 AUTO/MAN

I Auto or Manual mode select. TTL/CMOS compatible input.

12 LF+ I Loop filter component connection.

13 LFS I Loop filter component connection.

14 LF- I Loop filter component connection.

15 R

VCO

_RTN I R

VCO

return.

16 R

VCO

I Frequency setting resistor.

17 CBG I Internal bandgap voltage filter capacitor.

18 V

CC2

I Most positive power supply connection.

19 - 21 SS[2:0] I/O Data rate indication (Auto mode) or data rate select (Manual mode). TTL/CMOS compatible I/O. In

auto mode these pins can be left unconnected.

22, 23 SCO

/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω

pullup resistors.

24, 25 SDO

/SDO O Serial data output. SDO/SDO are differential current mode outputs and require external 75Ω pullup

resistors.

26 V

CC3

I Most positive power supply connection.

28 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled.

DDI
DDI

V

EE

V

EE

V

CC1

AUTO/MAN

V

EE

SDO
SDO
SCO
SCO
SSO
SS1
SS2

SMPTE

LOCK

COSC

VEECLK_EN

VEEV

CC3

GS9035A
TOP VIEW

LF+

LFS

LF-

R

VCO

_RTN

R

VCO

CBG

V

CC2

25
24
23
22
21
20
19

5
6
7
8
9
10
11

12 13 14 15 16 17 18

4 3 2 1 28 27 26

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GS9035A

TYPICAL PERFORMANCE CURVES

(V

S

= 5V, TA = 25°C unless otherwise shown.)

Fig. 2 Intrinsic Jitter (223-1 Pattern) 30Mb/s

Fig. 3 Intrinsic Jitter (2

23

-1 Pattern) 143Mb/s

Fig. 4 Intrinsic Jitter (2

23

-1 Pattern) 270Mb/s

Fig. 5 Intrinsic Jitter (2

23

-1 Pattern) 540Mb/s

Fig. 6 Intrinsic Jitter - Pseud orandom (2

23

-1)

Fig. 7 Intrinsic Jitter - Pathological SDI Checkfield

0

200

400

600

800

1000

1200

1400

1600

1800

2000

100 200 300 400 500 600

SDI DATA RATE (Mb/s)

JITTER (ps)

QA Output Jitter Limit, Sample Tested

Max

Typical

Min

T

A

=0 to 70˚C, VCC=4.75 to 5.25V for the typical range

Typical Range, Characterized

0

200

400

600

800

1000

1200

1400

1600

1800

2000

100 200 300 400 500 600

SDI DATA RATE (Mb/s)

Typical

Min

JITTER (ps p-p)

Max

QA Output Jitter Limit, Sample Tested

T

A

= 0 to 70˚C, VCC = 4.75 to 5.25V for the typical range

Typical Range, Characterized

GENNUM CORPORATION

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GS9035A

Fig. 8 Typical Input Jitter Tolerance (Character ized)

Fig. 9 Typical IJT vs. Temperature (V cc =5.0V) (Characterized)

DETAILED DESCRIPTION

The GS9035A receives either a single-ended or differential
PECL serial data stream at the DDI and DDI

inputs. It locks
an internal clock to the incoming data and outputs the
differential PECL retimed data signal and recovered clock
on outputs SDO

/SDO and SCO/SCO respectively. The
timing between the input, output, and clock signals is
shown below.

Fig. 10 Input/Output Clock Signal Timing

The GS9035A reclocker contains four main functional
blocks: the Phase Locked Loop, Auto/Manual Data Rate
Select, Frequency Acquisition, and Logic Circuit.

1. PHASE LOCKED LOOP (PLL)

The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.

Fig. 11 Simplified Diagram of the PLL

1.1. VCO

The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 30 and 540Mb/s and has a pull range of

-13 +25% about the center frequency depending on the
signal data rate. A single low impedance external resistor,
R

VCO

, sets the VCO center frequency

(see Figure 12).

The

low impedance R

VCO

minimizes thermal noise and reduces

the PLL's sensitivity to PCB noise.

For a given R

VCO

value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the ƒ

L

curve. For all other
SMPTE/SS0 combinations, the VCO center frequency
corresponds to the ƒH curve (ƒH is approximately 1.5 x ƒL).

0

0.1

0.2

0.3

0.4

0.5

0.6

100 200 300 400 500 600

DATA RATE (Mb/s)

IJT (UI)

TA = 0 to 70˚C, V

CC

= 4.75 to 5.25V

0.200

0.250

0.300

0.350

0.400

0.450

0.500

0.550

0.600

0 10203040506070

TEMPERATURE (C˚)

IJT (UI)

143Mb/s

177Mb/s
270Mb/s

360Mb/s

540Mb/s

DDI

SDO

SCO

50%

DDI/DDI

LF+

LFS

LF-

R

VCO

VCO

DIVISION

R

LFCLF1

C

LF2

2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

LOOP
FILTER

GENNUM CORPORATION

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GS9035A

Fig. 12 VCO Frequency vs. R

VCO

The recommended R

VCO

value for auto rate SMPTE 259M

applications is 365Ω.

The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN

, SMPTE, and SS[2:0] pin

(see

Auto/Manual Data Rate Select section for further details).

In
addition, a manually selectable modulus 8 divider allows
operation at data rates as low as 30Mb/s.

When the input data stream is removed for an excessive
period of time

(see AC electrical characteristics table),

the
VCO frequency can drift from the previously locked
frequency up to the maximum shown in Table 1.

1.2. Phase Detector

The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function between the input phase
and output timing pulses maximizing the input jitter
tolerance of the PLL.

1.3. Charge Pump

The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design ensures that the output phase does not drift when
data transitions are sparse. This makes the GS9035A ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.

1.4. Loop Filter

The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9035A increased immunity
to PCB board noise.

The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL Design
Guidelines section. Recommended values for SMPTE 259M
applications are shown in the Typical Application Circuit
diagram.

2. FREQUENCY ACQUISITION

The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9035A uses a frequency acquisition circuit.

The frequency acquisition circuit sweeps the VCO control
voltage such that the VCO frequency changes from -10% to
+10% of the center frequency. Figure 13 shows a typical
sweep waveform.

Fig. 13 Typical Sweep Form

The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 3-bit counter.

TABLE 1: Frequency Drift Range (when PLL loses lock)

LOSES LOCK FROM MIN (%) MAX(%)

143Mb/s lock -21 21

177Mb/s lock -12 26

270Mb/s lock -13 28

360 Mb/s lock -13 24

540 Mb/s lock -13 28

0

100

200

300

400

500

600

700

800

0 200 400 600 800 1000 1200 1400 1600 1800

VCO FREQUENCY (MHz)

R

VCO

(Ω)

ƒ

H

ƒ

L

SMPTE=1
SSO=1

V

LF

t

swp

T

cycle

T

cycle

= t

swp

+ t

sys

t

sys

A

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8

GS9035A

The average sweep time, t

swp

, is determined by the loop

filter component, C

LF1

, and the charge pump current, Ι

CP

:

The nominal sweep time is approximately 121µs when
C

LF1

= 15nF and Ι

CP

= 165µA (R

VCO

= 365Ω).

An internal system clock determines t

sys

(

see section 7,

Logic Circuit

).

3. LOGIC CIRCUIT

The GS9035A is controlled by a finite state logic circuit
which is clocked by an asynchronous system clock. That is,
the system clock is completely independent of the incoming
data rate. The system clock runs at low frequencies, relative
to the incoming data rate, and thus reduces interference to
the PLL. The period of the system clock is set by the COSC
capacitor and is

t

sys

= 9.6 x 104 x COSC [seconds]

The recommended value for t

sys

is 450µs (COSC = 4.7nF).

4. AUTO/MANUAL DATA RATE SELECT

The GS9035A can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN

).

4.1. Auto Mode (AUTO/MAN = 1)

In auto mode, the GS9035A uses a 3-bit counter to
automatically cycle through five (SMPTE=1) or three
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[2:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
Note that for SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[2:0].

4.2. Manual Mode (AUTO/MAN = 0)

In manual mode, the GS9035A divider moduli is fixed. In
this mode, the SS[2:0] pins are inputs and set the divider
moduli according to Table 3.

TABLE 2: Data Rate Indication in Auto Mode

AUTO/MAN

= 1 (Auto Mode)

ƒ

H

, ƒL = VCO center frequency as per Figure 12

SMPTE SS[2:0]

DIVIDER

MODULI

PLL CLOCK

1 000 4 ƒ

H

/4

1 001 2 ƒ

L

/2

1 010 2 ƒ

H

/2

1 011 1 ƒ

L

1 100 1 ƒ

H

1 101 - -

1 110 - -

1 111 - -

t

swp

4
3

-- -

C

LF1

I

CP

-------------

ondssec[]=

0 000 4 ƒH/4

0 001 4 ƒ

H

/4

0 010 2 ƒ

H

/2

0 011 2 ƒ

H

/2

0 100 1 ƒ

H

0 101 - -

0 110 - -

0 111 - -

TABLE 3: Data Rate Select in Manual Mode

AUTO/MAN

= 0 (Manual Mode)

ƒ

H

, ƒL = VCO center frequency as per Figure 8

SMPTE SS[2:0]

DIVIDER

MODULI

PLL CLOCK

1 000 4 ƒ

H

/4

1 001 2 ƒ

L

/2

1 010 2 ƒ

H

/2

1 011 1 ƒ

L

1 100 1 ƒ

H

1 101 8 ƒL/8

1 110 8 ƒ

H

/8

1 111 - -

0 000 4 ƒ

H

/4

0 001 4 ƒ

H

/4

0 010 2 ƒ

H

/2

0 011 2 ƒ

H

/2

0 100 1 ƒ

H

0 101 1 ƒ

H

0 110 8 ƒH/8

0 111 - -

TABLE 2: Data Rate Indication in Auto Mode (Continued)

AUTO/MAN

= 1 (Auto Mode)

ƒ

H

, ƒL = VCO center frequency as per Figure 12

SMPTE SS[2:0]

DIVIDER

MODULI

PLL CLOCK

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GS9035A

5. LOCKING

The GS9035A indicates lock when three conditions are
satisfied:

1. Input data is detected.

2. The incoming data signal and the PLL clock are phase

locked.

3. The system is not locked to a harmonic.

The GS9035A defines the presence of input data when at
least one data transition occurs every 1µs.

The GS9035A assumes that it is NOT locked to a harmonic
if the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every t

sys

/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. (In an harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.)

6. LOCK TIME

The lock time of the GS9035A depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9035A is changed from one source to another source
which is at a different data rate.

When input data to the GS9035A is removed, the GS9035A
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9035A begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9035A locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:

In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described in section 2,

Frequency Acquisition

. In
manual mode, the frequency acquisition circuit may have to
sweep over an entire cycle (depending on initial conditions)
to acquire lock resulting in a maximum lock time of 2T

cycle

+

2t

sys

. In auto tune mode, the maximum lock time is 6T

cycle

+

2t

sys

since the frequency acquisition circuit may have to

cycle through 5 possible counter states (depending on
initial conditions) to acquire lock. The nominal value of T

cycle

for the GS9035A operating in a typical SMPTE 259M
application is approximately 1.3ms.

The GS9035A has a dedicated LOCK output (pin 3)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.

7. OUTPUT DATA MUTING

The GS9035A internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO

/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data. The output data muting timing is
shown in Figure 14.

Fig. 14 Output Data Muting Timing

8. CLOCK ENABLE

When CLK_EN is high, the GS9035A SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO

/SCO outputs are

set to a high Z state and float to V

CC

. Disabling the clock
outputs results in a power savings of 10%. It is
recommended that the CLK_EN input be hard wired to the
desired state. For applications which do not require the
clock output, connect CLK_EN to Ground and connect the
SCO

/SCO outputs to VCC.

9. STRESSFUL DATA PATTERNS

All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of zeros or
ones (low data transition densities for a long period of time).
The GS9035A is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).

10. PLL DESIGN GUIDELINES

The performance of the GS9035A is primarily determined
by the PLL. Thus, it is important that the system designer is
familiar with the basic PLL design equations.

TABLE 4: Lock Time Relative to Switching Time

SWITCHING TIME LOCK TI ME

<0.5µs 10µs

0.5µs - 10ms 2t

sys

> 10ms 2T

cycle

+ 2t

sys

LOCK

DDI

SDO

VALID
DATA

NO DATA TRANSITIONS

VALID
DATA

OUTPUTS MUTED

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GS9035A

A model of the GS9035A PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.

Fig. 15 PLL Model

10.1. Transfer Function

The transfer function of the PLL is defined as Øo/Øi and can
be approximated as

Equation 1

where

N is the divider modulus

D is the data density (=0.5 for NRZ data)

Ι

CP

is the charge pump current in Amps

K

ƒ

is the VCO gain in Hz/V

This response has 1 zero (w

Z

) and three poles (wP1, wBW,

w

P2

) where

The bode plot for this transfer function is plotted in Figure

16.

Fig. 16 Bode Plot for PLL Transfe r Funct ion

The 3dB bandwidth of the transfer function is approximately

10.2. Transfer Function Peaking

There are two causes of peaking in the PLL transfer function
given by Equation 1.

The first is the quadratic

which has

and

This response is critically damped for Q = 0.5.

Thus, to avoid peaking:

or

Therefore,

w

P2

> 4 w

BW

However, it is desirable to keep wP2 as low as possible to
reduce the high frequency content on the loop filter.

LOOP

FILTER

Ø

i

Ø

o

VCO

Ι

CP

R

LF

K

PD

C

LF1

C

LF2

PHASE

DETECTOR

2πK

f

+

-

N

s

Ø

o

Ø

i

-------

sC

LF1RLF

1+

sC

LF1RLF

L

R

LF

--------- -–





1+

--------------------------------------------------------------- -

1

s

2

C

LF2

Ls

L

R

LF

-------- -

1++

---------------------------------------------------------

=

L

N

DI

CPKƒ

------------------- -=

w

Z

1

C

LF1RLF

-----------------------=

w

P1

1

C

LF1RLF

L

R

LF

---------–

---------------------------------------=

w

BW

R

LF

L

-------- -=

w

P2

1

C

LF2RLF

-----------------------=

W

Z

0

W

P1

W

BW

W

P2

FREQUENCY

AMPLITUDE (dB)

w

3dB

w

BW

12

w

BW

w

P2

------------

–

wBWw

P2

⁄()

2

12

w

BW

w

P2

----------- -

–

----------------------------------+

----------------------------------------------------------------------

w

BW

0.78

------------

≈=

s2C

LF2

Ls

L

R

LF

---------

1++

w

O

1

C

LF2

L

--------------------=

QR

LF

C

LF2

L

-------------=

R

LF

C

LF2

L

-------------

1
2

-- -

<

1

R

LFCLF2

-----------------------

L

R

LF

---------

4>

GENNUM CORPORATION

522 - 41- 04

11

GS9035A

The second is the zero-pole combination:

This causes lift in the transfer function given by

To keep peaking to less than 0.05dB,

w

Z

< 0.0057 w

BW

10.3. Selection of Loop Filter Components

Based on the above analysis, select the loop filter
components for a given PLL bandwidth, ƒ

3dB

, as follows:

1. Calculate

where

Ι

CP

is the charge pump current and is a function of the

R

VCO

resistor and is obtained from Figure 17.

K

ƒ

= 90MHz/V for VCO frequencies corresponding to

the ƒ

L

curve.

K

ƒ

= 140MHz/V for VCO frequencies corresponding to

the ƒH curve.

N is the divider modulus.

(ƒL, ƒH and N can be obtained from Table 2 or Table 3).

2. Choose R

LF

= 2(3.14) ƒ

3dB

(0.78)L

3. Choose C

LF1

= 174 L / (RLF)

2

4. Choose C

LF2

= L/4(RLF)

2

Fig. 17 Charge Pump Current vs. R

VCO

10.4. Spice Simulations

More detailed analysis of the GS9035A PLL can be done
using SPICE. A SPICE model of the PLL is shown below:

Fig. 18 SPICE Model of PLL

The model consists of a voltage controlled current source
(G1), the loop filter components (R

LF

, C

LF1

, and C

LF2

), a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.

V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, Ι

CP

. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2pK

ƒ

/Ns).

The netlist for the model is given below. The .PARAM
statements are used to set values for Ι

CP

, K

ƒ

, N, and D. Ι

CP

is determined by the R

VCO

resistor and is obtained from

Figure 17.

sC

LF1RLF

1+

sC

LF1RLF

L

R

LF

---------- -–





1+

-----------------------------------------------------------

s

w

Z

------ - 1+

s

w

P1

---------- 1+

--------------------=

20 LOG

w

P1

w

Z

--------- -

20 LOG

1

1

w

Z

w

BW

------------–

---------------------

=

L

2N

I

CPKƒ

---------------=

0

50

100

150

200

250

300

350

400

0 200 400 600 800 1000 1200 1400 1600 1800

CHARGE PUMP CURRENT (µA)

R

VCO

(Ω)

PHII

PHIO

R2

E1

R

LF

C

LF1

C

LF2

G1

V1

2πK

ƒ

IN+

IN-

Ns

1

LF

NOTE: PHII, PHIO, LF and 1 are node names in the SPICE netlist.

GENNUM CORPORATION

522 - 41- 04

12

GS9035A

SPICE NETLIST * GS9035A PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R2 0 1 1g
.END

11. I/O DESCRIPTION

11.1. High Speed Inputs (DDI/DDI

)

DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:

1. Input signal amplitudes are between 200 and 2000mV

2. The common mode input voltage range is as specified
in the DC Characteristics table.

Commonly used interface examples are shown in
Figures 19 and 20.

Figure 19 illustrates the simplest interface to the GS9035A.
In this example, the driving device generates the PECL
level signals (800mV amplitudes) having a common mode
input range between 0.4 and 4.6V. This scheme is
recommended when the trace lengths are less than 1in. The
value of the resistors and the DC connection (V

CC

or
Ground), depends on the output driver circuitry of the
previous device.

Fig. 19 Simple Interface to the GS9035A

When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface for differential signals is shown in Figure 20. In this
case, a parallel resistor (R

LOAD

) is placed near the GS9035A
inputs to terminate the controlled impedance trace. The
value of R

LOAD

should be twice the value of the

characteristic impedance of the trace. Both traces should

be in a symmetric arrangement and same physical
transmission line dimensions since common-mode signals
or common-mode noise is not terminated. In addition,
series resistors, R

SOURCE

, can be placed near the driving
chip to serve as source terminations. They should be equal
to the value of the trace impedance. Assuming 800mV
output swings at the driver, R

LOAD

=100Ω, R

SOURCE

=50Ω

and Z

O

= 50Ω.

Fig. 20 Recommended Interface for Differential Signals

Figure 21 shows the recommended interface when the
GS9035A is driven single-endedly. In this case, the input
must be AC-coupled and a matching resistor (Z

O

) must be

used.

Fig. 21 Recommended Interface for Single-Ended Driver

11.2. High Speed Outputs (SDO

/SDO and SCO/SCO)

SDO/SDO and SCO/SCO are current mode outputs that
require external pullups (

see Figure 22

). Note that no

external pull-ups are required when used with the GS9020.
The output signal swings are 800mV when 75Ω resistors are
used. A diode can be placed between V

CC

and the pullups
to shift the signal levels down by approximately 0.7 volts.
When the output traces are longer than 1in, controlled
impedance traces should be used. The pullup resistors
should be placed at the end of the output traces as they
terminate the trace in its characteristic impedance (75Ω).

Fig. 22 High Speed Outputs with External Pullups

DDI

DDI

V

CC

or GND

V

CC

or GND

GS9035A

DDI

DDI

R

SOURCE

R

LOAD

R

SOURCE

Z

O

Z

O

GS9035A

DDI

DDI

Z

O

GS9035A

V

CC

SDO
SDO

SCO
SCO

75Ω75Ω

V

CC

75Ω 75Ω

GS9035A

GENNUM CORPORATION

522 - 41- 04

13

GS9035A

TYPICAL APPLICATION CIRCUIT

The figure below shows the GS9035A connected in a typical auto rate select SMPTE 259M application. Table 4 summarizes
the relevant system parameters.

TABLE 5: System Parameters

R

VCO

= 365Ω, ƒH = 540MHz, ƒL = 360MHz

SMPTE SS[2:0] DATA RATE (M b/s) LOOP BANDWIDTH

1 000 143 1.2MHz

1 001 177 1.9MHz

1 010 270 3.0MHz

1 011 360 4.5MHz

1 100 540 6.0MHz

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

4 x 75

To
GS9020

1

To LED
Driver
(optional)

10k

1800

15n

3.3p

4.7n

0.1µ

0.1µ

}

From
GS9024

R

VCO

R

LFCLF1

C

LF2

DDI

DDI

V

EE

V

EE

V

CC1

AUTO/MAN

V

EE

SMPTE

LOCK

COSC

V

EE

CLK_EN

V

EE

V

CC3

GS9035A

TOP VIEW

LF+

LFS

LF-

R

VCO

_RTN

R

VCO

CBG

V

CC2

25

24

23

22

21

20

19

5

6

7

8

9

10

11

12 13 14 15 16 17 18

4 3 2 1 28 27 26

SDO

SDO

SCO

SCO

SSO

SS1

SS2

All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
Power supply decoupling
capacitors are not shown.
See application note "EB9035A"
for details on PCB artwork.

NOTE

1. The 75Ω pullup resistors on SDO/SDO and
SCO/SCO are not required when interfacing
the GS9035A to the GS9020 since the GS9020
has internal 75Ω resistors.

365
(1%)

522 - 41- 04

14

GENNUM CORPORATION

MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. [phone] Fax. [phone]

SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5

GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. [phone] Fax. [phone]

GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. [phone] Fax [phone]

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.

© Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada.

GS9035A

PACKAGE DIMENSIONS

12.319

MIN

11.582 MAX

11.430 MIN

12.573

MAX

1.270

x 45

1.219

1.067

SEATING

PLANE

MIN 0.508

4.572 MAX

4.115 MIN

3.048 MAX

2.286 MIN

11.582 MAX

11.430 MIN

12.319

MIN

12.573

MAX

10.922 MAX

9.906 MIN

All dimensions in millimetres.
28 pin PLCC (QM)

REVISION NOTES:

Clarified symbols for pin numbers 22, 23, 24, and 25.

For latest product information, visit www.gennum.com

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STATIC-FREE WORKSTATION

DOCUMENT IDENTIFICATION

DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.