Datasheet GS9025-CTM, GS9025-CQM Datasheet (Gennum Corporation)

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

Revision Date: November 2000 Document No. 521 - 63 - 05

PRELIMINARY DATA SHEET

GS9025

FEATURES

• SMPTE 259M compliant

• operational to 540Mb/s

• automatic cable equalization (typically greater than
350m of high quality cable at 270Mb/s)

• adjustment-free operation

• auto-rate selection (5 rates) with manual override

• single external VCO resistor for operation with five
input data rates

• data rate indication output

• system friendly: serial data outputs muted and serial
clock remains active when input data is lost

• operation independent of SAV/EAV sync signals

• signal strength indicator output

• output 'eye' monitor (OEM ) with large sig nal amplitude
and power down option

• carrier detect with programmable threshold level

• power savings mode (output serial clock disable)

• 44 pin MQFP

APPLICATIONS

Cable equalization plus clock and data recovery for all high
speed serial digital interface applications involving SMPTE
259M and other data standards.

DESCRIPTION

The GS9025 provides automatic cable equalization and
high performance clock and data recovery for serial digital
signals. The GS9025 receives either single-ended or
differential serial digital data and outputs differential clock
and retimed data signals at PECL levels (800mV). The on­board cable equalizer provides up to 40dB of gain at
200MHz which typically results in equalization of greater
than 350m of high quality cable at 270Mb/s.

The GS9025 operates in either auto or manual data rate
selection mode. In both modes, the GS9025 requires only
one external resistor to set the VCO centre frequency and
provides adjustment free operation.

The GS9025 has dedicated pins to indicate signal
strength/carrier detect, LOCK and data rate. Optional
external resistors allow the carrier detect threshold level to
be customized to the user's requirement. In addition, the
GS9025 provides an 'Output Eye Monitor' (OEM) which
allows the verification of signal integrity after equalization,
prior to reslicing. The serial clock outputs can be disabled
to reduce power consumption. The GS9025 operates from a
single +5 or -5 volt supply.

BLOCK DIAGRAM

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS9025-CQM 44 pin MQFP Tray 0°C to 70°C

GS9025-CTM 44 pin MQFP Tape 0°C to 70°C

LF+ LFS LF- CBG R

VCO

CARRIER DETECT

PHASELOCK

HARMONIC

FREQUENCY
ACQUISITION

VCO

DIVISION

3 BIT

COUNTER

LOCK

SDO

SDO

CLK_EN

SCO

SCO

SMPTE

AUTO/MAN

SS0
SS1
SS2

MUTE

COSC

A/D

PHASE

DETECTOR

DECODER

LOGIC

ANALOG

DIGITAL

MUX

DDI

+

-

DDI

SDI
SDI

OEM

AGC CAP CD_ADJ

AUTO EQ

CONTROL

EYE

MONITOR

VARIABLE

GAIN EQ

STAGE

CHARGE

PUMP

+

-

+ -

SSI/CD

GENLINX

™

II

GS9025

Serial Digital Receiver

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GS9025

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage (V

S

)5.5V

Input Voltage Range (any input) V

CC

+0.5 to VEE-0.5V

Operating Temperature Range 0°C ≤ T

A

≤ 70°C

Storage Temperature Range -65°C ≤ T

S

≤ 150°C

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0v, VEE = 0V, TA = 0°C to 70°C unless otherwise shown.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

TEST

LEVEL

Supply Voltage V

CC

4.75 5.0 5.25 V 1

Supply Current

Ι

S

CLK_EN = 0 - 115 - mA 1

CLK_EN = 1 - 125 - mA 1

CLK_EN = 0,
OEM active

- 135 - mA 1

CLK_EN = 1,
OEM active

- 145 - mA 1

SDI/SDI

Common Mode

Volta ge

-2.5-V 1

DDI/DDI

Common
Mode Input Voltage
Range

VEE+(V

DIFF

/2) 0.4 to 4.6 VCC-(V

DIFF

/2) V 1 1

DDI/DDI

Differential
Drive

200 800 2000 mV 1

AGC+/AGC- Common
Mode Voltage

-2.7-V 1

OEM Bias Potential - 4.5 - V

SSI/CD Output Current V

SSI/CD

= 2.4V - +120 - µA 3

V

SSI/CD

= 0.4V (Muted) - -1.0 - mA

AUTO/MAN

,
SMPTE,
SS[2:0] Input
Volta ge

High 2.0 - - V 3 1

Low - - 0.8 V

CLK_EN Input
Volta ge

High 2.5 - - V 1

Low - - 0.8 V

LOCK Output Sink
Current

500 - - µA 4 1

SS[2:0] Output
Volta ge

High 4.4 4.7 - V 3 1

Low - 0.2 0.4 V

SS[2:0] Source Current Auto Mode 180 300 - µA 3 1

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GS9025

Fig. 1 Test Setup for Figures 6 - 11

SS[2:0] Sink Current Auto Mode 0.6 1 - mA 3 1

SS[2:0] Source Current Manual Mode - - 0 µA 3 1

SS[2:0] Sink Current Manual Mode - 0.8 5 µA 3 1

NOTES

1. V

DIFF

is the differential input signal swing.

2. See DESCRIPTION.

3. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode.

4. LOCK is an open collector output and requires an external pullup resistor.

TEST LEVELS

1. 100% tested at 25°C.

2. Guaranteed by design.

3. Inferred or correlated value.

AC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, VEE = 0V, TA = 0°C to 70°C unless otherwise shown. RLF = 1kΩ, C

LF1

= 15nF, C

LF2

= 5.6pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

TEST

LEVELS

Data Rate 143 - 540 Mb/s 1

Maximum Equalizer Gain at 200MHz - 40 - dB

Additive Jitter t

J

270Mb/s, 300m - 300 - ps p-p see Figs

7-11

1

540Mb/s, 100m - 275 - ps p-p

Jitter Transfer Function
Peaking

--0.1dB 2

Frequency Drift when PLL
loses lock

-±15 % 2

Lock Time Synchronous
Switch

t

SWITCH

< 0.5µs,

270Mb/s

-1- µs 1 2

0.5µs<t

SWITCH

<10ms - 1 - ms

t

SWITCH

> 10ms - 4 - ms

Lock Time Asynchronous
Switch

-10- ms 2 2

SDO

/SDO, SCO/SCO Output

Signal Swing

75Ω DC Load 600 800 1000 mVp-p 3 1

SDO to SCO Synchronization -200 0 200 ps 2

SDO

/SDO, SCO/SCO Rise &

Fall Times

20 - 80%, TA =25°C 200 300 400 ps 2

NOTES

1. Synchronous switching refers to switching the input data from one source to another

source which is at the same data rate (ie: line 10 switching for component NTSC).

2. Asynchronous switching refers to switching the input data from one source to another

source which is at a different data rate.

3. Assuming 75Ω pullup resistors on SDO

/SDO and SCO/SCO.

TEST LEVELS

1. 100% tested at 25°C.

2. Guaranteed by design.

3. Inferred or correlated value.

4. Evaluated using test setup Figure 1.

DC ELECTRICAL CHARACTERISTICS (Continued)

VCC = 5.0v, VEE = 0V, TA = 0°C to 70°C unless otherwise shown.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

TEST

LEVEL

EB9025
BOARD

GS9028

CABLE

DRIVER

TEKTRONIX

GigaBERT

1400

ANALYZER

TEKTRONIX

GigaBERT

1400

TRANSMITTER

BELDEN 8281

CABLE

DATA

DATA

CLOCK

TRIGGER

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GS9025

PIN CONNECTIONS

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1, 2 DDI/DDI

I Digital data inputs (Differential ECL/PECL).

3, 44 V

CC

_75 I Power supply connection for internal 75Ω pullup resistors connected to DDI/DDI.

4, 8, 13, 22, 35 V

CC

I Most positive power supply connection.

5, 9, 14, 18, 27,

30, 33, 34, 37

V

EE

I Most negative power supply connection.

6, 7 SDI/SDI

I Differential analog data inputs.

10 CD_ADJ I Carrier detect threshold adjust.

11, 12 AGC-, AGC+ I External AGC capacitor.

15 LF+ I Loop filter component connection.

16 LFS I Loop filter component connection.

17 LF- I Loop filter component connection.

19 R

VCO

_RTN I Frequency setting resistor return connection.

20 R

VCO

I Frequency setting resistor connection.

21 CBG I Internal bandgap voltage filter capacitor.

23, 24, 25 SS[2:0] I/O Data rate indication (auto mode) or data rate select (manual mode). TTL/CMOS

compatible I/O. In auto mode these pins can be left unconnected.

26 AUTO/MAN

I Auto or manual mode select. TTL/CMOS compatible input.

DDI
DDI

V

CC

_75

V

CC

V

EE

SDI
SDI

V

CC

V

EE

CD_ADJ

AGC-

SDO
SDO
V

EE

SCO
SCO
V

EE

AUTO/MAN
SS0

SS1
SS2

GS9025

TOP VIEW

AGC+

V

CC

V

EE

LF+

LFS

LF-

V

EE

R

VCO

_RTN

R

VCO

CBG

V

CC

V

CC

_75

OEM

SMPTE

A/D

SSI/CD

LOCK

COSC

V

EE

CLK_EN

V

CC

V

EE

V

EE

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

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28, 29 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require

external 75Ω pullup resistors.

31, 32 SDO

/SDO O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current

mode outputs and require external 75Ω pullup resistors.

36 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled.

38 COSC I Timing control capacitor for internal system clock.

39 LOCK O Lock indication. When HIGH, the GS9025 is locked. LOCK is an open collector output

and requires an external 10kΩ pullup resistor.

40 SSI/CD O Signal strength indicator/Carrier detect.

41 A/D

I Analog/Digital select.

42 SMPTE I SMPTE/Other data rate select. TTL/CMOS compatible input.

43 OEM O Output ‘Eye’ monitor. OEM is a single ended current mode output and requires an

external 50Ω pullup resistor.

PIN DESCRIPTIONS (Continued)

NUMBER SYMBOL TYPE DESCRIPTION

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GS9025

TYPICAL PERFORMANCE CURVES

(V

S

= 5V, TA = 25°C unless otherwise shown)

Fig. 2 SSI/CD Voltage vs. Cable Length

(Belden 8281)(CD_ADJ = 0V)

Fig. 4 Carrier Detect Adjust Voltage Threshold Characteristics

Fig. 6 Error Free Cable Length vs. Data Rate

Fig. 3 Equalizer Gain vs. Frequency

Fig. 5 Input Impedance

Fig. 7 Additive Jitter vs. Input Cable Length (Belden 8281)

0 50 100 150 200 250 300 350 400 450 500

5.00

4.50

4.00

3.50

3.00

2.50

CABLE LENGTH (m)

SSI/CD OUTPUT VOLTAGE (V)

5.0

4.5

4.0

3.5

3.0

2.5

2.0
200 250 300 350 400

CABLE LENGTH (m)

CD_ADJ VOLTAGE (V)

150

200

250

300

350

400

450

90 180 270 360 450 540 630

TYPICAL ERROR FREE CABLE LENGTH (m)

DATA RATE (Mb/s)

0

5

10

15

20

25

30

35

40

45

50

1 10 100 1000

GAIN (dB)

FREQUENCY (MHz)

270

j1

3000

1620

810

-j1

-j2

-j5

j5

j2

j0.2

-j0.2

-j0.5

j0.5

Frequencies in MHz, impedances normalized to 50Ω

0

50

100

150

200

250

300

350

400

450

0

100 200 300

400

ADDITIVE JITTER p-p (ps)

CABLE LENGTH (m)

540Mb/s

270Mb/s

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GS9025

Fig. 8 Output Jitter (143Mb/s, 300m)

Fig. 10 Output Jitter (360Mb/s, 300m)

Fig. 9 Output Jitter (270Mb/s, 300m)

Fig. 11 Output Jitter (540Mb/s, 100m)

DETAILED DESCRIPTION

The GS9025 Serial Digital Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and reclocker.

Serial digital signals are applied to either the analog
SDI/SDI

or digital DDI/DDI inputs. Signals applied to the

SDI/SDI

inputs are equalized and then passed to a

multiplexer. Signals applied to the DDI/DDI

inputs bypass
the equalizer and go directly to the multiplexer. The
analog/digital select pin (A/D

) determines which signal is

then passed to the reclocker.

Packaged in a 44 pin MQFP, the receiver operates from a
single 5V supply to data rates of 540Mb/s. Typical power
consumption is 575mW.

1. CABLE EQUALIZER

The automatic cable equalizer is designed to equalize
serial digital data signals between 30Mb/s and 540Mb/s.

The serial data signal is connected to the input pins
(SDI/SDI

) either differentially or single ended. The input
signal passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. In addition, the variation of the
frequency response with control voltage imitates the

variation of the inverse cable loss characteristic with cable
length. The gain stage provides up to 40dB of gain at
200MHz which typically results in equalization of greater
than 350m at 270Mb/s of Belden 8281 cable.

The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.

The equalized signal is DC restored, thereby restoring its
logic threshold to its corrective level regardless of shifts due
to AC coupling.

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GS9025

2. SIGNAL STRENGTH INDICATION/CARRIER DETECT

The GS9025 incorporates an analog signal strength
indicator/carrier detect (SSI/CD) output indicating both the
presence of a carrier and the amount of equalization
applied to the signal. The voltage output of this pin versus
cable length (signal strength) is shown in Figures 2 and 12.

With 0m of cable (800mV input signal levels), the SSI/CD
output voltage is approximately 4.5V. As the cable length
increases, the SSI/CD voltage decreases linearly providing
accurate correlation between the SSI/CD voltage and cable
length.

Fig. 12

When the signal strength decreases to the level set at the
"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage
goes to a logic "0" state (0.8 V) and can be used to drive
other TTL/CMOS compatible logic inputs. In addition, when
loss of carrier is detected the SDO

/SDO outputs are muted

(set to a known static state).

3. CARRIER DETECT THRESHOLD ADJUST

This feature has been designed for use in applications such
as routers where signal crosstalk and circuit noise cause
the equalizer to output erroneous data when no input signal
is present. The use of a Carrier Detect function with a fixed
internal reference does not solve this problem since the
signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set
by the on chip reference. To alleviate this problem, the
GS9025 provides a user adjustable threshold to meet the
unique conditions that exist in each user's application.
Override and internal default settings have also been
provided to give the user total flexibility.

The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin. The
control voltage at the CD_ADJ pin is set by a simple resistor
divider circuit (

see Typical Application Circuit

). The
threshold level is adjustable from 200m to 350m. By default
(no external resistors), the threshold is typically 320m. In

noisy environments, it is not recommended to leave this pin
floating. Connecting this pin to V

EE

disables the SDO/SDO
muting function and allows for maximum possible cable
length equalization.

4. OUTPUT EYE MONITOR

The GS9025 also provides an 'Output Eye Monitor' (OEM)
which allows the verification of signal integrity after
equalization, prior to reslicing. The OEM pin is an open
collector current output that requires an external 50Ω pullup
resistor. When the pullup resistor is not used, the OEM
block is disabled and the internal OEM circuit is powered
down. The OEM provides a 100mVp-p

signal when driving a

50Ω oscilloscope input.

5. RECLOCKER

The reclocker receives a differential serial data stream from
the internal multiplexer. It locks an internal clock to the
incoming data and outputs the differential PECL retimed
data signal and recovered clock on outputs SDO

/SDO and

SCO

/SCO, respectively. The timing between the output and

clock signals is shown below.

Fig. 13

The reclocker contains four main functional blocks: the
Phase Locked Loop, Frequency Acquisition, Logic Circuit,
and Auto/Manual Data Rate Select.

5.1. Phase Locked Loop (PLL)

The Phase Locked Loop locks the internal PLL clock to the
incoming data rate. A simplified block diagram of the PLL is
shown below. The main components are the VCO, the
phase detector, the charge pump, and the loop filter.

0

1

2

3

4

5

50

100

150 200 250 300 350 400 450

500

SSI/CD OUTPUT VOLTAGE (V)

CABLE LENGTH (m)

0

CD_ADJ
CONTROL RANGE

SDO

SCO

50%

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GS9025

Fig. 14

5.1.1. VCO

The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO center frequency. The VCO
operates between 30 and 540Mb/s and has a pull range of
±15% about the center frequency. A single low impedance
external resistor, R

VCO

, sets the VCO center frequency (

see

Figure 15

). The low impedance R

VCO

minimizes thermal

noise and reduces the PLL's sensitivity to PCB noise.

For a given R

VCO

value, the VCO can oscillate at one of two
frequencies. When SMPTE = SS0 = logic 1, the VCO center
frequency corresponds to the ƒ

L

curve. For all other SMPTE/
SS0 combinations, the VCO center frequency corresponds
to the ƒ

H

curve (ƒ

H

is approximately 1.5 x ƒL).

Fig. 15

The recommended R

VCO

value for auto rate SMPTE 259M

applications is 365Ω.

The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN

, SMPTE, and SS[2:0] pins

(see

Auto/Manual Data Rate Select section for further details)

. In
addition, a manually selectable modulus 8 divider allows
operation at data rates as low as 30Mb/s.

5.1.2. Phase Detector

The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function between the input phase
and output timing pulses maximizing the input jitter
tolerance of the PLL.

5.1.3. Charge Pump

The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design insures that the output phase does not drift when
data transitions are sparse. This makes the GS9025 ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.

5.1.4. Loop Filter

The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9025 increased immunity to
PCB board noise.

The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL DESIGN
GUIDELINES section. Recommended values for
SMPTE259M applications are shown in the Typical
Application Circuit.

5.2. Frequency Acquisition

The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9025 uses a frequency acquisition circuit.

The frequency acquisition circuit sweeps the VCO control
voltage such that the VCO frequency changes from

-10% to +10% of the center frequency. Figure 16 shows a
typical sweep waveform.

DDI/DDI

LF+

LFS

LF-

R

VCO

VCO

DIVISION

RLFC

LF1

C

LF2

2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

LOOP
FILTER

0

100

200

300

400

500

600

700

800

0 200 400 600 800 1000 1200 1400 1600 1800

VCO REQUENCY (MHz)

R

VCO

(Ω)

ƒ

H

ƒ

L

SMPTE=1
SSO=1

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GS9025

Fig. 16

The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 3-bit counter.

The average sweep time, t

swp

, is determined by the loop

filter component, C

LF1

, and the charge pump current, Ι

CP

:

The nominal sweep time is approximately 121µs when
C

LF1

= 15nF and Ι

CP

= 165µA (R

VCO

= 365Ω).

An internal system clock determines t

sys

(see the Logic

Circuit section)

.

5.3. Logic Circuit

The GS9025 is controlled by a finite state logic circuit which
is clocked by an asynchronous system clock. That is, the
system clock is completely independent of the incoming
data rate. The system clock runs at low frequencies, relative
to the incoming data rate, and thus reduces interference to
the PLL.The period of the system clock is set by the COSC
capacitor and is:

The recommended value for t

sys

is 450µs (COSC = 4.7nF)

5.4. Auto/Manual Data Rate Select

The GS9025 can operate in either auto or manual data rate
select mode. The mode of operation is selected by a single
input pin (AUTO/MAN

).

5.4.1. Auto Mode (AUTO/MAN = 1)

In auto mode, the GS9025 uses a 3-bit counter to
automatically cycle through five (SMPTE=1) or three
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[2:0] pins are outputs and indicate
the current value of the divider moduli according to the
table below. Note that for SMPTE = 0 and divider moduli of
2 and 4, the PLL can correctly lock for two values of
SS[2:0].

5.4.2. Manual Mode (AUTO/MAN = 0)

In manual mode, the GS9025 divider moduli is fixed. In this
mode, the SS[2:0] pins are inputs and set the divider moduli
according to Table 2.

6. LOCKING

The GS9025 indicates lock when three conditions are
satisfied:

1. input data is detected

2. the incoming data signal and the PLL clock are phase

locked

3. the system is not locked to a harmonic

V

LF

t

swp

T

cycle

T

cycle

= t

swp

+ t

sys

t

sys

A

t

swp

4 C

LF1

3I

CP

---------------- -=

t

sys

9.6 10

4

COSC [seconds]××

=

TABLE 1

AUTO/MAN

= 1 (AUTO MODE)

ƒ

H

, ƒL = VCO center frequency as per figure 15.

SMPTE SS[2:0]

DIVIDER

MODULI

PLL CLOCK

1 000 4 ƒ

H

/4

1 001 2 ƒ

L

/2

1 010 2 ƒ

H

/2

1 011 1 ƒ

L

1 100 1 ƒ

H

1 101 - -

1 110 - -

1 111 - -

0 000 4 ƒ

H

/4

0 001 4 ƒ

H

/4

0 010 2 ƒ

H

/2

0 011 2 ƒ

H

/2

0 100 1 ƒ

H

0 101 - -

0 110 - -

0 111 - -

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GS9025

The GS9025 defines the presence of input data when at
least one data transition occurs every 1µs.

The GS9025 assumes that it is NOT locked to a harmonic if
the pattern ‘101’ or ‘010’ (in the reclocked data stream)
occurs at least once every t

sys

/3 seconds. Using the
recommended component values, this corresponds to
approximately 150µs. (In an harmonically locked system, all
bit cells are double clocked and the above patterns
become ‘110011’ and ‘001100’, respectively.)

7. LOCK TIME

The lock time of the GS9025 depends on whether the input
data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data to the
GS9025 is changed from one source to another source
which is at a different data rate.

When input data to the GS9025 is removed, the GS9025
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9025 begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9025 locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the table below:

In asynchronous switching applications (including power
up) the lock time is determined by the frequency acquisition
circuit as described above. In manual mode, the frequency
acquisition circuit may have to sweep over an entire cycle
(depending on initial conditions) to acquire lock resulting in
a maximum lock time of 2T

cycle

+ 2t

sys

. In auto tune mode,

the maximum lock time is 6T

cycle

+ 2t

sys

since the frequency
acquisition circuit may have to cycle through 5 possible
counter states (depending on initial conditions) to acquire
lock. The nominal value of T

cycle

for the GS9025 operating in

a typical SMPTE 259M application is approximately 1.3ms.

The GS9025 has a dedicated LOCK output (pin 39)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5µs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.

8. OUTPUT DATA MUTING

The GS9025 internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO

/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data.

The output data muting timing is shown in Figure 17.

Fig. 17

TABLE 2

AUTO/MAN

= 1 (MANUAL MODE)

ƒ

H

, ƒL = VCO center frequency as per figure 15.

SMPTE SS[2:0]

DIVIDER

MODULI

PLL CLOCK

1 000 4 ƒ

H

/4

1 001 2 ƒ

L

/2

1 010 2 ƒ

H

/2

1 011 1 ƒ

L

1 100 1 ƒ

H

1 101 8 ƒL/8

1 110 8 ƒ

H

/8

1 111 - -

0 000 4 ƒ

H

/4

0 001 4 ƒ

H

/4

0 010 2 ƒ

H

/2

0 011 2 ƒ

H

/2

0 100 1 ƒ

H

0 101 1 ƒ

H

0 110 8 ƒH/8

0 111 - -

TABLE 3

SWITCHING TIME LOCK TIME

< 0.5µs 10µs

0.5µs - 10ms 2t

sys

> 10ms 2T

cycle

+ 2t

sys

LOCK

DDI

SDO

VALID
DATA

NO DATA TRANSITIONS

VALID
DATA

OUTPUTS MUTED

GENNUM CORPORATION

521 - 63 - 05

12

GS9025

9. CLOCK ENABLE

When CLK_EN is high, the GS9025 SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO

/SCO outputs are

tri-stated and float to V

CC

. Disabling the clock outputs
results in a power savings of 10%. It is recommended that
the CLK_EN input be hard wired to the desired state. For
applications which do not require the clock output, CLK_EN
should be connected to Ground and the SCO

/SCO outputs

should be connected to V

CC

.

10. STRESSFULL DATA PA TTERNS

All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS9025 has been designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).

11. PLL DESIGN GUIDELINES

The reclocking performance of the GS9025 is primarily
determined by the PLL. Thus, it is important that the system
designer is familiar with the basic PLL design equations.

A model of the GS9025 PLL is shown below. The main
components are the phase detector, the VCO, and the
external loop filter components.

Fig. 18

11.1. Transfer Function

The transfer function of the PLL is defined as Øo/Øi and can
be approximated as:

Equation 1

where and

N is the divider modulus

D is the data density (=0.5 for NRZ data)

I

CP

is the charge pump current in Amps

K

ƒ

is the VCO gain in Hz/V

This response has 1 zero (w

Z

) and three poles

(w

P1,wBW,wP2

) where:

The bode plot for this transfer function is plotted in Figure

19.

Fig. 19

The 3dB bandwidth of the transfer function is
approximately:

11.2. Transfer Function Peaking

There are two causes of peaking in the PLL transfer function
given by Equation 1.

The first is quadratic:

which has:

and

This response is critically damped for Q = 0.5.

LOOP

FILTER

Ø

i

Ø

o

VCO

Ι

CP

R

LF

K

PD

C

LF1

C

LF2

PHASE

DETECTOR

2 π K

ƒ

+

­ Ns

Ø

o

Ø

i

-------

sC

LF1RLF

1+

sC

LF1RLF

L

R

LF

---------–





1+

----------------------------------------------------------------

1

s

2

C

LF2

Ls

L

R

LF

---------

1++

---------------------------------------------------------

=

L

N

DICPK

ƒ

--------------------=

w

Z

1

C

LF1RLF

-----------------------=

w

P1

1

C

LF1RLF

L

R

LF

---------–

---------------------------------------=

w

BW

R

LF

L

---------=

w

P2

1

C

LF2RLF

---------------------- -=

WZW

P1

W

BW

W

P2

FREQUENCY

AMPLITUDE

w

3dB

w

BW

12

w

BW

w

P2

------------

–

wBWw

P2

⁄()

2

12

w

BW

w

P2

------------

–

----------------------------------+

----------------------------------------------------------------------

w

BW

0.78

------------

≈=

s2C

LF2

Ls

L

R

LF

---------

1++

w

o

1

C

LF2

L

--------------------=

QR

LF

R

LF2

L

----------- -=

GENNUM CORPORATION

521 - 63 - 05

13

GS9025

Thus, to avoid peaking:

or

Therefore,

w

P2

> 4 w

BW

However, it is desirable to keep wP2 as low as possible to
reduce the high frequency content on the loop filter.

The second is the zero-pole combination:

This causes lift in the transfer function given by:

To keep peaking to less than 0.05dB:

w

Z

< 0.0057w

BW

11.3. Selection of Loop Filter Components

Based on the above analysis, the loop filter components
should be selected for a given PLL bandwidth, ƒ

3dB

, as

follows:

1. Calculate

where:

ICP is the charge pump current and is a function of the
R

VCO

resistor and is obtained from Figure 21.

K

ƒ

= 90MHz/V for VCO frequencies corresponding to

the ƒ

L

curve.

K

ƒ

= 140MHz/V for VCO frequencies corresponding to

the ƒH curve.

N is the divider modulus

(ƒL, ƒH and N can be obtained from Table 1 or Table 2)

2. Choose R

LF

= 2(3.14)ƒ

3dB

(0.78)L

3. Choose C

LF1

= 174L/(RLF)

2

4. Choose C

LF2

= L/4(RLF)

2

Fig. 20

11.4. SPICE Simulations

More detailed analysis of the GS9025 PLL can be done
using SPICE. A SPICE model of the PLL is shown below:

Fig. 21

The model consists of a voltage controlled current source
(G1), the loop filter components (R

LF

, C

LF1

, and C

LF2

) a
voltage controlled voltage source (E1), and a voltage
source (V1). R2 is necessary to create a DC path to ground
for Node 1.

V1 is used to generate the input phase waveform. G1
compares the input and output phase waveforms and
generates the charge pump current, Ι

CP

. The loop filter
components integrate the charge pump current to establish
the loop filter voltage. E1 creates the output phase
waveform (PHIO) by multiplying the loop filter voltage by
the value of the Laplace transform (2πK

ƒ

/Ns).

The net list for the model is given below. The .PARAM
statements are used to set values for Ι

CP

, K

ƒ

, N, and D. Ι

CP

is determined by the R

VCO

resistor and is obtained from

Figure 20.

R

LF

C

LF2

L

------------ -

1
2

---

<

1

R

LF2CLF2

------------------------- -

L

R

LF

---------

4>

sC

LF1RLF

1+

sC

LF1RLF

1

R

LF

---------–





1+

----------------------------------------------------------

s

w

Z

------- 1+

s

w

P1

---------- 1+

--------------------=

20 LOG

w

P1

w

Z

----------

20 LOG

1

1

w

Z

w

BW

----------- -–

---------------------

=

L

2N

I

CPKƒ

---------------=

0

50

100

150

200

250

300

350

400

0 200 400 600 800 1000 1200 1400 1600 1800

CHANGE PUMP CURRENT (µA)

R

VCO

(Ω)

PHII

PHIO

R2

E1

R

LF

C

LF1

C

LF2

G1

V1

2 π K

ƒ

IN+

IN-

Ns

1

LF

NOTE: PHII, PHIO, LF, and 1 are node names in the SPICE netlist.

GENNUM CORPORATION

521 - 63 - 05

14

GS9025

SPICE NETLIST * GS9025 PLL Model
.PARAM ICP = 165E-6 KF= 90E+6
.PARAM N = 1 D = 0.5
.PARAM PI = 3.14
.IC V(Phio) = 0
.ac dec 30 1k 10meg
RLF 1 LF 1000
CLF1 1 0 15n
CLF2 0 LF 15p
E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)}
G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)}
V1 2 0 DC 0V AC 1V
R2 0 1 1g
.END

12. I/O DESCRIPTION

12.1. High Speed Analog Inputs (SDI/SDI

)

SDI/SDI are high impedance inputs which accept
differential or single-ended input drive.

Figure 22 shows the recommended interface when a single­ended serial digital signal is used.

Fig. 22

12.2. High Speed Digital Inputs (DDI/DDI

)

DDI/DDI are high impedance inputs which accept
differential or single-ended input drive. Two conditions must
be observed when interfacing to these inputs:

1. Input signal amplitudes are between 200 and 2000 mV

2. The common mode input voltage range is as specified
in the DC Characteristics table.

Commonly used interface examples are shown in Figures
23 through 25.

Figure 23 illustrates the simplest interface to the GS9025
digital inputs. In this example, the driving device generates
the PECL level signals (800mV amplitudes) having a
common mode input range between 0.4 and 4.6V. This
scheme is recommended when the trace lengths are less
than 1in. The value of the resistors depends on the output
driver circuitry.

Fig. 23

When trace lengths become greater than 1in, controlled
impedance traces should be used. The recommended
interface is shown in Figure 25. In this case, a parallel
resistor (R

LOAD

) is placed near the GS9025 inputs to
terminate the controlled impedance trace. The value of
R

LOAD

should be 2 times the value of the characteristic
impedance of the trace. In addition, series resistors,
R

SOURCE

, can be placed near the driving chip to serve as
source terminations. They should be equal to the value of
the trace impedance. Assuming 800mV output swings at
the driver, R

LOAD

= 100Ω, R

SOURCE

= 50Ω and ZO = 50Ω.

Fig. 24

Figure 25 shows the recommended interface when the
GS9025 digital inputs are driven single-endedly. In this
case, the input must be AC-coupled and a matching
resistor (Z

o

) must be used.

Fig. 25

When the DDI and the DDI inputs are not used, either pins
44 and 1 or pins 2 and 3 should be connected to V

CC

in

order to saturate one input of the differential amplifier.

12.3. High Speed Outputs (SDO/SDO and SCO/SCO)

SDO/SDO and SCO/SCO are current mode outputs that
require external pullups (

see Figure 26

). The output signal

swings are 800mV when 75Ω resistors are used. A diode
can be placed between V

CC

and the pullups to shift the
signal levels down by approximately 0.7 volts. When the
output traces are longer than 1in, controlled impedance
traces should be used. The pullup resistors should be
placed at the end of the output traces as they terminate the
trace in its characteristic impedance (75Ω).

Fig. 26

SDI

GS9025

SDI

75

10nF

10nF

75

113

DDI
DDI

GS9025

DDI

DDI

R

SOURCE

R

LOAD

R

SOURCE

Z

O

Z

O

GS9025

DDI

DDI

Z

O

GS9025

V

CC

SDO
SDO
SCO
SCO

75

75

V

CC

75

75

GS9025

GENNUM CORPORATION

521 - 63 - 05

15

GS9025

TYPICAL APPLICATION CIRCUIT

TABLE 4: R

VCO

= 365, ƒH = 540MHz, ƒL = 360MHz

SMPTE SS[2:0] DATA RATE (Mb/s)

LOOP

BANDWIDTH

1 000 143 850kHz

1 001 177 1.40MHz

1 010 270 1.70MHz

1 011 360 3.0MHz

1 100 540 4.0MHz

SDO
SDO
V

EE

SCO
SCO
V

EE

SS0
SS1
SS2

GS9025

TOP VIEW

AGC+

VCCVEE LF+

LFS

LF-

VEER

VCO

_RTN

R

VCO

CBG

V

CC

DDI
DDI
V

CC_75

V

CC

V

EE

SDI
SDI

V

CC

V

EE

CD_ADJ
AGC-

V

CC_75

OEM

SMPTE

A/D

SSI/CD

LOCK

COSC

V

EE

CLK_EN

V

CC

V

EE

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

VCCV

CC

4 x 75

see Note 2

From
GS9024

see Note 1

To
GS9020

To LED
Driver
(optional)

1k

15n

0.1µ

0.1µ

5.6p

365
(1%)

1n

4.7n

}

V

CC

10k

50

7537.5

75

10n

10n

75

100k

Pot

(Optional)

100p

Power supply decoupling
capacitors are not shown.

AUTO/MAN

V

EE

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

All resistors in ohms,
all capacitors in microfarads,
unless otherwise stated.

NOTES

1. It is recommended that the DDI/DDI inputs are not driven when the SDI/SDI inputs are being used.
This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance.

2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used.

521 - 63 - 05

16

GENNUM CORPORATION

MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. [phone] Fax. [phone]

SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5

GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. [phone] Fax. [phone]

GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. [phone] Fax [phone]

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.

© Copyright August 1997 Gennum Corporation. All rights reserved. Printed in Canada.

GS9025

PACKAGE DIMENSIONS

10.00 ±0.10

13.20 ±0.25

PIN 1

10.00
±0.10

0.80 BSC

0.45 MAX

0.30 MIN

13.20
±0.25

2.20 MAX

1.85 MIN

0.35 MAX

0.15 MIN

2.55 MAX

0.23
MAX.

1.60
REF

0.3 MAX.
RADIUS

0.13 MIN.
RADIUS

0.88
NOM.

0.20 MIN

5˚ to 16˚

5˚ to 16˚

7˚ MAX
0˚ MIN

0˚ MIN

44 pin MQFP

All dimensions in millimetres

REVISION NOTES:

Clarified symbols for pin numbers 28, 29, 31, and 32;
Changed SSI/CD

to SSI/CD.

For latest product information, visit www.gennum.com

DOCUMENT IDENTIFICATION

PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change.

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STATIC-FREE WORKSTATION