Datasheet GS882ZV18, GS882ZV36BB Datasheet (GSI TECHNOLOGY)

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Page 1

GS882ZV18/36BB/D-333/300/250/200

119-bump and 165-bump BGA

9Mb Pipelined and Flow Through

Commercial Temp Industrial Temp

Synchronous NBT SRAM

Features

• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high

/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip parity encoding and error detection

• LBO

pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA and 165-bump FPBGA packages

• Pb-Free 119-bump and 165-bump BGA packages available

Functional Description

The GS882ZV18/36B is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Paramter Synopsis

Pipeline

3-1-1-1

Flow Through

2-1-1-1

tCycle

Curr (x18)

Curr (x32/x36)

tCycle

Curr (x18)

Curr (x32/x36)

333 MHz–200 MHz

Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS882ZV18/36B may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS882ZV18/36B is implemented with GSI's high performance CMOS technology and is available in JEDECstandard 119-bump BGA and 165-bump FPBGA packages.

-333 -300 -250 -200 Unit

2.5

3.0

245 275

4.5

195 220

2.5

3.3

225 250

5.0

180 200

2.5

4.0

195 220

5.5

155 175

3.0

5.0

165 185

6.5

140 155

) must be tied to a power

ns ns

mA mA

ns ns

mA mA

1.8 V V

1.8 V I/O

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 2

GS882ZV18/36BB/D-333/300/250/200

GS882ZV36B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A V

DDQ

AANCAAV

DDQ

B NC E2 AADVA E3 NC

C NC A A V

D DQ

E DQC DQC V

F V

C DQPC V

DDQ

DQC V

ZQ V

E1 V

G V

AANC

DQPB DQB

DQB DQB

DQB V

DDQ

G DQC DQC BC ABB DQB DQB

H DQC DQC V

J V

DDQ

K DQD DQD V

NC V

W V

CK V

NC V

DQB DQB

DDQ

DQA DQA

L DQD DQD BD NC BA DQA DQA

M V

DDQ

N DQD DQD V

P DQD DQPD V

R NC A LBO V

DQD V

CKE V

A1 V

A0 V

DQA V

DQA DQA

DQPA DQA

DDQ

FT APE

T NC NC A A A NC ZZ

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 3

GS882ZV18/36BB/D-333/300/250/200

GS882ZV18B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A V

DDQ

AANCAAV

DDQ

B NC E2 AADVA E3 NC

C NC A A V

D DQ

E NC DQ

F V

B NC V

B V

DDQ

NC V

ZQ V

E1 V

G V

AANC

DQPA NC

NC DQA

DQA V

DDQ

G NC DQB BB ANCNCDQA

H DQB NC V

J V

DDQ

K NC DQB V

NC V

W V

CK V

NC V

DQA NC

DDQ

NC DQA

L DQB NC NC NC BA DQA NC

M V

DDQ

DQB V

N DQB NC V

P NC DQP

B V

R NC A LBO V

CKE V

A1 V

A0 V

NC V

DDQ

DQA NC

NC DQA

FT APE

T NC A A NC A A ZZ

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 4

GS882ZV18/36BB/D-333/300/250/200

165 Bump BGA—x18 Commom I/O—Top View (Package D)

1234567891011

ANC

BNC

CNCNC

DNC

ENC

FNC

GNC

HFT

DQB NC V

AE1BB NC E3 CKE ADV A17 A A18 A

AE2NCBACK W G NC ANC B

DQB V

MCH NC V

DDQ

NC DQA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

DDQ

DQA NC J

DQA NC K

DQA NC L

DQB NC V

DQB DNU V

PNCNC

RLBO

NC A ATMSA0 TCK A A A AR

DDQ

A ATDIA1 TDO A A ANC P

NC NC NC V

DDQ

DQA NC M

NC NC N

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 5

GS882ZV18/36BB/D-333/300/250/200

165 Bump BGA—x36 Common I/O—Top View (Package D)

1234567891011

ANC

BNC

HFT

DQC NC V

DQC DQC V

MCH NC V

DQD DQD V

AE1BC BB E3 CKE ADV A17 ANC A

AE2BDBA CK W G NC ANC B

DDQ

NC DQB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

DDQ

DQA DQA J

DQA DQA K

DQA DQA L

DQD DQD V

DQD DNU V

PNCNC

RLBO

NC A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

DDQ

NC NC NC V

DDQ

DQA DQA M

NC DQA N

A ATDIA1 TDO A A ANC P

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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GS882ZV18/36BB/D-333/300/250/200

GS882ZV18/36B BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs

DQB DQC DQD

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

CKE

1 I Chip Enable; active low

3 I Chip Enable; active low

2 I Chip Enable; active high

ADV I Burst address counter advance enable; active high

ZZ I Sleep mode control; active high

LBO

ZQ I

TMS

TDI

TDO

TCK

MCH

DNU

DDQ

I/O Data Input and Output pins

I Clock Enable; active low

I Write Enable; active low

I Output Enable; active low

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I 9th Bit Enable; active low (119-bump BGA only)

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect High

—Do Not Use

I Core power supply

I I/O and Core Ground

I Output driver power supply

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 7

GS882ZV18/36BB/D-333/300/250/200

Functional Details

Clocking

Deassertion of the Clock Enable (CKE suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load activation is accomplished by asserting all three of the Chip Enable inputs (E inputs will deactivate the device.

) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

pin (ADV) held low, in order to load the new address. Device

1, E2, and E3). Deassertion of any one of the Enable

Function W

BA BB BC BD

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE chip enables (E

1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

is asserted low, all three

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B

A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 8

Synchronous Truth Table

GS882ZV18/36BB/D-333/300/250/200

Operation Type Address CK CKE

Read Cycle, Begin Burst R External L-H L L H X L H L L L Q

Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10

NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2

Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10

Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3

Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10

Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10

Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z

Deselect Cycle D None L-H L L L H L H L X L High-Z

Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1

Sleep Mode None X X X X X X X X X H High-Z

Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4

ADV W Bx E1 E2 E3 G ZZ DQ Notes

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G

can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx

6. All inputs, except G

7. Wait states can be inserted by setting CKE

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

and ZZ must meet setup and hold times of rising clock edge.

high.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 9

GS882ZV18/36BB/D-333/300/250/200

Pipelined and Flow Through Read Write Control State Diagram

Deselect

New Read New Write

Burst Read Burst Write

Key Notes

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table.

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 10

GS882ZV18/36BB/D-333/300/250/200

Pipeline Mode Data I/O State Diagram

Intermediate Intermediate

Key

Transition

Current State (n) Next State (n+2)

High Z (Data In)

Input Command Code

Intermediate

Transition

Intermediate State (N+1)

Intermediate

High Z

Intermediate

Data Out

(Q Valid)

Intermediate

Notes

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command codes as indicated in the Truth Tables.

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒƒƒ

Intermediate

Next State

State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 11

GS882ZV18/36BB/D-333/300/250/200

Flow Through Mode Data I/O State Diagram

High Z (Data In)

Key Notes

Input Command Code

Transition

Current State (n)

Next State (n+1)

High Z

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Data Out

(Q Valid)

n n+1 n+2 n+3

Clock (CK)

Command

ƒƒƒ

Current State Next State

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 12

GS882ZV18/36BB/D-333/300/250/200

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

FLXDrive Output Impedance Control ZQ

9th Bit Enable PE

Note:

There are pull-up devices onthe ZQ PE chip will operate in the default states as specified in the above tables.

and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

L Activate DQPx I/Os (x18/x36 mode)

H or NC Deactivate DQPx I/Os (x16/x32 mode)

). When this pin is Low, a linear burst

Standby, I

= I

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 13

Burst Counter Sequences

GS882ZV18/36BB/D-333/300/250/200

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I

2 is guaranteed after the time tZZS is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V

on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

tKLtKL

tZZHtZZS

tZZR

signal

or V

on pipelined parts and VSS

DDQ

Page 14

GS882ZV18/36BB/D-333/300/250/200

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

DDQ

I/O

OUT

STG

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to 3.6 V

+0.5 (≤ 3.6 V max.)

DDQ

+0.5 (≤ 3.6 V max.)

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

1.8 V Supply Voltage

1.8 V V

I/O Supply Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DDQ

+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

1.6 1.8 2.0 V

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

2. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

02570°C2

–40 25 85 °C2

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 15

Logic Levels

GS882ZV18/36BB/D-333/300/250/200

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

DDQ

IHQ

ILQ

0.6*V

–0.3 —

0.6*V

–0.3 —

—

0.3*V

DDQ

0.3*V

+ 0.3

V1,3

Notes:

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Undershoot Measurement and Timing Overshoot Measurement and Timing

50%

– 2.0 V

+ 2.0 V

20% tKC

50%

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

I/O

Note:

These parameters are sample tested.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

OUT

= 0 V

45pF

67pF

Page 16

AC Test Conditions

Parameter Conditions

– 0.2 V

DDQ

Output Load 1

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

GS882ZV18/36BB/D-333/300/250/200

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

and ZQ Input Current

Output Leakage Current

Output High Voltage

Output Low Voltage

* Distributed Test Jig Capacitance

IN1

IN2

OH1

OL1

50Ω

DDQ/2

V 0 V ≤ V

Output Disable, V

= –4 mA, V

= 4 mA, V

30pF

= 0 to V

DD ≥ VIN ≥ VIH

DD ≥ VIN ≥ VIL

≤ V

OUT

DDQ

= 0 to V

= 1.6 V

= 1.6 V V

–1 uA 1 uA

–1 uA –1 uA

–100 uA

–1 uA

–1 uA 1 uA

– 0.4 V

DDQ

— 0.4 V

1 uA

100 uA

1 uA 1 uA

—

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 17

Operating Currents

Parameter Test Conditions Mode Symbol

Pipeline

Flow

Through

Pipeline

Flow

Through

Pipeline

Flow

Through

Pipeline

Flow

Through

Operating

Current

Standby

Current

Deselect

Current

Device Selected;

All other inputs

≥V

or ≤ V

– 0.2 V

Output open

ZZ ≥ V

Device Deselected;

All other inputs

≥ V

(x32/

x36)

(x18)

—

DDQ

GS882ZV18/36BB/D-333/300/250/200

-333 -300 -250 -200

–40

70°C

85°C

25025270252302025020200202202017015190

20515225151851520515160151801514015160

23015250152101523015185102051015510175

18510205101701019010145101651013010150

40 50 40 50 40 50 40 50 mA

95 100 90 95 85 90 75 80 mA

60 65 60 65 60 65 50 55 mA

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Unit

Notes:

1. I

and I

apply to any combination of V

DDQ

2. All parameters listed are worst case scenario.

and V

operation.

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 18

AC Electrical Characteristics

GS882ZV18/36BB/D-333/300/250/200

-333 -300 -250 -200

Pipeline

Flow

Through

Parameter Symbol

Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 3.0 — 3.3 — 4.0 — 5.0 — ns

Clock to Output Valid tKQ — 2.5 — 2.5 — 2.5 — 3.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

Setup time tS 1.0 — 1.0 — 1.2 — 1.4 — ns

Hold time tH 0.1 — 0.1 — 0.2 — 0.4 — ns

Clock Cycle Time tKC 4.5 — 5.0 — 5.5 — 6.5 — ns

Clock to Output Valid tKQ — 4.5 — 5.0 — 5.5 — 6.5 ns

Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — 2.0 — ns

Clock to Output in Low-Z

Setup time tS 1.3 — 1.4 — 1.5 — 1.5 — ns

Hold time tH 0.3 — 0.4 — 0.5 — 0.5 — ns

Clock HIGH Time tKH 1.0 — 1.0 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.2 — 1.2 — 1.5 — 1.5 — ns

Clock to Output in

High-Z

to Output Valid tOE — 2.5 — 2.5 — 2.5 — 3.0 ns

to output in Low-Z

to output in High-Z

ZZ setup time

ZZ hold time

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

tLZ

tHZ

tOLZ

tOHZ

tZZS

tZZH

1.5 — 1.5 — 1.5 — 1.5 — ns

2.0 — 2.0 — 2.0 — 2.0 — ns

1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 ns

0 — 0 — 0 — 0 — ns

— 2.5 — 2.5 — 2.5 — 3.0 ns

5 — 5 — 5 — 5 — ns

1 — 1 — 1 — 1 — ns

Unit

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 19

CKE

ADV

A0–An

DQa–DQd

GS882ZV18/36BB/D-333/300/250/200

Pipeline Mode Timing (NBT)

Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G Deselect

tKL

tKC

tKHtKH

AB C DEFG

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)

tKC

tLZtH

tOEtOHZ

tHZ

tKQXtKQ

tOLZ

*Note: E

= High(False) if E1 = 1 or E2 = 0 or E3 = 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 20

CKE

ADV

A0–An

GS882ZV18/36BB/D-333/300/250/200

Flow Through Mode Timing (NBT)

Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G

tKLtKL

AB C DEFG

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)

tKHtKH

tLZ

tKCtKC

tOHZ

tOLZ tOE

tKQXtKQ

tKQ

tLZtHZ

tKQX

*Note: E

= High(False) if E1 = 1 or E2 = 0 or E3 = 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 21

GS882ZV18/36BB/D-333/300/250/200

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

drivers are powered by V

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V

DDQ

or VSS. TDO should be left unconnected.

JTAG Port Registers JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

. The JTAG output

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 22

GS882ZV18/36BB/D-333/300/250/200

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

·· ······

Boundary Scan Register

108

Bypass Register

012

Instruction Register

TDI

TDO

ID Code Register

31 30 29 12

····

Control Signals

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 23

ID Register Contents

GS882ZV18/36BB/D-333/300/250/200

Die

Revision

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x36 XXXX000000000000100000011011001 1

x18 XXXX000000000000101000011011001 1

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 24

Test Logic Reset

GS882ZV18/36BB/D-333/300/250/200

JTAG Tap Controller State Diagram

Run Test Idle

111

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

0 0

Exit2 IR

Update IR

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 25

GS882ZV18/36BB/D-333/300/250/200

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

100

TDO. Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 26

JTAG Port AC Test Conditions

GS882ZV18/36BB/D-333/300/250/200

Parameter Conditions

Input high level

– 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

DDQ

Input reference level

Output reference level

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

Test Port Input High Voltage

Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

≤ V

2. V

ILJ

3. 0 V ≤ V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

OHJ

7. I

OLJ

8. I

OHJC

9. I

OHJC

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

IHJ

ILJ

INHJ

INLJ

OLJ

OHJ

OLJ

OHJC

OLJC

DDQ

JTAG Port AC Test Load

30pF

0.6 * V

–0.3

50Ω

DDQ

* Distributed Test Jig Capacitance

0.3 * V

+0.3

–300 1 uA 2

–1 100 uA 3

–11uA4

1.7 — V5, 6

— 0.4 V 5, 7

– 100 mV

— V5, 8

— 100 mV V 5, 9

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 27

TCK

TDI

TMS

TDO

Parallel SRAM input

GS882ZV18/36BB/D-333/300/250/200

JTAG Port Timing Diagram

tTKLtTKLtTKHtTKHtTKCtTKC

tTH

tTS

tTH

tTS

tTKQ

tTH

tTS

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 28

GS882ZV18/36BB/D-333/300/250/200

Package Dimensions—119-Bump FPBGA (Package B, Variation 2)

TOP VIEW

Ø0.10 Ø0.30

C A B

1 2 3 4 5 6 7

A B C D E F G H J K L M N P R T U

22±0.10

BOTTOM VIEW

1.27

20.32

Ø0.60~0.90 (119x)

7 6 5 4 3 2 1

0.15

0.70±0.05

0.15

0.20(4x)

1.27

7.62

14±0.10

0.56±0.05

SEATING PLANE

1.86.±0.13

0.50~0.70

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 29

GS882ZV18/36BB/D-333/300/250/200

Package Dimensions—165-Bump FPBGA (Package D; Variation 1)

A1 CORNER

1 2 3 4 5 6 7 8 9 10 11

A B C D E F G H J K L M N P R

0.25

0.45±0.05

TOP VIEW

Ø0.10

Ø0.25

C A B

Ø0.40~0.50 (165x)

BOTTOM VIEW

A1 CORNER

11 10 9 8 7 6 5 4 3 2 1

A B C D E

1.01.0

F G

14.0

15±0.07

H J K L M N P R

0.15

0.20(4x)

1.0 1.0

10.0

13±0.07

(0.26)

SEATING PLANE

1.20 MAX.

0.25~0.40

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 30

GS882ZV18/36BB/D-333/300/250/200

Ordering Information—GSI NBT Synchronous SRAM

Org

512K x 18 GS882ZV18BB-333 NBT Pipeline/Flow Through 119 BGA (var. 2) 333/4.5 C

512K x 18 GS882ZV18BB-300 NBT Pipeline/Flow Through 119 BGA (var. 2) 300/5 C

512K x 18 GS882ZV18BB-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 C

512K x 18 GS882ZV18BB-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 C

256K x 36 GS882ZV36BB-333 NBT Pipeline/Flow Through 119 BGA (var. 2) 333/4.5 C

256K x 36 GS882ZV36BB-300 NBT Pipeline/Flow Through 119 BGA (var. 2) 300/5 C

256K x 36 GS882ZV36BB-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 C

256K x 36 GS882ZV36BB-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 C

512K x 18 GS882ZV18BB-333I NBT Pipeline/Flow Through 119 BGA (var. 2) 333/4.5 I

512K x 18 GS882ZV18BB-300I NBT Pipeline/Flow Through 119 BGA (var. 2) 300/5 I

512K x 18 GS882ZV18BB-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 I

512K x 18 GS882ZV18BB-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 I

256K x 36 GS882ZV36BB-333I NBT Pipeline/Flow Through 119 BGA (var. 2) 333/4.5 I

256K x 36 GS882ZV36BB-300I NBT Pipeline/Flow Through 119 BGA (var. 2) 300/5 I

256K x 36 GS882ZV36BB-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 I

256K x 36 GS882ZV36BB-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 I

512K x 18 GS882ZV18BD-333 NBT Pipeline/Flow Through 165 BGA (var. 1) 333/4.5 C

512K x 18 GS882ZV18BD-300 NBT Pipeline/Flow Through 165 BGA (var. 1) 300/5 C

512K x 18 GS882ZV18BD-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 C

512K x 18 GS882ZV18BD-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 C

256K x 36 GS882ZV36BD-333 NBT Pipeline/Flow Through 165 BGA (var. 1) 333/4.5 C

256K x 36 GS882ZV36BD-300 NBT Pipeline/Flow Through 165 BGA (var. 1) 300/5 C

256K x 36 GS882ZV36BD-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 C

256K x 36 GS882ZV36BD-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 C

512K x 18 GS882ZV18BD-333I NBT Pipeline/Flow Through 165 BGA (var. 1) 333/4.5 I

512K x 18 GS882ZV18BD-300I NBT Pipeline/Flow Through 165 BGA (var. 1) 300/5 I

512K x 18 GS882ZV18BD-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 I

512K x 18 GS882ZV18BD-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 I

256K x 36 GS882ZV36BD-333I NBT Pipeline/Flow Through 165 BGA (var. 1) 333/4.5 I

256K x 36 GS882ZV36BD-300I NBT Pipeline/Flow Through 165 BGA (var. 1) 300/5 I

256K x 36 GS882ZV36BD-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882ZV36B-200IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

Type Package

) for a complete listing of current offerings

Speed

(MHz/ns)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 31

GS882ZV18/36BB/D-333/300/250/200

Ordering Information—GSI NBT Synchronous SRAM (Continued)

Org

256K x 36 GS882ZV36BD-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 I

512K x 18 GS882ZV18BGB-333 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 333/4.5 C

512K x 18 GS882ZV18BGB-300 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 300/5 C

512K x 18 GS882ZV18BGB-250 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 250/5.5 C

512K x 18 GS882ZV18BGB-200 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 200/6.5 C

256K x 36 GS882ZV36BGB-333 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 333/4.5 C

256K x 36 GS882ZV36BGB-300 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 300/5 C

256K x 36 GS882ZV36BGB-250 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 250/5.5 C

256K x 36 GS882ZV36BGB-200 NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 200/6.5 C

512K x 18 GS882ZV18BGB-333I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 333/4.5 I

512K x 18 GS882ZV18BGB-300I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 300/5 I

512K x 18 GS882ZV18BGB-250I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 250/5.5 I

512K x 18 GS882ZV18BGB-200I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 200/6.5 I

256K x 36 GS882ZV36BGB-333I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 333/4.5 I

256K x 36 GS882ZV36BGB-300I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 300/5 I

256K x 36 GS882ZV36BGB-250I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 250/5.5 I

256K x 36 GS882ZV36BGB-200I NBT Pipeline/Flow Through Pb-Free 119 BGA (var. 2) 200/6.5 I

512K x 18 GS882ZV18BGD-333 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 333/4.5 C

512K x 18 GS882ZV18BGD-300 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 300/5 C

512K x 18 GS882ZV18BGD-250 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 250/5.5 C

512K x 18 GS882ZV18BGD-200 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 200/6.5 C

256K x 36 GS882ZV36BGD-333 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 333/4.5 C

256K x 36 GS882ZV36BGD-300 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 300/5 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882ZV36B-200IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Part Number

Type Package

) for a complete listing of current offerings

Speed

(MHz/ns)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 32

GS882ZV18/36BB/D-333/300/250/200

Ordering Information—GSI NBT Synchronous SRAM (Continued)

Org

256K x 36 GS882ZV36BGD-250 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 250/5.5 C

256K x 36 GS882ZV36BGD-200 NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 200/6.5 C

512K x 18 GS882ZV18BGD-333I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 333/4.5 I

512K x 18 GS882ZV18BGD-300I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 300/5 I

512K x 18 GS882ZV18BGD-250I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 250/5.5 I

512K x 18 GS882ZV18BGD-200I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 200/6.5 I

256K x 36 GS882ZV36BGD-333I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 333/4.5 I

256K x 36 GS882ZV36BGD-300I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 300/5 I

256K x 36 GS882ZV36BGD-250I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 250/5.5 I

256K x 36 GS882ZV36BGD-200I NBT Pipeline/Flow Through Pb-Free 165 BGA (var. 1) 200/6.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882ZV36B-200IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

Part Number

Type Package

) for a complete listing of current offerings

Speed

(MHz/ns)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Page 33

9Mb Sync SRAM Datasheet Revision History

GS882ZV18/36BB/D-333/300/250/200

DS/DateRev. Code: Old;

New

882ZVxxB_r1

882ZVxxB_r1;

882ZVxxB_r1_01

882ZVxxB_r1_01;

882ZVxxB_r1_02

882ZVxxB_r1_02;

882ZVxxB_r1_03

Types of Changes Format or Content

Content

Page;Revisions;Reason

• Creation of new datasheet

• Updated mechanical drawings and added variation numbers to ordering information

• Corrected mode pins table note

• Corrected tZZI to tZZS on page 13

• Re-added Temperature Condition table to Abs Max section

• Added Pb-Free information

• Removed 150 MHz speed bin

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Datasheet GS882ZV18, GS882ZV36BB Datasheet (GSI TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

GS882ZV36B Pad Out—119-Bump BGA—Top View (Package B)

GS882ZV18B Pad Out—119-Bump BGA—Top View (Package B)

165 Bump BGA—x18 Commom I/O—Top View (Package D)

165 Bump BGA—x36 Common I/O—Top View (Package D)

GS882ZV18/36B BGA Pin Description

Functional Details

Clocking

Pipeline Mode Read and Write Operations

Flow Through Mode Read and Write Operations

Synchronous Truth Table

Pipelined and Flow Through Read Write Control State Diagram

Pipeline Mode Data I/O State Diagram

Flow Through Mode Data I/O State Diagram

Burst Cycles

Burst Order

FLXDrive™

Mode Pin Functions

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

Sleep Mode Timing Diagram

Designing for Compatibility

Absolute Maximum Ratings

Power Supply Voltage Ranges

Recommended Operating Temperatures

Logic Levels

Capacitance

AC Test Conditions

DC Electrical Characteristics

Operating Currents

Notes:

AC Electrical Characteristics

Pipeline Mode Timing (NBT)

Flow Through Mode Timing (NBT)

JTAG Port Operation

Overview

Disabling the JTAG Port

Overview

Instruction Register

Bypass Register

Boundary Scan Register

JTAG TAP Block Diagram

Identification (ID) Register

ID Register Contents

Tap Controller Instruction Set

Overview

JTAG Tap Controller State Diagram

Instruction Descriptions

JTAG TAP Instruction Set Summary

JTAG Port AC Test Conditions

JTAG Port Recommended Operating Conditions and DC Characteristics

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Boundary Scan (BSDL Files)

Package Dimensions—119-Bump FPBGA (Package B, Variation 2)

Package Dimensions—165-Bump FPBGA (Package D; Variation 1)

9Mb Sync SRAM Datasheet Revision History