Datasheet GS88237BB-333, GS88237BB-300, GS88237BB-250, GS88237BB-200, GS88237BB-333I Datasheet (GSI TECHNOLOGY)

GS88237BB/D-333/300/250/200

119- & 165-Bump BGA

256K x 36

Commercial Temp
Industrial Temp

9Mb SCD/DCD Sync Burst SRAM

Features

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO

pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump and 165-bump BGA packages

• Pb-Free 119-bump and 165-bump BGA packages available

) and/or Global Write (GW) operation

/low output drive

Functional Description

Applications

The GS88237BB/D is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1
inputs (ADSP
BW

, GW) are synchronous and are controlled by a positive­edge-triggered clock input (CK). Output enable (G
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP
subsequent burst addresses are generated internally and are
controlled by ADV
configured to count in either linear or interleave order with the
Linear Burst Order (LBO
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.

, ADSC, ADV), and write control inputs (Bx,

or ADSC inputs. In Burst mode,

. The burst address counter may be

) input. The Burst function need not

), address burst control

) and power

333 MHz–200 MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

SCD and DCD Pipelined Reads

The GS88237BB/D is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
DCD SRAMs pipeline disable commands to the same degree
as read commands. SCD SRAMs pipeline deselect commands
one stage less than read commands. SCD RAMs begin turning
off their outputs immediately after the deselect command has
been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure this SRAM for either mode of operation using
the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW

) input combined with one or more individual byte write
signals (Bx
writing all bytes at one time, regardless of the Byte Write
control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88237BB/D operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V

internal circuits and are 3.3 V and 2.5 V compatible.

). In addition, Global Write (GW) is available for

) pins are used to decouple output noise from the

DDQ

Parameter Synopsis

-333 -300 -250 -200 Unit

2.0

2.2

2.3

4.0

2.7

5.0nsns

Pipeline

3-1-1-1

3.3 V Curr

2.5 V Curr

Rev: 1.04 3/2005 1/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

t

KQ

tCycle

(x36) 435 395 330 270 mA
(x36) 435 395 330 270 mA

3.0

3.3

GS88237BB/D-333/300/250/200

GS88237B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC NC A4 ADSC A15 A17 NC

NC A5 A3 V

DQC4 DQC9 V

DQC3 DQC8 V

V

DDQ

DQC2 DQC6 BC ADV BB DQB6 DQB2

DQC1 DQC5 V

V

DDQ

DQD1 DQD5 V

DQD2 DQD6 BD SCD BA DQA6 DQA2

A6 A7 ADSP A8 A9 V

A14 A16 NC

DQB9 DQB4

SS

DQB8 DQB3

SS

DQB7 V

SS

DQB5 DQB1

SS

NC V

SS

DD

DQA5 DQA1

DQC7 V

V

DD

SS

SS

SS

SS

NC V

SS

DD

ZQ V

E1 V

G V

GW V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQD3 DQD8 V

DQD4 DQD9 V

NC A2 LBO V

NC NC A10 A11 A12 NC ZZ

V

DDQ

DQD7 V

SS

SS

SS

BW V

A1 V

A0 V

V

DD

SS

SS

SS

DDQ

DNU

DQA7 V

DQA8 DQA3

DQA9 DQA4

/

A

13 PE

TMS TDI TCK TDO NC V

DDQ

DDQ

Rev: 1.04 3/2005 2/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

165 Bump BGA—x36 Common I/O—Top View (Package D)

1234567891011

ANC

BNC

C

D

E

F

G

HV

J

K

DQC NC V

DQC DQC V

DQC DQC V

DQC DQC V

DQC DQC V

/NCMCL NC V

DDQ

DQD DQD V

DQD DQD V

AE1BC BB E3 BW ADSC ADV ANC A

AE2BDBA CK GW G ADSP ANC B

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

SS

SS

SS

SS

SS

SS

SS

SS

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

V

DDQ

DDQ

DQA DQA J

DQA DQA K

L

M

N

DQD DQD V

DQD DQD V

DQD SCD V

PNCNC

RLBO

NC A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

DDQ

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

V

DD

DD

SS

V

V

V

DDQ

DDQ

DDQ

DQA DQA L

DQA DQA M

NC DQA N

A ATDIA1 TDO A A A A17 P

Rev: 1.04 3/2005 3/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

GS882V37 BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs

DQ

A

DQB
DQC
DQD

B

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

NC — No Connect

CK I Clock Input Signal; active high

BW

GW

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

G

ADV

ADSC

, ADSP I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high

LBO

PE

ZQ I

TMS

TDI

TDO

TCK

MCL

SCD

V

DD

V

SS

V

DDQ

I/O Data Input and Output pins

I Byte Write—Writes all enabled bytes; active low

I Global Write Enable—Writes all bytes; active low

I Output Enable; active low

I Burst address counter advance enable; active l0w

I Linear Burst Order mode; active low

I 9th Bit Enable; active low (only on 119-bump BGA)

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect Low

— Single Cycle Deselect/Dual Cyle Deselect Mode Control

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 3/2005 4/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237B Block Diagram

GS88237BB/D-333/300/250/200

A0–An

LBO

ADV

CK

ADSC
ADSP

GW
BW

BA

BB

BC

BD

Register

DQ

A0

A1

D0

D1

Counter

Load

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Q0

Q1

A0

A1

A

Memory

Array

QD

36

4

DQ

Register

36

Register

DQ

E1
E2
E3

G

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

Register

DQ

Register

DQ

Register

DQ

DQx1–DQx9

Rev: 1.04 3/2005 5/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Power Down Control ZZ

Single/Dual Cycle Deselect Control SCD

FLXDrive Output Impedance Control ZQ

9th Bit Enable PE

Note:

There are pull-up devices onthe ZQ, SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.

Burst Counter Sequences

L Linear Burst

H Interleaved Burst

L or NC Active

H

L Dual Cycle Deselect

H or NC Single Cycle Deselect

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

L Activate DQPx I/Os (x18/x36 mode)

H or NC Deactivate DQPx I/Os (x16/x32 mode)

Standby, I

DD

= I

SB

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.04 3/2005 6/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read HL HHHH1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytesHLLLLL2, 3, 4

Write all bytesLXXXXX

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs B

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “

C” and “D” are only available on the x36 version.

A, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

Rev: 1.04 3/2005 7/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram

X

Deselect

WR

GS88237BB/D-333/300/250/200

Simple Synchronous OperationSimple Burst Synchronous Operation

W

X

First Write

WR

Burst Write

CW CR

R

CR

R

CR

R

First Read

Burst Read

X

CRCW

XX

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G

2. The upper portion of the diagram assumes active use of only the Enable (E1
that ADSP

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC
assumes ADSP

Rev: 1.04 3/2005 8/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

is tied high and ADSC is tied low.

is tied high and ADV is tied low.

) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

is tied low.

control inputs and

Simplified State Diagram with G

X

Deselect

WR

GS88237BB/D-333/300/250/200

W

X

First Write

W

X

Burst Write

CW CR

R

CR

R

CR

W

CW

W

CW

R

First Read

R

Burst Read

X

CRCW

X

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G

2. Use of “Dummy Reads” (Read Cycles with G
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G
Data Input Set Up Time.

Rev: 1.04 3/2005 9/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

High) may be used to make the transition from read cycles to write cycles without passing

has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

.

GS88237BB/D-333/300/250/200

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

CK

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Voltage on VDD Pins

Voltage in V

DDQ

Pins

–0.5 to 4.6 V

–0.5 to 4.6 V

Voltage on Clock Input Pin –0.5 to 6 V

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V

V

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o

o

C

C

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

V

DD3

V

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

Rev: 1.04 3/2005 10/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

Range Logic Levels

DDQ3

GS88237BB/D-333/300/250/200

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

V

DD

I/O Input High Voltage V

V

DDQ

I/O Input Low Voltage V

V

DDQ

IH

IL

IHQ

ILQ

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

V

V

DD

DDQ

+ 0.3

+ 0.3

V1

V1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

V

Range Logic Levels

DDQ2

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

V

DD

V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

V

DDQ

IH

IL

IHQ

ILQ

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

V

0.3*V

V

DDQ

0.3*V

DD

+ 0.3

DD

+ 0.3

DD

V1

V1

V1,3

V1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

Rev: 1.04 3/2005 11/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

02570°C2

–40 25 85 °C2

GS88237BB/D-333/300/250/200

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

V

+ 2.0 V

DD

V

SS

50%

20% tKC

50%

– 2.0 V

SS

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note:

These parameters are sample tested.

C

IN

C

I/O

AC Test Conditions

Parameter Conditions

V

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

– 0.2 V

DD

VDD/2

V

DDQ

/2

V

V

OUT

IN

= 0 V

= 0 V

V

DD

V

IL

45pF

67pF

Output Load 1

DQ

50Ω

V

DDQ/2

* Distributed Test Jig Capacitance

30pF

*

Rev: 1.04 3/2005 12/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

Output Leakage Current

Output High Voltage

Output High Voltage

Output Low Voltage

I

IL

I

IN1

I

OL

V

OH2

V

OH3

V

OL

Operating Currents

Parameter Test Conditions Mode Symbol

Operating

Current

3.3 V

Operating

Current

2.5 V

Standby

Current

Deselect

Current

Notes:

1. I

and I

DD

2. All parameters listed are worst case scenario.

Device Selected;

All other inputs

≥V

or ≤ V

IH

or ≤ V

IH

DD

or ≤ V

IH

IL

IL

– 0.2 V

IL

Output open

Device Selected;

All other inputs

≥V

Output open

ZZ ≥ V

Device Deselected;

All other inputs

≥ V

apply to any combination of V

DDQ

(x36) Pipeline

(x36) Pipeline

— Pipeline

— Pipeline

, V

DD3

DD2

, V

I

DD

I

DDQ

I

DD

I

DDQ

I

SB

I

DD

DDQ3

GS88237BB/D-333/300/250/200

V

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V

Output Disable, V

I

= –8 mA, V

OH

I

= –8 mA, V

OH

I

OL

≤ V

IN

OUT

DDQ

DDQ

= 8 mA

DD

IH

= 0 to V

= 2.375 V

= 3.135 V

DD

-333 -300 -250 -200

0

–40

to

to

70°C

85°C

38055390553455035550290403004024030250

38055390553450535550290403004024030250

40 50 40 50 40 50 40 50 mA

85 90 80 85 85 90 75 80 mA

, and V

DDQ2

operation.

0

to

70°C

–40

to

85°C

0

to

70°C

–1 uA 1 uA

–1 uA
–1 uA

–1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

–40

to

85°C

0

to

70°C

–40

to

85°C

30

30

1 uA

100 uA

Unit

mA

mA

Rev: 1.04 3/2005 13/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

GS88237BB/D-333/300/250/200

Pipeline

Parameter Symbol

-333 -300 -250 -200

Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 3.0 — 3.3 — 4.0 — 5.0 — ns

Clock to Output Valid tKQ — 2.0 — 2.2 — 2.3 — 2.7 ns

Clock to Output Invalid tKQX 1.0 — 1.0 — 1.0 — 1.0 — ns

Clock to Output in Low-Z

tLZ

1

1.0 — 1.0 — 1.0 — 1.0 — ns

Setup time tS 1.0 — 1.1 — 1.2 — 1.4 — ns

Hold time tH 0 — 0.1 — 0.2 — 0.4 — ns

G

to Output Valid tOE — 2.0 — 2.2 — 2.3 — 2.5 ns

to output in High-Z

G

tOHZ

1

— 2.0 — 2.2 — 2.3 — 2.5 ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in

High-Z

to output in Low-Z

G

ZZ setup time

tHZ

tOLZ

tZZS

1

1

2

1.0 2.0 1.0 2.2 1.5 2.3 1.5 3.0 ns

0 — 0 — 0 — 0 — ns

5 — 5 — 5 — 5 — ns

Unit

ZZ hold time

tZZH

2

1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Rev: 1.04 3/2005 14/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Pipeline Mode Timing (+1)

Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect

tKCtKC

tKLtKLtKHtKH

CK

ADSP

ADSC

ADV

A0–An

GW

BW

Ba–Bd

E1

E2

E3

tS

tH

tHtS

tS

tH

ABC

tS

tS

tS

tS

tH

tS

tH

tH

E2 and E3 only sampled with ADSC

ADSC initiated read

tHtS

tH

Deselected with E1

G

tKQXtKQ

tHZ

DQa–DQd

tOHZtOE

tS

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)

tLZtH

Rev: 1.04 3/2005 15/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

CK

Setup

Hold

ADSP

ADSC

ZZ

tKLtKL

tZZR

tZZHtZZS

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or VSS. TDO should be left unconnected.

DD

Rev: 1.04 3/2005 16/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

. The JTAG output

DD

GS88237BB/D-333/300/250/200

JTAG Port Registers
JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

Rev: 1.04 3/2005 17/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TDI

·· ······

·

·

108

JTAG TAP Block Diagram

Boundary Scan Register

0

Bypass Register

012

Instruction Register

ID Code Register

31 30 29 12

····

0

GS88237BB/D-333/300/250/200

·

1

0

TDO

Control Signals

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.04 3/2005 18/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Tap Controller Instruction Set

ID Register Contents

GS88237BB/D-333/300/250/200

Die

Revision

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x36 XXXX000X100100001000000110110011

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Rev: 1.04 3/2005 19/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Test Logic Reset

1

GS88237BB/D-333/300/250/200

JTAG Tap Controller State Diagram

0

Run Test Idle

0

111

Select DR

1

Capture DR

Shift DR

1

Exit1 DR

Pause DR

Exit2 DR

Update DR

1

Select IR

0

1

0

0

Capture IR

0

Shift IR

1

0

0

1

1

Exit1 IR

0

Pause IR

1

1

0

0 0

1

Exit2 IR

1

Update IR

0

10

0

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili­tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.

Rev: 1.04 3/2005 20/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc­tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso­ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ­ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high­Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

Rev: 1.04 3/2005 21/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port AC Test Conditions

GS88237BB/D-333/300/250/200

Parameter Conditions

V

Input high level

– 0.2 V

DD

DQ

JTAG Port AC Test Load

Input low level 0.2 V

V

DDQ

50Ω

/2

Input slew rate 1 V/ns

Input reference level

Output reference level

V

V

DDQ

DDQ

/2

/2

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

100

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

TDO.
Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

30pF

*

1

1

1

1

Rev: 1.04 3/2005 22/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

2. V

3. 0 V ≤ V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

7. I

8. I

9. I

ILJ

OHJ

OLJ

OHJC

OHJC

≤ V

IN

IN

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V
≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

JTAG Port Timing Diagram

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

V

V

V

V

I

INHJ

I

I

V

V

V

OHJC

V

IHJ3

ILJ3

IHJ2

ILJ2

INLJ

OLJ

OHJ

OLJ

OLJC

V

DDQ

0.6 * V

GS88237BB/D-333/300/250/200

V

2.0

–0.3 0.8 V 1

DD2

–0.3

–300 1 uA 2

–1 100 uA 3

–11uA4

1.7 — V5, 6

— 0.4 V 5, 7

– 100 mV

— 100 mV V 5, 9

DD3

V

DD2

0.3 * V

+0.3

+0.3

DD2

V1

V1

V1

— V5, 8

tTKLtTKLtTKHtTKHtTKCtTKC

TCK

tTH

tTS

TDI

tTH

tTS

TMS

tTKQ

TDO

tTH

tTS

Parallel SRAM input

Rev: 1.04 3/2005 23/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [e-mail]

.

Rev: 1.04 3/2005 24/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Package Dimensions—119-Bump FPBGA (Package B, Variation 2)

A1

TOP VIEW

Ø0.10
Ø0.30

S

C

S

C A B

1 2 3 4 5 6 7

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

22±0.10

BOTTOM VIEW

S

S

1.27

20.32

A1

Ø0.60~0.90 (119x)

7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

B

C

0.15

0.70±0.05

C

0.15

A

0.20(4x)

1.27

7.62

14±0.10

C

0.56±0.05

SEATING PLANE

0.50~0.70

1.86.±0.13

Rev: 1.04 3/2005 25/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Package Dimensions—165-Bump FPBGA (Package D; Variation 1)

GS88237BB/D-333/300/250/200

A1 CORNER

TOP VIEW

1 2 3 4 5 6 7 8 9 10 11

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R

C

0.25

0.45±0.05

M

Ø0.10

C

M

Ø0.25

C A B

Ø0.40~0.50 (165x)

BOTTOM VIEW

A1 CORNER

11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E

1.01.0

F
G

14.0

15±0.07

H
J
K
L
M
N
P
R

A

C

0.15

B

0.20(4x)

1.0 1.0

10.0

13±0.07

C

(0.26)

SEATING PLANE

0.25~0.40

1.20 MAX.

Rev: 1.04 3/2005 26/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Ordering Information for GSI Synchronous Burst RAMs

2

Org

256K x 36 GS88237BB-333 S/DCD Pipeline 119 BGA (var. 2) 333 C

256K x 36 GS88237BB-300 S/DCD Pipeline 119 BGA (var. 2) 300 C

256K x 36 GS88237BB-250 S/DCD Pipeline 119 BGA (var. 2) 250 C

256K x 36 GS88237BB-200 S/DCD Pipeline 119 BGA (var. 2) 200 C

256K x 36 GS88237BB-333I S/DCD Pipeline 119 BGA (var. 2) 333 I

256K x 36 GS88237BB-300I S/DCD Pipeline 119 BGA (var. 2) 300 I

256K x 36 GS88237BB-250I S/DCD Pipeline 119 BGA (var. 2) 250 I

256K x 36 GS88237BB-200I S/DCD Pipeline 119 BGA (var. 2) 200 I

256K x 36 GS88237BD-333 S/DCD Pipeline 165 BGA (var. 1) 333 C

256K x 36 GS88237BD-300 S/DCD Pipeline 165 BGA (var. 1) 300 C

Part Number

1

Type Package

Speed

(MHz)

3

T

A

Status

256K x 36 GS88237BD-250 S/DCD Pipeline 165 BGA (var. 1) 250 C

256K x 36 GS88237BD-200 S/DCD Pipeline 165 BGA (var. 1) 200 C

256K x 36 GS88237BD-333I S/DCD Pipeline 165 BGA (var. 1) 333 I

256K x 36 GS88237BD-300I S/DCD Pipeline 165 BGA (var. 1) 300 I

256K x 36 GS88237BD-250I S/DCD Pipeline 165 BGA (var. 1) 250 I

256K x 36 GS88237BD-200I S/DCD Pipeline 165 BGA (var. 1) 200 I

256K x 36 GS88237BGB-333 S/DCD Pipeline Pb-Free 119 BGA (var. 2) 333 C

256K x 36 GS88237BGB-300 S/DCD Pipeline Pb-Free 119 BGA (var. 2) 300 C

256K x 36 GS88237BGB-250 S/DCD Pipeline Pb-Free 119 BGA (var. 2) 250 C

256K x 36 GS88237BGB-200 S/DCD Pipeline Pb-Free 119 BGA (var. 2) 200 C

256K x 36 GS88237BGB-333I S/DCD Pipeline Pb-Free 119 BGA (var. 2) 333 I

256K x 36 GS88237BGB-300I S/DCD Pipeline Pb-Free 119 BGA (var. 2) 300 I

256K x 36 GS88237BGB-250I S/DCD Pipeline Pb-Free 119 BGA (var. 2) 250 I

256K x 36 GS88237BGB-200I S/DCD Pipeline Pb-Free 119 BGA (var. 2) 200 I

256K x 36 GS88237BGD-333 S/DCD Pipeline Pb-Free 165 BGA (var. 1) 333 C

256K x 36 GS88237BGD-300 S/DCD Pipeline Pb-Free 165 BGA (var. 1) 300 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88237BB-200IB.

2. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

) for a complete listing of current offerings.

Rev: 1.04 3/2005 27/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88237BB/D-333/300/250/200

Ordering Information for GSI Synchronous Burst RAMs

2

Org

256K x 36 GS88237BGD-250 S/DCD Pipeline Pb-Free 165 BGA (var. 1) 250 C

256K x 36 GS88237BGD-200 S/DCD Pipeline Pb-Free 165 BGA (var. 1) 200 C

256K x 36 GS88237BGD-333I S/DCD Pipeline Pb-Free 165 BGA (var. 1) 333 I

256K x 36 GS88237BGD-300I S/DCD Pipeline Pb-Free 165 BGA (var. 1) 300 I

256K x 36 GS88237BGD-250I S/DCD Pipeline Pb-Free 165 BGA (var. 1) 250 I

256K x 36 GS88237BGD-200I S/DCD Pipeline Pb-Free 165 BGA (var. 1) 200 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88237BB-200IB.

2. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz)

3

T

A

Status

Rev: 1.04 3/2005 28/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

9Mb Sync SRAM Datasheet Revision History

GS88237BB/D-333/300/250/200

DS/DateRev. Code: Old;

New

88237B_r1

88237B_r1; 88237B_r1_01 Content

88237B_r1_01;

88237B_r1_02

88237B_r1_02;

88237B_r1_03

88237B_r1_03;

88237B_r1_04

Types of Changes
Format or Content

Content

Content

Content

Page;Revisions;Reason

• Creation of new datasheet

• Corrected ordering information (incorrect speed bins
corrected)

• Updated entire format

• Added 165 BGA to entire document

• Removed Preliminary banner

• Removed 275 & 225 MHz speed bins

• Updated mechanical drawings and added variation numbers
to ordering information

• Added Pb-Free information

• Corrected block diagram (added E2 & E3 references)

• Added /PE information to pin description table

Rev: 1.04 3/2005 29/29 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.