Datasheet GS88236B-80I, GS88236B-80, GS88236B-66I, GS88236B-66, GS88236B-11I Datasheet (GSI)

Rev: 1.15 5/2001 1/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

512K x 18, 256K x 36 ByteSafe™

8Mb S/DCD Sync Burst SRAMs

100 MHz–66 MHz

3.3 V V

DD

3.3 V and 2.5 V I/O

119-Bump BGA
Commercial Temp
Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect Selectable

• IEEE 1149.1 JTAG Compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive strength

• x16/x32 mode with on-chip parity encoding and error detection

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 119-bump BGA package

Functional Description

Applications

The GS88218/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1 and E2), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising­edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS88218/36B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.

ByteSafe™ Parity Functions

The GS88218/36B features ByteSafe data security functions.
See “ByteSafe™ Parity Functions” on page8 for further
information.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart on page 38 for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88218/36B operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V

DDQ

) pins are used to decouple output noise

from the internal circuit.

-11 -11.5 -100 -80 -66

Pipeline

3-1-1-1

tCycle

t

KQ

I

DD

10 ns

4.0 ns

225 mA

10 ns

4.0 ns

225 mA

10 ns

4.0 ns

225 mA

12.5 ns

4.5 ns

200 mA

15 ns

5 ns

185 mA

Flow

Through

2-1-1-1

t

KQ

tCycle

I

DD

11 ns
15 ns

180 mA

11.5 ns
15 ns

180 mA

12 ns
15 ns

180 mA

14 ns
15 ns

175 mA

18 ns
20 ns

165 mA

Rev: 1.15 5/2001 2/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88236 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC E2 A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQC4 DQC9 V

SS

ZQ V

SS

DQB9 DQB4

E

DQC3 DQC8 V

SS

E1 V

SS

DQB8 DQB3

F

V

DDQ

DQC7 V

SS

G V

SS

DQB7 V

DDQ

G

DQC2 DQC6 BC ADV BB DQB6 DQB2

H

DQC1 DQC5 V

SS

GW V

SS

DQB5 DQB1

J

V

DDQ

V

DD

DP V

DD

QE V

DD

V

DDQ

K

DQD1 DQD5 V

SS

CK V

SS

DQA5 DQA1

L

DQD2 DQD6 BD SCD BA DQA6 DQA2

M

V

DDQ

DQD78 V

SS

BW V

SS

DQA7 V

DDQ

N

DQD3 DQD8 V

SS

A1 V

SS

DQA8 DQA3

P

DQD4 DQD9 V

SS

A0 V

SS

DQA9 DQA4

R

NC A2 LBO V

DD

FT A13 PE

T

NC NC A10 A11 A12 NC ZZ

U

V

DDQ

Q TMS TDI TCK TDO NC V

DDQ

Rev: 1.15 5/2001 3/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88218 Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9 V

DDQ

B

NC E2 A4 ADSC A15 A17 NC

C

NC A5 A3 V

DD

A14 A16 NC

D

DQB1 NC V

SS

ZQ V

SS

DQA9 NC

E

NC DQB2 V

SS

E1 V

SS

NC DQA8

F

V

DDQ

NC V

SS

G V

SS

DQA7 V

DDQ

G

NC DQB3 BB ADV NC NC DQA6

H

DQB4 NC V

SS

GW V

SS

DQA5 NC

J

V

DDQ

V

DD

DP V

DD

QE V

DD

V

DDQ

K

NC DQB5 V

SS

CK V

SS

NC DQA4

L

DQB6 NC NC SCD BA DQA3 NC

M

V

DDQ

DQB7 V

SS

BW V

SS

NC V

DDQ

N

DQB8 NC V

SS

A1 V

SS

DQA2 NC

P

NC DQB9 V

SS

A0 V

SS

NC DQA1

R

NC A2 LBO V

DD

FT A13 PE

T

NC A10 A11 NC A12 A18 ZZ

U

V

DDQ

TMS TDI TCK TDO NC V

DDQ

Rev: 1.15 5/2001 4/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88218/36 BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

A2, A3, A5, A6, B3, B5, B6, C2, C3,

C5, C6, R2, R6, T3, T5

An I Address Inputs

T4 An I Address Inputs (x36 Version)
T2, T6 NC — No Connect (x36 Version)
T2, T6 An I Address Inputs (x18 Version)

K7, K6, L7, L6, M6, N7, N6, P7, P6
H7, H6, G7, G6, F6, E7, E6, D7, D6
H1, H2, G1, G2, F2, E1, E2, D1, D2

K1, K2, L1, L2, M2, N1, N2, P1, P2

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9

I/O Data Input and Output pins (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BB I Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

NC — No Connect (x18 Version)

K4 CK I Clock Input Signal; active high
M4 BW I Byte Write—Writes all enabled bytes; active low
H4 GW I Global Write Enable—Writes all bytes; active low

E4 E1 I Chip Enable; active low

B2 E2 I Chip Enable; active high

F4 G I Output Enable; active low
G4 ADV I Burst address counter advance enable; active low

A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

T7 ZZ I Sleep Mode control; active high
R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low

L4 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control
R7 PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

J3 DP I Data Parity Mode Input; 1 = Even, 0 = Odd

J5 QE O Parity Error Out; Open Drain Output

D4 ZQ I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

B1, C1, R1, T1, B7, C7, U6 NC — No Connect

Rev: 1.15 5/2001 5/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

BPR2000.002.14

U2 TMS I Scan Test Mode Select
U3 TDI I Scan Test Data In
U5 TDO O Scan Test Data Out
U4 TCK I Scan Test Clock

J2, C4, J4, R4, J6

V

DD

I Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

V

SS

I I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

V

DDQ

I Output driver power supply

GS88218/36 BGA Pin Description

Pin Location Symbol Type Description

Rev: 1.15 5/2001 6/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88218/36 (PE = 0) Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx9

DP

Parity

QE

Parity

Encode

Compare

36

4

36

36

4

32

Note: Only x36 version shown for simplicity.

SCD

36

36

D Q

Register

4

E1

E2

Rev: 1.15 5/2001 7/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88218/36 (PE = 1) X16x32 Mode Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx8

DP

Parity

QE

Parity

Encode

Compare

32

4

32

36

4

32

Note: Only x36 version shown for simplicity.

SCD

D Q

Register

D Q

Register

Parity

Encode

32

4

32

36

E1

E2

Rev: 1.15 5/2001 8/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

ByteSafe™ Parity Functions

In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16
mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it
along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an
error in the cycle following parity check.
In x32/x16 mode the device does not drive the 9th data output, even though the internal ByteSafe parity encoding has been
activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in applications where parity encoding or
checking are not otherwise available. As in any system that checks read parity, reads of un-written memory locations may well
produce parity errors. Initialization of the memory should be implemented to avoid this issue.

In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write
cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write
data errors are reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high to set
the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data validity is
best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error.
Multiple Parity Error Output pins may share a common pull-up resistor.

x32 Mode (PE = 1) Read Parity Error Output Timing Diagram

CK

Address A Address B Address C Address D Address E Address F

D Out A D Out B D Out C D Out D D Out E

tKQ

tLZ

DQ

QE

Flow Through ModePipelined Mode

D Out A D Out B D Out C D Out D

tKQ

tLZ

DQ

QE

Err A

Err A Err C

Err C

tHZ

tKQX

tHZ

tKQX

Rev: 1.15 5/2001 9/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

x18/x36 Mode (PE = 0) Write Parity Error Output Timing Diagram

BPR 1999.05.18

CK

D In A D In B D In C D In D D In E

tKQ

tLZ

DQ

QE

Flow Through ModePipelined Mode

tKQ

tLZ

DQ

QE

D In A D In B D In C D In D D In E

Err A

Err A Err C

Err C

tHZ

tKQX

tHZ

tKQX

Rev: 1.15 5/2001 10/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Note:
There are pull-up devices on the LBO, ZQ, SCD, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be
unconnected and the chip will operate in the default states as specified in the above table.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or
x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

L Linear Burst

H or NC Interleaved Burst

Output Register Control FT

L Flow Through

H or NC Pipeline

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Single / Dual Cycle Deselect Control SCD

L Dual Cycle Deselect

H or NC Single Cycle Deselect

ByteSafe Data Parity Control DP

L Check for Odd Parity

H or NC Check for Even Parity

Parity Enable PE

L or NC Activate 9th I/Os (x18/36 Mode)

H Deactivate 9th I/Os (x16/32 Mode)

FLXDrive Output Impedance Control ZQ

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01

4th address 11 10 01 00

Rev: 1.15 5/2001 11/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Rev: 1.15 5/2001 12/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Synchronous Truth Table

Operation

Address

Used

State

Diagram

Key

5

E

2

ADSP ADSC ADV

W

3

DQ

4

Deselect Cycle, Power Down None X X X L X X High-Z

Deselect Cycle, Power Down None X F L X X X High-Z

Deselect Cycle, Power Down None X F H L X X High-Z

Read Cycle, Begin Burst External R T L X X X Q

Read Cycle, Begin Burst External R T H L X F Q

Write Cycle, Begin Burst External W T H L X T D

Read Cycle, Continue Burst Next CR X H H L F Q

Read Cycle, Continue Burst Next CR X X H L F Q

Write Cycle, Continue Burst Next CW X H H L T D

Write Cycle, Continue Burst Next CW X X H L T D
Read Cycle, Suspend Burst Current X H H H F Q
Read Cycle, Suspend Burst Current X X H H F Q

Write Cycle, Suspend Burst Current X H H H T D
Write Cycle, Suspend Burst Current X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E2 = 1; E = F (False) if E2 = 0

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active
drivers (shown as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to
accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items
above.

Rev: 1.15 5/2001 13/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W R

XX

X

Simple Synchronous OperationSimple Burst Synchronous Operation

CR

R

CW CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1and E2) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.

Rev: 1.15 5/2001 14/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W

R

X

X

X

CR

R

CW CR

CR

W

CW

W

CW

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.

Rev: 1.15 5/2001 15/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V

DDQ

≤ 2.375 V

(i.e., 2.5 V I/O) and 3.6 V ≤ V

DDQ

≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V

DD

+2 V with a pulse width not to exceed 20% tKC.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

Voltage on VDD Pins

–0.5 to 4.6 V

V

DDQ

Voltage in V

DDQ

Pins –0.5 to V

DD

V

V

CK

Voltage on Clock Input Pin –0.5 to 6 V

V

I/O

Voltage on I/O Pins

–0.5 to V

DDQ

+0.5 (≤ 4.6 V max.)

V

V

IN

Voltage on Other Input Pins

–0.5 to V

DD

+0.5 (≤ 4.6 V max.)

V

I

IN

Input Current on Any Pin +/–20 mA

I

OUT

Output Current on Any I/O Pin +/–20 mA

P

D

Package Power Dissipation 1.5 W

T

STG

Storage Temperature –55 to 125

o

C

T

BIAS

Temperature Under Bias –55 to 125

o

C

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage

V

DD

3.135 3.3 3.6 V

I/O Supply Voltage

V

DDQ

2.375 2.5

V

DD

V 1

Input High Voltage

V

IH

1.7 —

V

DD

+0.3

V 2

Input Low Voltage

V

IL

–0.3 — 0.8 V 2

Ambient Temperature (Commercial Range Versions)

T

A

0 25 70 °C 3

Ambient Temperature (Industrial Range Versions)

T

A

–40 25 85 °C 3

Rev: 1.15 5/2001 16/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Note: These parameters are sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 3.3 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

C

IN

V

IN

= 0 V

4 5 pF

Input/Output Capacitance

C

I/O

V

OUT

= 0 V

6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single

R

ΘJA

40 °C/W 1,2

Junction to Ambient (at 200 lfm) four

R

ΘJA

24 °C/W 1,2

Junction to Case (TOP) —

R

ΘJC

9 °C/W 3

20% tKC

VSS – 2.0 V

50%

V

SS

V

IH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

V

DD

V

IL

Rev: 1.15 5/2001 17/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

I

IL

V

IN

= 0 to V

DD

–1 uA 1 uA

ZZ Input Current

I

INZZ

V

DD ≥ VIN ≥ VIH

0 V ≤ V

IN

≤ V

IH

–1 uA
–1 uA

1 uA

300 uA

Mode Pin Input Current

I

INM

V

DD ≥ VIN ≥ VIL

0 V ≤ V

IN

≤ V

IL

–300 uA

–1 uA

1 uA
1 uA

Output Leakage Current

I

OL

Output Disable,

V

OUT

= 0 to V

DD

–1 uA 1 uA

Output High Voltage

V

OH

I

OH

= –8 mA, V

DDQ

= 2.375 V

1.7 V —

Output High Voltage

V

OH

I

OH

= –8 mA, V

DDQ

= 3.135 V

2.4 V —

Output Low Voltage

V

OL

I

OL

= 8 mA

— 0.4 V

DQ

VT = 1.25 V

50Ω

30pF

*

DQ

2.5 V

Output Load 1

Output Load 2

225Ω

225Ω

5pF

*

* Distributed Test Jig Capacitance

Rev: 1.15 5/2001 18/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Operating Currents

Parameter Test Conditions Symbol

-11 -11.5 -100 -80 -66
Unit

0 to

70°C

-40 to
85°C

0 to

70°C

-40 to
85°C

0 to

70°C

-40 to
85°C

0 to

70°C

-40 to
85°C

0 to

70°C

-40 to
85°C

Operating

Current

Device Selected;

All other inputs

≥VIH or ≤ V

IL

Output open

I

DD

Pipeline

225 235 225 235 225 235 200 210 185 195 mA

I

DD

Flow-Thru

180 190 180 190 180 190 175 185 165 175 mA

Standby

Current

ZZ ≥ V

DD

- 0.2V

I

SB

Pipeline

30 40 30 40 30 40 30 40 30 40 mA

I

SB

Flow-Thru

30 40 30 40 30 40 30 40 30 40 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ V

IL

I

DD

Pipeline

80 90 80 90 80 90 70 80 60 70 mA

I

DD

Flow-Thru

65 75 65 75 65 75 55 65 50 60 mA

Rev: 1.15 5/2001 19/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Parameter Symbol

-11 -11.5 -100 -80 -66
Unit

Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 10 — 10 — 10 — 12.5 — 15 — ns

Clock to Output Valid tKQ — 4.0 — 4.0 — 4.0 — 4.5 — 5.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Flow-

Thru

Clock Cycle Time tKC 15.0 — 15.0 — 15.0 — 15.0 — 20.0 — ns

Clock to Output Valid tKQ — 11.0 — 11.5 — 12.0 — 14.0 — 18.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.7 — 1.7 — 2 — 2 — 2.3 — ns

Clock LOW Time tKL 2 — 2 — 2.2 — 2.2 — 2.5 — ns

Clock to Output in High-Z

tHZ

1

1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8 ns

G to Output Valid tOE — 4.0 — 4.2 — 4.5 — 4.5 — 4.8 ns

G to output in Low-Z

tOLZ

1

0 — 0 — 0 — 0 — 0 — ns

G to output in High-Z

tOHZ

1

— 4.0 — 4.2 — 4.5 — 4.5 — 4.8 ns

Setup time tS 1.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

tZZS

2

5 — 5 — 5 — 5 — 5 — ns

ZZ hold time

tZZH

2

1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns

Rev: 1.15 5/2001 20/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

CK

ADSP

ADSC

ADV

GW

BW

WR2 WR3

WR1

WR1

WR2 WR3

tKC

Single Write

Burst Write

tKL

tKH

tS

tH

tS

tH

tS

tH

tS

tH

tS tH

tS

tH

tS

tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E inactive

A0–An

BA–BD

DQA–DQD

Write

Deselected

WR1 WR2 WR3

Write Cycle Timing

E1

tS

tH

E2 only sampled with ADSP or ADSC

E1 masks ADSP

Deselected with E2

G

tS

tH

D2A D2B

D2C D2D D3A

D1A

Hi-Z

tS

tH

E2

Rev: 1.15 5/2001 21/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Q1A

Q3A

Q2D

Q2cQ2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2 RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BA–BD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

tH

tH

E1 masks ADSP

Deselected with E2

E1

tS

tS

E2

E2 only sampled with ADSP or ADSC

Rev: 1.15 5/2001 22/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Flow Through Read-Write Cycle Timing

CK

ADSP

ADV

GW

BW

G

Q1A D1A

Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE

tOHZ

tS

tH

tS

tH

tH

tS

tH

tS tH

tKH

DQA–DQD

BA–BD

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Q2A

Burst wrap around to it’s initial state

WR1

E1

tS

tS

tH

E1 masks ADSP

E2 only sampled with ADSP and ADSC

tH

ADSC

tS

tH

ADSC initiated read

RD1

WR1

RD2

tS

tH

A0–An

E2

Rev: 1.15 5/2001 23/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

CK

ADSP

ADV

GW

BW

G

Q1A

D1A Q2A

Q2B Q2c

Q2D

Single Read Burst Read

tOE tOHZ

tS

tH

tS tH

tH

tS tH

tS

tH

tKH

DQA–DQD

BWA–BWD

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Pipelined SCD Read - Write Cycle Timing

WR1

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS

tH

ADSC initiated read

E1

tS

E1 masks ADSP

tH

tS

tH

E2 only sampled with ADSP and ADSC

E2

Rev: 1.15 5/2001 24/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Pipelined SCD Read Cycle Timing

Q1A

Q3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BWA–BWD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

tH

tH

E1 masks ADSP

E2 only sampled with ADSP or ADSC

Deselected with E2

E1

tS

tS

E2

Rev: 1.15 5/2001 25/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Pipelined DCD Read Cycle Timing

Q1A

Q3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tH

tH

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

E1 masks ADSP

E2 only sampled with ADSP or ADSC

Single Read

ADSP is blocked by E1 inactive

A0–An

BA–BD

E1

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

tS

tS

RD1

Hi-Z

E2

Rev: 1.15 5/2001 26/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Pipelined DCD Read-Write Cycle Timing

CK

ADSP

ADV

GW

BW

G

WR1

Q1A

D1a Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE tOHZ

tS

tH

tS tH

tH

tS

tH

tS

tH

tKH

DQA–DQD

tKL

tKC

tS

Single Write

ADSP is blocked by E1 inactive

tKQ

tS

tH

Hi-Z

BA–BD

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS

tH

ADSC initiated read

E1

tS

E1 masks ADSP

tH

tS

tH

E2 only sampled with ADSP and ADSC

E2

Rev: 1.15 5/2001 27/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some
functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP
(Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of
Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

CK

ADSP

ADSC

tH

tKH

tKL

tKC

tS

ZZ

tZZR

tZZH

tZZS

~

~

~

~

~

~

~

~

~

~

~

~

Snooze

Sleep Mode Timing Diagram

Rev: 1.15 5/2001 28/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

JTAG Port Registers

Overview

The various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS
as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and
push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAMs JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP
instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the
falling edge of TCK.

TMS

Test Mode

Select

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state
machine. An undriven TMS input will produce the same result as a logic one input level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed
between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP
Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to
the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input
level.

TDO Test Data Out Out

Output that is active depending on the state of the TAP state machine. Output changes in response to the
falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Rev: 1.15 5/2001 29/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1­compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
device will not perform EXTEST, INTEST or the SAMPLE/PRELOAD command.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

1
1

10 9 8 7 6 5 4 3 2 1 0

x36

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x32

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x18

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1

x16

X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1

Instruction Register

ID Code Register

Boundary Scan Register

012

012

· · · ·

31 30 29

012

· · ·

· · ·· · ·

n

0

Bypass Register

TDI

TDO

TMS
TCK

Test Access Port (TAP) Controller

Rev: 1.15 5/2001 30/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc­tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con­tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data cap­ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0

0

1

0

1

1

0

0

1

1

1

0

0

1

1

0

0

0

0

1

1

0 0

1

1 0

0

0

1

1 1 1

Rev: 1.15 5/2001 31/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update­DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not 1149.1-compliant. Neverthe­less, this RAM’s TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction regis­ter the RAM responds just as it does in response to the BYPASS instruction described above.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant *

1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.

1

RFU 011

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1 Compliant *

1

GSI 101 GSI private instruction. 1

RFU 110

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.15 5/2001 32/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

Test Port Input High Voltage

V

IHT

1.7

V

DD

+0.3

V 1, 2

Test Port Input Low Voltage

V

ILT

–0.3 0.8 V 1, 2

TMS, TCK and TDI Input Leakage Current

I

INTH

–300 1 uA 3

TMS, TCK and TDI Input Leakage Current

I

INTL

–1 1 uA 4

TDO Output Leakage Current

I

OLT

–1 1 uA 5

Test Port Output High Voltage

V

OHT

2.4 — V 6, 7

Test Port Output Low Voltage

V

OLT

— 0.4 V 6, 8

Notes:

1. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DD

+2 V with a pulse width not to exceed 20%

tTKC.

3. V

DD ≥ VIN ≥ VIL

4. 0 V ≤ V

IN

≤ V

IL

5. Output Disable, V

OUT

= 0 to V

DD

6. The TDO output driver is served by the VDD supply.

7. I

OH

= –4 mA

8. I

OL

= +4 mA

Notes:

1. Include scope and jig capacitance.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

DQ

VT = 1.25 V

50Ω

30pF

*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Rev: 1.15 5/2001 33/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 20 — ns

TCK Low to TDO Valid tTKQ — 10 ns

TCK High Pulse Width tTKH 10 — ns

TCK Low Pulse Width tTKL 10 — ns

TDI & TMS Set Up Time tTS 5 — ns

TDI & TMS Hold Time tTH 5 — ns

tTKQ

tTS tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

Rev: 1.15 5/2001 34/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

GS88218/36B BGA Boundary Scan Register

Note:

1. The Boundary Scan Register contains a number of registers that are not connected to any pin. They default to the value shown at reset.

2. Registers are listed in exit order (i.e., Location 1 is the first out of the TDO pin).

3. NC = No Connect, NA = Not Active

Order

x36 x18

Bump

x36 x18

1 PE 7R
2 PH = 0 n/a
3 A10 3T 2T
4 A11 4T 3T
5 A12 5T
6 A13 6R
7 A14 5C
8 A15 5B
9 A16 6C

10

x36 = DQA9

x32 = NA = 0

NC = 1 6P

11 DQA8 NC = 1 7N
12 DQA4 NC = 1 6M
13 DQA3 NC = 1 7L
14 DQA7 NC = 1 6K
15 DQA6 DQA1 7P
16 DQA5 DQA2 6N
17 DQA2 DQA3 6L
18 DQA1 DQA4 7K
19 ZZ 7T
20 QE 5J
21 DQB5 DQA5 6H
22 DQB1 DQA6 7G
23 DQB2 DQA7 6F
24 DQB6 DQA8 7E

25 DQB3

x18 =DQA9

x16 = NA = 0

7H 6D

26 DQB4 NC = 1 6G
27 DQB7 NC = 1 6E
28 DQB8 NC = 1 7D

29

x36 = DQB9

x32 = NA = 0

A18

6D 6T

30 A9 6A
31 A8 5A
32 ADV 4G
33 ADSP 4A
34 ADSC 4B
35 G 4F
36 BW 4M
37 GW 4H
38 CK 4K
39 PH = 0 n/a
40 PH = 0 n/a
41 A17 6B
42 BA 5L
43 BB BB 5G 3G
44 BC NC = 1 3G 5G
45 BD NC = 1 3L
46 CE2 2B
47 CE1 4E
48 A7 3A
49 A6 2A

50

x36 =DQC9

x32 = NA = 0

NC = 1 2D

51 DQC8 NC = 1 1E
52 DQC4 NC = 1 2F
53 DQC3 NC = 1 1G
54 DQC7 NC = 1 2H
55 DQC6 DQB1 1D
56 DQC5 DQB2 2E
57 DQC2 DQB3 2G
58 DQC1 DQB4 1H
59 FT 5R

Order

x36 x18

Bump

x36 x18

60 DP 3J
61 SCD 4L
62 DQD1 DQB5 2K
63 DQD2 DQB6 1L
64 DQD5 DQB7 2M
65 DQD6 DQB8 1N

66 DQD3

x18 = DQB9

x16 = NA = 0

1K 2P

67 DQD4 NC = 1 2L
68 DQD7 NC = 1 2N
69 DQD8 NC = 1 1P

70

x36 = DQD9

x32 = NA = 0

NC = 1 2P 1K

71 LBO 3R
72 A5 2C
73 A4 3B
74 A3 3C
75 A2 2R
76 A1 4N
77 A0 4P
78 ZQ 4D

BPR 1999.08.11

Order

x36 x18

Bump

x36 x18

Rev: 1.15 5/2001 35/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

FLXDrive Output Driver Characteristics

BPR 2000.02.14

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

80.0

100.0

120.0

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)

VDDQ - V Out (Pull Up)

I Out (mA)

3.6V PD HD 3.3V PD HD 3.1V PD HD 3.6V PD LD 3.3V PD LD 3.1V PD LD

3.1V PU LD 3.3V PU LD 3.6V PU LD 3.1V PU HD 3.3V PU HD 3.6V PU HD

Pull Up Drivers

Pull Down Drivers

VDD

VOut

I Out

VSS

Rev: 1.15 5/2001 36/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Package Dimensions—119 Pin BGA

BPR 1999.05.18

N

P

A

B

Pin 1
Corner

K

E

F

C T

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

G

S

D

1234567

Package Dimensions—119-Pin BGA

Unit: mm

Symbol Description Min Nom Max

A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) — — 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70

F Package Height (excluding balls) — 1.46 1.70
G Width between Balls — 1.27 —
K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width — 12.00 —
P Foot Length — 19.50 —
R Width of package between balls — 7.62 —
S Length of package between balls — 20.32 —

T Variance of Ball Height — 0.15 —

Bottom View

R

Top View

Side View

Rev: 1.15 5/2001 37/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

Ordering Information for GSI Synchronous Burst RAMs

Org

Part Number

1

Type Package

Speed

2

(MHz/ns)

T

A

3

Status

514K x 18 GS88218B-11 ByteSafe S/DCD Pipeline/Flow Through BGA 100/11 C
514K x 18 GS88218B-11.5 ByteSafe S/DCD Pipeline/Flow Through BGA 100/11.5 C
514K x 18 GS88218B-100 ByteSafe S/DCD Pipeline/Flow Through BGA 100/12 C
514K x 18 GS88218B-80 ByteSafe S/DCD Pipeline/Flow Through BGA 80/14 C
514K x 18 GS88218B-66 ByteSafe S/DCD Pipeline/Flow Through BGA 66/18 C
256K x 36 GS88236B-11 ByteSafe S/DCD Pipeline/Flow Through BGA 100/11 C
256K x 36 GS88236B-11.5 ByteSafe S/DCD Pipeline/Flow Through BGA 100/11.5 C
256K x 36 GS88236B-100 ByteSafe S/DCD Pipeline/Flow Through BGA 100/12 C
256K x 36 GS88236B-80 ByteSafe S/DCD Pipeline/Flow Through BGA 80/14 C
256K x 36 GS88236B-66 ByteSafe S/DCD Pipeline/Flow Through BGA 66/18 C
514K x 18 GS88218B-11I ByteSafe S/DCD Pipeline/Flow Through BGA 100/11 I
514K x 18 GS88218B-11.5I ByteSafe S/DCD Pipeline/Flow Through BGA 100/11.5 I
514K x 18 GS88218B-100I ByteSafe S/DCD Pipeline/Flow Through BGA 100/12 I
514K x 18 GS88218B-80I ByteSafe S/DCD Pipeline/Flow Through BGA 80/14 I
514K x 18 GS88218B-66I ByteSafe S/DCD Pipeline/Flow Through BGA 66/18 I
256K x 36 GS88236B-11I ByteSafe S/DCD Pipeline/Flow Through BGA 100/11 I
256K x 36 GS88236B-11.5I ByteSafe S/DCD Pipeline/Flow Through BGA 100/11.5 I
256K x 36 GS88236B-100I ByteSafe S/DCD Pipeline/Flow Through BGA 100/12 I
256K x 36 GS88236B-80I ByteSafe S/DCD Pipeline/Flow Through BGA 80/14 I
256K x 36 GS88236B-66I ByteSafe S/DCD Pipeline/Flow Through BGA 66/18 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88218BT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.15 5/2001 38/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

8M Synchronous Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes
Format or Content

Page;Revisions;Reason

GS88218/36BRev1.04h 5/

1999;

1.05 9/1999I

Format/Typos

• Last Page/Fixed “GSGS..” in Ordering Information Note.

• Fromatted Pin Outs and Pin Description to new small caps.

• Formatted Block diagrams to new small caps.

• Formatted Timing Diagrams to new small caps.

• Changed “Flow thru” to “Flow Through” in Timing Diagrams.

• Boundary Scan Register/Formatted to new small caps.

Content

• 5/Fixed pin description table to match pinouts.

• Pin Description/Changed chip enables to match pins.

• Pin Description/Took 4A out of NC x18 row.

• Pin Description/Reversed 4P and 4N to be consistent with A0
and A1.

• Pin Description?Changed 2H to 1H in x18 Data I/O’s.

• Boundary Scan Register/Corrected sequence of Data I/O
pins.

• Boundary Scan Register?Minor corrections and comments
invisible.

GS88218/36B1.05 9/

1999I;1.06 11/1999J

Content

• Changed 4J to VDD in Pad out.

• Changed 5J to QE.

• First Release of 880 F.

GS88218/36B1.06 11/

1999J;1.07 11/1999K

content

• Changed Bump 3C to 4L on first page to correspond SCD pin
in BGA pinout.

GS8821836 Rev 1.07 11/

1999;

GS8821836 Rev 1.08 3/2000

Content

• Changed speed bin to 150 - 80 Mhz

• Correction on page 8. x32 Mode (PE = 0) Changed to (PE = 1)

• Correction on page 9. x18/x36 Mode (PE = 1) Changed to (PE
= 0)

GS88218/36B1.0 3/2000;

GS88218/36B1.0 3/2000O;

Content

• Corrections to AC Electrical Characteristics Table -

GS88218/36B1.0 3/2000O;

88218_r1_10

Content

• Updated BSR table on page 37 (see order 39 & 60)

• Updated ADSC, E1 and E2 on timing diagrams on pages 25,
26, & 29

88218_r1_10; 88218_r1_11 Content

• Updated diagrams on pages 8 & 9

88218_r1_11; 88218_r1_12 Content

• Updated BGA pin description to meet JEDEC standard

Rev: 1.15 5/2001 39/39 © 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88218/36B-11/11.5/100/80/66

88218_r1_12; 88218_r1_13 Content/Format

• Deleted 150 MHz references

• Changed 133 MHz references to 11 ns

• Changed 117 MHz references to 11.5 ns

• Used 100 MHz Pipeline mode numbers for 11 ns and 11.5 ns

• Added 66 MHz speed bin

• Updated format to comply with Technical Publications
standards

88218_r1_13; 88218_r1_14 Content

• Updated Capitance table—removed Input row and changed
Output row to I/O

88218_r1_14; 88218_r1_15 Content

• Updated Synchronous Truth Table (deleted E1 reference)

8M Synchronous Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes
Format or Content

Page;Revisions;Reason