Datasheet GS880Z18T-80I, GS880Z18T-80, GS880Z18T-66I, GS880Z18T-66, GS880Z18T-11I Datasheet (GSI)

Preliminary

GS880Z18/36T-11/100/80/66

100-Pin TQFP

8Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAMs

Features

• 512K x 18 and 256K x 36 configurations

• User configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization

• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs

• Pin compatible with 2M, 4M and 16M (future) devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO

pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

-11 -100 -80 -66

t
Pipeline
3-1-1-1

Flow Through
2-1-1-1

Cycle

t
I

t

t

Cycle

I

KQ
DD

KQ

DD

10 ns

4.5 ns

210 mA

11 ns
15 ns

150 mA

10 ns

4.5 ns

210 mA

12 ns
15 ns

150 mA

12.5 ns

4.8 ns

190 mA

14 ns
15 ns

130 mA

15 ns

5 ns

170 mA

18 ns
20 ns

130 mA

Functional Description

The GS880Z18/36T is an 8Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single

100 MHz–66 MHz

3.3 V V

2.5 V and 3.3 V V

late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS880Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.

The GS880Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­standard 100-pin TQFP package.

DD

DDQ

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Rev: 1.10 8/2000 1/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

A B C D E F

R W R W R W

Q

A

D

B

Q

A

Q

C

D

B

D

D

Q

C

Q

E

D

D

Q

E

GS880Z18T Pinout

Preliminary.

GS880Z18/36T-11/100/80/66

DD

SS

A6

E1

A7

E2

NC

NC

E3

BB

V

BA

V

CKE

W

G

CK

ADV

A8

A17

NC

A9

NC
NC
NC

V

DDQ

V

NC

NC
DQB1
DQB2

V

V

DDQ

DQB3
DQB4

V

V

V
DQB5
DQB6

V

DDQ

V
DQB7
DQB8
DQB9

NC

V
V

DDQ

NC
NC
NC

SS

SS

FT

DD
DD

SS

SS

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

512K x 18

Top View

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A18
NC
NC
V

DDQ

V

SS

NC
DQA9
DQA8
DQA7
V

SS

V

DDQ

DQA6
DQA5
V

SS

NC
V

DD

ZZ
DQA4
DQA3
V

DDQ

V

SS

DQA2
DQA1
NC
NC
V

SS

V

DDQ

NC
NC
NC

SS

A5

A4

A3

A2

A1

A0

LBO

NC

DD

NC

V

NC

NC

V

A11

A10

A12

A13

A14

A16

A15

Rev: 1.10 8/2000 2/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS880Z36T Pinout

Preliminary.

GS880Z18/36T-11/100/80/66

DD

SS

A6

E1

A7

E2

BC

BD

E3

BB

V

BA

V

CKE

W

G

CK

ADV

A8

A17

NC

A9

DQC9
DQC8
DQC7

V

DDQ

V
DQC6
DQC5
DQC4
DQC3

V

V

DDQ

DQC2
DQC1

V
V
V

DQD1
DQD2

V

DDQ

V

DQD3
DQD4
DQD5
DQD6

V

V

DDQ

DQD7
DQD8
DQD9

SS

SS

FT

DD
DD
SS

SS

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

256K x 36

Top View

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQB9
DQB8
DQB7
V

DDQ

V

SS

DQB6
DQB5
DQB4
DQB3
V

SS

V

DDQ

DQB2
DQB1
V

SS

NC
V

DD

ZZ
DQA1
DQA2
V

DDQ

V

SS

DQA3
DQA4
DQA5
DQA6
V

SS

V

DDQ

DQA7
DQA8
DQA9

SS

A5

A4

A3

A2

A1

A0

LBO

NC

DD

NC

NC

V

NC

V

A11

A10

A12

A13

A14

A16

A15

Rev: 1.10 8/2000 3/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS880Z18/36T-11/100/80/66

100 Pin TQFP Pin Descriptions

Pin Location Symbol Type Description

37, 36 A0, A1 In Burst Address Inputs; preload the burst counter

35, 34, 33, 32, 100, 99, 83, 82,

81, 50, 49, 48, 47, 46, 45, 44

80 A18 In Address Input (x18 Version Only)
89 CK In Clock Input Signal
93 BA In Byte Write signal for data inputs DQA1-DQA9; active low
94 BB In Byte Write signal for data inputs DQB1-DQB9; active low
95 BC In Byte Write signal for data inputs DQC1-DQC9; active low (x32/x36 Versions Only)
96 BD In Byte Write signal for data inputs DQD1-DQD9; active low (x32/x36 Versions Only)
88 W In Write Enable; active low
98 E1 In Chip Enable; active low
97 E2 In Chip Enable; active high; for self decoded depth expansion
92 E3 In Chip Enable; active low, for self decoded depth expansion
86 G In Output Enable; active low
85 ADV In Advance / Load—Burst address counter control pin
87 CKE In Clock Input Buffer Enable; active low

58, 59, 62,63, 68, 69, 72, 73, 74 DQA1–DQA9 I/O Byte A Data Input and Output pins (x18 Version Only)

8, 9, 12, 13, 18, 19, 22, 23, 24 DQB1–DQB9 I/O Byte B Data Input and Output pins (x18 Version Only)

51, 52, 53, 56, 57, 75, 78, 79,

1, 2, 3, 6, 7, 25, 28, 29, 30, 95,

96

51, 52, 53, 56, 57, 58, 59, 62,63 DQA1–DQA9 I/O Byte A Data Input and Output pins (x36 Versions Only)

68, 69, 72, 73, 74, 75, 78, 79, 80 DQB1–DQB9 I/O Byte B Data Input and Output pins (x36 Versions Only)

1, 2, 3, 6, 7, 8, 9, 12, 13 DQC1–DQC9 I/O Byte C Data Input and Output pins (x36 Versions Only)

18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1–DQD9 I/O Byte D Data Input and Output pins (x36 Versions Only)

64 ZZ In Power down control; active high
14 FT In Pipeline/Flow Through Mode Control; active low
31 LBO In Linear Burst Order; active low

15, 16, 41, 65, 91

5,10, 17, 21, 26, 40, 55, 60, 67,

71, 76, 90

4, 11, 20, 27, 54, 61, 70, 77

38, 39, 42, 43, 66, 84 NC - No Connect

A2–A17 In Address Inputs

NC - No Connect (x18 Version Only)

V

V

DD

V

SS

DDQ

In 3.3 V power supply
In Ground
In 3.3 V output power supply for noise reduction

Preliminary.

Rev: 1.10 8/2000 4/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GS880Z18/36 NBT SRAM Functional Block Diagram

A

Preliminary.

GS880Z18/36T-11/100/80/66

DQa–DQn

FT

D Q

K

Sense Amps

Array

Memory

Write Drivers

Write Data

Write Data

K

Register 1

K

Register 2

FT

SA1’

SA0’

Burst

Counter

SA1

K

SA0

Register 2

Write Address

K

Register 1

D Q

K

LBO

0–A17

ADV

Write Address

K

Match

Read, Write and

W

BA

Control Logic

Data Coherency

K

E3

E2

BB

BC

E1

BD

CK

Rev: 1.10 8/2000 5/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

G

CKE

Preliminary.

GS880Z18/36T-11/100/80/66

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipelined Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.

Flow through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.

Rev: 1.10 8/2000 6/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

Synchronous Truth Table

Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first

2. Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is
sampled low, but no byte write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.

4. If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will
remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low

6. All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.10 8/2000 7/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipelined and Flow Through Read-Write Control State Diagram

Preliminary.

GS880Z18/36T-11/100/80/66

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

Current State (n)

Input Command Code

ƒ

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.10 8/2000 8/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline Mode Data I/O State Diagram

Preliminary.

GS880Z18/36T-11/100/80/66

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

Intermediate State (N+1)

R

D

Transition

Intermediate

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒ ƒ ƒ

Intermediate

State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.10 8/2000 9/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode Data I/O State Diagram

Preliminary.

GS880Z18/36T-11/100/80/66

W

B

High Z
(Data In)

Key Notes

Current State (n)

Input Command Code

ƒ

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram

Rev: 1.10 8/2000 10/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

Linear Burst Sequence

I

GS880Z18/36T-11/100/80/66

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note:
There are pull-up devices on the LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.

L Linear Burst

H or NC Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

Standby, IDD = I

SB

Burst Counter Sequences

nterleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Rev: 1.10 8/2000 11/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

ZZ

tZZS

Sleep

~

~

~

~

tZZR

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as VDD or V

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Pin 66, a No Connect (NC) on GSI’s GS880Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT
SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked VDD or V

pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature
may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or

tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up
resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs
(GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open
drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.

on pipelined parts and VSS on flow

DDQ

DDQ

on

Rev: 1.10 8/2000 12/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

CK

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Voltage on VDD Pins

Voltage in V

Pins –0.5 to V

DDQ

–0.5 to 4.6 V

DD

Voltage on Clock Input Pin –0.5 to 6 V

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o
o

V

V
V

C
C

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

Supply Voltage
I/O Supply Voltage
Input High Voltage

Input Low Voltage

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ V
(i.e., 2.5 V I/O) and 3.6 V ≤ V

≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.

DDQ

2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be –2 V > Vi < V

Rev: 1.10 8/2000 13/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

V

DD

V

DDQ

V

IH

V

IL

T

A

T

A

+2 V with a pulse width not to exceed 20% tKC.

DD

3.135 3.3 3.6 V

2.375 2.5

1.7 —

–0.3 — 0.8 V 2

0 25 70 °C 3

–40 25 85 °C 3

V

DD

V

+0.3

DD

V 1
V 2

≤ 2.375 V

DDQ

GS880Z18/36T-11/100/80/66

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

V

SS

50%

VSS – 2.0 V

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 3.3 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note: These parameters are sample tested.

Package Thermal Characteristics

VDD + 2.0 V

50%

V

DD

V

IL

C

IN

C

I/O

V

V

OUT

IN

= 0 V

= 0 V

20% tKC

4 5 pF
6 7 pF

Preliminary.

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four

Junction to Case (TOP) —

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

R
R
R

ΘJA
ΘJA

ΘJC

40 °C/W 1,2
24 °C/W 1,2

9 °C/W 3

Rev: 1.10 8/2000 14/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

4. Device is deselected as defined by the Truth Table.

DQ

and t

OLZ

Output Load 1

OHZ

Preliminary.

GS880Z18/36T-11/100/80/66

Output Load 2

2.5 V

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

Mode Pin Input Current

Output Leakage Current

Output High Voltage
Output High Voltage

Output Low Voltage

I

INZZ

I

INM

I

V
V
V

I

IL

OL

OH
OH
OL

50Ω

VT = 1.25 V

I

OH

I

OH

*

30pF

* Distributed Test Jig Capacitance

V

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V

V

DD ≥ VIN ≥ VIL

0 V

≤ V

≤ V

IN

IN

DD

≤ V

≤ V

IH

IL

Output Disable,

V

= 0 to V

OUT

= –8 mA, V
= –8 mA, V

I

OL

DDQ
DDQ

= 8 mA

DD

= 2.375 V
= 3.135 V

DQ

5pF

–1 uA 1 uA
–1 uA

–1 uA

300 uA

–300 uA

–1 uA

–1 uA 1 uA

1.7 V —

2.4 V —
— 0.4 V

*

1 uA

1 uA
1 uA

225Ω

225Ω

Rev: 1.10 8/2000 15/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Operating Currents

Parameter Test Conditions Symbol

Device Selected;

Operating

Current

Standby

Current

Deselect

Current

All other inputs

≥ V

or ≤ V

IH

IL

Output open

ZZ ≥ V

DD

- 0.2V

Device Deselected;

All other inputs

≥ V

or ≤ V

IH

IL

I

DD

Pipeline

I

DD

Flow-through

I

SB

Pipeline

I

SB

Flow-through

I

DD

Pipeline

I

DD

Flow-through

Preliminary.

GS880Z18/36T-11/100/80/66

-11 -100 -80 -66

0 to

-40 to

70°C

+85°C

210 220 210 220 190 200 170 180 mA

150 160 150 160 130 140 130 140 mA

30 40 30 40 30 40 30 40 mA

30 40 30 40 30 40 30 40 mA

80 90 80 90 70 80 65 75 mA

65 75 65 75 55 65 55 65 mA

0 to

70°C

-40 to
+85°C

0 to

70°C

-40 to

+85°C

0 to

70°C

-40 to

+85°C

Unit

Rev: 1.10 8/2000 16/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

AC Electrical Characteristics

Parameter Symbol

Clock Cycle Time tKC 10 — 10 — 12.5 — 15 — ns
Clock to Output Valid tKQ — 4.5 — 4.5 — 4.8 — 5 ns

Pipeline

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns
Clock to Output in Low-Z

tLZ

1

Clock Cycle Time tKC 15.0 — 15.0 — 15.0 — 20 — ns

Flow­through

Clock to Output Valid tKQ — 11.0 — 12.0 — 14.0 — 18.0 ns
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

Clock HIGH Time tKH 2 — 2 — 2 — 2.3 — ns
Clock LOW Time tKL 2.2 — 2.2 — 2.2 — 2..5 — ns

Clock to Output in High-Z

tHZ

1

G to Output Valid tOE — 4.5 — 4.5 — 4.8 — 5 ns
G to output in Low-Z

G to output in High-Z

tOLZ

tOHZ

1
1

Setup time tS 2.0 — 2.0 — — 2.0 — 2.0 ns
Hold time tH 0.5 — 0.5 — — 0.5 — 0.5 ns

ZZ setup time
ZZ hold time

tZZS
tZZH

2
2

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup
and hold times as specified above.

-11 -100 -80 -66

Min Max Min Max Min Max Min Max

Unit

1.5 — 1.5 — 1.5 — 1.5 — ns

3.0 — 3.0 — 3.0 — 3.0 — ns

1.5 4.5 1.5 4.5 1.5 4.8 1.5 5 ns

0 — 0 — 0 — 0 — ns

— 4.5 — 4.5 — 4.8 — 5 ns

5 — 5 — 5 — 5 — ns
1 — 1 — 1 — 1 — ns

Rev: 1.10 8/2000 17/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline Mode Read/Write Cycle Timing

1 2 3 4 5 6 7 8 9 10

CK

tH

CKE

E*

ADV

Bn

tS

tH

tS

tH

tS

tH

tS

tH

tS

tS

tH

tKHWtKL tKC

Preliminary.

GS880Z18/36T-11/100/80/66

A0–An

DQA–DQD

A1

A2 A3

D(A1)

tS

D(A2)

tH

G

COMMAND

Write
D(A1)

D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Write

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

A4 A5 A6 A7

tLZ

D

(A2+1)

Read
Q(A4)

tKQ

Q(A3)

tOHZ

BURST
Read
Q(A4+1)

tKQX

tOE

Q(A4)

Write
D(A5)

Q

(A4+1)

tOLZ

Read
Q(A6)

tHZ

DON’T CARE UNDEFINED

tKQX

Write
D(A7)

D(A5)

Q(A6)

DESELECT

Rev: 1.10 8/2000 18/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Pipeline Mode No-Op, Stall and Deselect Timing

Preliminary.

GS880Z18/36T-11/100/80/66

CK

CKE

E*

ADV

W

Bn

A0–An

DQ

1

tS

tS

tS

tS

A1 A5

2

tH

tH

tH

tH

A2 A3 A4

D(A1)

4

3

Q(A2)

5 6

Q(A3)

7

8

D(A4)

9

tKQX

10

tHZ

Q(A5)

NOP

Read
Q(A5)

DESELECT

CONTINUE
DESELECT

COMMAND

Write
D(A1)

Read
Q(A2)

STALL Read

Q(A3)

Write
D(A4)

STALL

DON’T CARE UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.10 8/2000 19/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode Read/Write Cycle Timing

Preliminary.

GS880Z18/36T-11/100/80/66

CK

CKE

E*

ADV

Bn

A0–An

DQ

tKHWtKL

tLZ

D

(A2+1)

4

5 6

7

8

9

10

tKC

A7

tKQ

Q(A3)

tOHZ

tKQX

tOE

Q(A4)

Q

(A4+1)

tOLZ

tHZ

tKQX

D(A5)

Q(A6)

1 2

tH

tS

tS

tS

tH

tS

tH

tS

tH

tS

tH

tH

3

A1 A2 A3 A4 A5 A6

D(A1)

tS

D(A2)

tH

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE

DESELECT

Write
D(A7)

UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.10 8/2000 20/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Flow Through Mode No-Op, Stall and Deselect Timing

Preliminary.

GS880Z18/36T-11/100/80/66

CK

CKE

E*

ADV

W

Bn

A0–An

DQ

1 2

tH

tS

tH

tS

tH

tS

A1 A5A2 A3 A4

D(A1)

3

4

Q(A2)

5 6

Q(A3)

7

D(A4)

8

tKQX

9

Q(A5)

10

tHZ

COMMAND

Write
D(A1)

Read
Q(A2)

STALL Read

Q(A3)

Write
D(A4)

STALL

NOP

Read
Q(A5)

DESELECT

CONTINUE
DESELECT

DON’T CARE UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.10 8/2000 21/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Output Driver Characteristics

I Out (mA)

120.0

100.0

Pull Down Drivers

80.0

60.0

40.0

Preliminary.

GS880Z18/36T-11/100/80/66

20.0

VDDQ

I Out

0.0

VOut

-20.0

VSS

-40.0

-60.0

Pull Up Drivers

-80.0

-100.0

-120.0

-140.0

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD HD 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 3.6V PU HD

BPR 1999.05.18

Rev: 1.10 8/2000 22/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

TQFP Package Drawing

D

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

L1

Preliminary.

GS880Z18/36T-11/100/80/66

θ

L

c

Pin 1

c Lead Thickness 0.09 — 0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75

L1 Lead Length — 1.00 —

Y Coplanarity — — 0.10

θ Lead Angle 0° — 7°

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

A1

e

D1

b

A2

Y

E1

E

BPR 1999.05.18

Rev: 1.10 8/2000 23/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

Ordering Information—GSI NBT Synchronous SRAM

2

Org

512K x 18 GS880Z18T-11 NBT Pipeline/Flow Through TQFP 100/11 C
512K x 18 GS880Z18T-100 NBT Pipeline/Flow Through TQFP 100/12 C
512K x 18 GS880Z18T-80 NBT Pipeline/Flow Through TQFP 80/14 C
512K x 18 GS880Z18T-66 NBT Pipeline/Flow Through TQFP 66/18 C
256K x 36 GS880Z36T-11 NBT Pipeline/Flow Through TQFP 100/11 C
256K x 36 GS880Z36T-100 NBT Pipeline/Flow Through TQFP 100/12 C
256K x 36 GS880Z36T-80 NBT Pipeline/Flow Through TQFP 80/14 C
256K x 36 GS880Z36T-66 NBT Pipeline/Flow Through TQFP 66/18 C
512K x 18 GS880Z18T-11I NBT Pipeline/Flow Through TQFP 100/11 I
512K x 18 GS880Z18T-100I NBT Pipeline/Flow Through TQFP 100/12 I
512K x 18 GS880Z18T-80I NBT Pipeline/Flow Through TQFP 80/14 I
512K x 18 GS880Z18T-66I NBT Pipeline/Flow Through TQFP 66/18 I
256K x 36 GS880Z36T-11I NBT Pipeline/Flow Through TQFP 100/11 I
256K x 36 GS880Z36T-100I NBT Pipeline/Flow Through TQFP 100/12 I
256K x 36 GS880Z36T-80I NBT Pipeline/Flow Through TQFP 80/14 I
256K x 36 GS880Z36T-66I NBT Pipeline/Flow Through TQFP 66/18 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS882Z36T-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

1

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

3

T

A

Status

Rev: 1.10 8/2000 24/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary.

GS880Z18/36T-11/100/80/66

DS/DateRev. Code: Old;

New

GS880Z18/36TRev1.04h 5/

1999;

1.05 9/1999

GS880Z18/36T 1.05 9/

1999K/ 1.06 10/1999

GS880Z18/36T 1.06 9/

1999K 1.07 1/2000L

GS880Z18/36T 1.07 1/

2000K 1.08 5/2000M

GS880Z18/36T 1.07 1/

2000K 1.08 5/2000M;

880Z18_r1_09

880Z18_r1_09;

880Z18_r1_10

Types of Changes
Format or Content

Format/Typos

Content

Format

Content

Content

Content

Content/Format

Page /Revisions/Reason

• Last Page/Fixed “GSGS..” in Ordering Information
Note.Document/Changed format of all E’s from EN to EN.

• Timing Diagrams/Changed format. ex. A0 to A0.

• Flow Through Timing Diagrams/Upper case “T” in Flow
Through. thru to Through.

• Pin outs/Block Diagrams -Updated format to small caps.

• Added Rev History.

• 5/Fixed TQFP pin description table to match pinout/
Enhancement.

• 5/Changed chip enables to match pins./Clarification

• Ordered Address inputs in pin description table to match pin
out.

• Changed Dimension D in Dimension table from 20.1 to 22.1/
Correction.

• Speed Bins on Page 1/Last column-changed 12ns to 15ns
and 15ns to 12ns.

• Improved Appearance of Timing Diagrams.

• Minor formatting changes.

• New GSI Logo.

• Pin 14 removed from ground section on page 4

• Grammar updates

• Timing diagrams updated on pages 18, 19, 20, and 21

• Pin Descriptions table on page 4 updated

• Features on page 1 updated

• Removed 166 MHz and 150 MHz speed bins

• Used 100 MHz Pipeline numbers for 133 MHz

• Changed all 133 MHz references to 11 ns

• Updated format to comply with Technical Publications
standards

• Updated Capitance table—removed Input row and changed
Output to I/O

Rev: 1.10 8/2000 25/25 © 1998, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com