Datasheet GS842Z18AB-180I, GS842Z18AGB-180, GS842Z18AGB-166, GS842Z18AGB-150, GS842Z18AGB-100 Datasheet (GSI TECHNOLOGY)

GS842Z18/36AB-180/166/150/100

119-Bump BGA

4Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAMs

Features

• 256K x 18 and 128K x 36 configurations

• User configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization

• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs

• Pin-compatible with 2M, 8M, and 16M devices

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA package

• RoHS-compliant package available

Functional Description

The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

180 MHz–100 MHz

3.3 V V

2.5 V and 3.3 V V

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge­triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­standard 119-bump BGA package.

LBO) must be tied to a power

DD

DDQ

Parameter Synopsis

–180 –166 –150 –100

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Rev: 1.03a 10/2006 1/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tCycle

t

KQ

I

DD

t

KQ

tCycle

I

DD

5.5 ns

3.2 ns

335 mA

8 ns

9.1 ns

210 mA

6.0 ns

3.5 ns

310 mA

8.5 ns
10 ns

190 mA

6.6 ns

3.8 ns

280 mA

10 ns
12 ns

165 mA

10 ns

4.5 ns

190 mA

12 ns
15 ns

135 mA

GS842Z18/36AB-180/166/150/100

GS842Z18A Pad Out—119-Bump BGA—Top View (Packge B)

1234567

A V

DDQ

AANCAAV

DDQ

B NC E2 AADVA E3 NC

C NC A A V

D DQ

E NC DQ

F V

B NC V

B V

DDQ

NC V

SS

SS

SS

DD

ZQ V

E1 V

G V

AANC

DQPA NC

SS

SS

SS

NC DQA

DQA V

DDQ

G NC DQB BB NC NC NC DQA

H DQB NC V

J V

DDQ

V

DD

K NC DQB V

SS

NC V

SS

W V

DD

CK V

SS

NC V

SS

DQA NC

V

DD

DDQ

NC DQA

L DQB NC NC NC BA DQA NC

M V

DDQ

DQB V

N DQB NC V

P NC DQP

B V

R NC A LBO V

SS

SS

SS

CKE V

A1 V

A0 V

DD

SS

SS

SS

NC V

DDQ

DQA NC

NC DQA

FT ANC

T NC A A NC A A ZZ

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

Rev: 1.03a 10/2006 2/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

GS842Z36A Pad Out— 119-Bump BGA—Top View (Package B)

1234567

A V

DDQ

AANCA8 AV

DDQ

B NC E2 AADVA E3 NC

C NC A A V

D DQ

E DQC DQC V

F V

C DQPC V

DDQ

DQC V

SS

SS

SS

DD

ZQ V

E1 V

G V

AANC

DQPB DQB

SS

DQB DQB

SS

DQB V

SS

DDQ

G DQC DQC BC NC BB DQB DQB

H DQC DQC V

J V

DDQ

V

DD

K DQD DQD V

SS

NC V

SS

W V

DD

CK V

SS

NC V

SS

DQB DQB

V

DD

DDQ

DQA DQA

L DQD DQD BD NC BA DQA DQA

M V

DDQ

N DQD DQD V

P DQD DQPD V

R NC A LBO V

DQD V

SS

SS

SS

CKE V

A1 V

A0 V

DD

DQA V

SS

SS

SS

DQA DQA

DQPA DQA

DDQ

FT ANC

T NC NC A A A NC ZZ

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

Rev: 1.03a 10/2006 3/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

GS842Z18/36A Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQA
DQB
DQC
DQD

BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQA I/Os; active low ( x36 Version)

CK I Clock Input Signal; active high

CKE I Clock Input Buffer Enable; active low

W I Write Enable. Writes all enabled bytes; active low

E1 I Chip Enable; active low

G I Output Enable; active low

ADV I Burst address counter advance enable; active high

ZZ I Sleep Mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

ZQ I

NC — No Connect

TMS I Scan Test Mode Select

TDI I Scan Test Data In

TDO O Scan Test Data Out

TCK I Scan Test Clock

V

DD

V

SS

V

DDQ

CK I Clock Input Signal; active high

I/O Data Input and Output pins

I Chip Enable; active high

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.03a 10/2006 4/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipelined Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/
activation is accomplished by asserting all three of the Chip Enable inputs (
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Load pin (ADV) held low, in order to load the new address. Device

E1, E2, and E3). Deassertion of any one of the Enable

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.

Flow through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address

BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.

Rev: 1.03a 10/2006 5/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Synchronous Truth Table

Operation Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes

Read Cycle, Begin Burst R External L-H L L H X L H L L L Q

Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10

NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2

Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10

Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3

Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10

Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10

Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z

Deselect Cycle D None L-H L L L H L H L X L High-Z

Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1

Sleep Mode None X X X X X X X X X H High-Z

Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese­lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

1

Rev: 1.03a 10/2006 6/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Pipelined and Flow Through Read-Write Control State Diagram

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.03a 10/2006 7/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Data I/O State Diagram

GS842Z18/36AB-180/166/150/100

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

R

D

Intermediate

Transition

Intermediate State (N+1)

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

D

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒƒƒ

Intermediate

Next State

State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.03a 10/2006 8/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Flow Through Mode Data I/O State Diagram

W

B

High Z
(Data In)

R

D

W

R

High Z

B

D

R

B

Data Out

W

(Q Valid)

D

Key Notes

ƒ

Current State (n)

Clock (CK)

Command

Input Command Code

Transition

Next State (n+1)

n n+1 n+2 n+3

ƒ

Current State Next State

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

ƒƒƒ

Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram

Rev: 1.03a 10/2006 9/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (
sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables
below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Single/Dual Cycle Deselect Control SCD

FLXDrive Output Impedance Control ZQ

9th Bit Enable PE

Note:

There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L Dual Cycle Deselect

H or NC Single Cycle Deselect

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

L or NC Activate DQPx I/Os (x18/x3672 mode)

H Deactivate DQPx I/Os (x16/x3272 mode)

LBO). When this pin is low, a linear burst

Standby, IDD = I

SB

Rev: 1.03a 10/2006 10/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Burst Counter Sequences

GS842Z18/36AB-180/166/150/100

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

8

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

CK

ZZ

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as V

on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.

tKLtKL

DD

tZZR

or V

on pipelined parts and VSS

DDQ

tZZHtZZS

Rev: 1.03a 10/2006 11/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

–0.5 to 4.6 V

–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V

V

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o

o

C

C

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

V

DD3

V

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

Rev: 1.03a 10/2006 12/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

Range Logic Levels

DDQ3

GS842Z18/36AB-180/166/150/100

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

IH

IL

IHQ

ILQ

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

VDD + 0.3

V

+ 0.3

DDQ

V 1

V 1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

V

(max) is voltage on V

IHQ

Range Logic Levels

DDQ2

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

IH

IL

IHQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

VDD + 0.3

0.3*V

V

+ 0.3

DDQ

0.3*V

DD

DD

V 1

V 1

V 1,3

V 1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

Rev: 1.03a 10/2006 13/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0 25 70 °C 2

–40 25 85 °C 2

GS842Z18/36AB-180/166/150/100

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

V

+ 2.0 V

DD

V

SS

50%

50% tKC

50%

– 2.0 V

SS

50% tKC

Capacitance

o

(TA = 25 = 2.5 V)

C, f = 1 MHZ, V

DD

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note:

These parameters are sample tested.

C

IN

C

I/O

AC Test Conditions

Parameter Conditions

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

VDD – 0.2 V

VDD/2

V

/2

DDQ

V

V

IN

OUT

= 0 V

= 0 V

V

DD

V

IL

4 5 pF

6 7 pF

Output Load 1

DQ

50Ω

V

DDQ/2

* Distributed Test Jig Capacitance

30pF

*

Rev: 1.03a 10/2006 14/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

FT, SCD, ZQ Input Current

Output Leakage Current

Output High Voltage

Output High Voltage

Output Low Voltage

GS842Z18/36AB-180/166/150/100

I

IL

I

IN1

I

IN2

I

OL

V

OH2

V

OH3

V

OL

Output Disable, V

I

= –8 mA, V

OH

I

= –8 mA, V

OH

V

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V

V
0 V ≤ V

IN

DD ≥ VIN ≥ VIL

IN

OUT

DDQ

DDQ

I

= 8 mA

OL

DD

≤ V

IH

≤ V

IL

= 0 to V

= 2.375 V

= 3.135 V

DD

–1 uA 1 uA

–1 uA
–1 uA

–100 uA

–1 uA

1 uA

100 uA

1 uA
1 uA

–1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

Rev: 1.03a 10/2006 15/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Operating Currents

Parameter Test Conditions Symbol

Operating

Current

Standby

Current

Deselect

Current

Device Selected;

All other inputs

≥V or ≤ V

IH IL

Output open

ZZ ≥ V –

DD

0.2 V

Device Deselected;

All other inputs

≥ V or ≤ V

IH IL

Pipeline

Flow-Thru

Pipeline

Flow-Thru

Pipeline

Flow-Thru

GS842Z18/36AB-180/166/150/100

- - - -

0 to

70°C

I

DD

I

DD

I

SB

I

SB

I

DD

I

DD

335 345 310 320 280 290 190 200 mA

210 220 190 200 165 175 135 145 mA

–40 to

85°C

0 to

70°C

–40 to

85°C

0 to

70°C

–40 to

85°C

0 to

70°C

–40 to

85°C

20 30 20 30 20 30 20 30 mA

20 30 20 30 20 30 20 30 mA

55 65 50 60 50 60 40 50 mA

40 50 40 50 35 45 35 45 mA

Unit

Rev: 1.03a 10/2006 16/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

GS842Z18/36AB-180/166/150/100

Parameter Symbol

- - -150 -100
Unit

Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 9.1 — 10.0 — 12.0 — 15.0 — ns

Flow

Through

Clock to Output Valid tKQ — 8.0 — 8.5 — 10.0 — 12.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in High-Z

tHZ

1

1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns

G to Output Valid tOE — 3.2 — 3.5 — 3.8 — 5 ns

G to output in Low-Z

G to output in High-Z

tOLZ

tOHZ

1

1

0 — 0 — 0 — 0 — ns

— 3.2 — 3.5 — 3.8 — 5 ns

Setup time tS 1.5 — 1.5 — 1.5 — 2.0 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

ZZ hold time

tZZS

tZZH

2

2

5 — 5 — 5 — 5 — ns

1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Rev: 1.03a 10/2006 17/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Timing

Write A Read B Suspend Read C Write D writeno-op Read E Deselect

CK

tH

tS

A

CKE

E*

ADV

W

Bn

DQ

AB CD E

tH

tS

tH

tS

tH

tS

tH

tS

tH

tS

tKHtKH

tKLtKL

tS

D(A) D(D) Q(E)Q(B) Q(C)

tKCtKC

GS842Z18/36AB-180/166/150/100

tH

tS

tLZtH

tHZ

tKQXtKQ

Rev: 1.03a 10/2006 18/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

CK

GS842Z18/36AB-180/166/150/100

Flow Through Mode Timing

Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G

tKLtKL

tKHtKH

tKCtKC

CKE

ADV

Bn

A0–An

DQ

tS

tS

E

tS

tS

W

tS

tS

tH

tH

tH

tH

tH

tH

AB C DEFG

tLZtHZ

tKQ

tKQX

tH

tS

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)

tLZ

tOLZ

tOE

tKQXtKQ

tOHZ

G

*Note: E

= High(False) if E1 = 1 or E2 = 0 or E3 = 1

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or VSS. TDO should be left unconnected.

DD

Rev: 1.03a 10/2006 19/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

. The JTAG output

DD

GS842Z18/36AB-180/166/150/100

JTAG Port Registers
JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Te st C l ock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

Rev: 1.03a 10/2006 20/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TDI

·· ······

·

·

108

JTAG TAP Block Diagram

Boundary Scan Register

0

Bypass Register

012

Instruction Register

ID Code Register

31 30 29 12

····

0

GS842Z18/36AB-180/166/150/100

·

1

0

TDO

Control Signals

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.03a 10/2006 21/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Tap Controller Instruction Set

ID Register Contents

GS842Z18/36AB-180/166/150/100

Die

Revision

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1

x36 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1

x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Rev: 1.03a 10/2006 22/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Test Logic Reset

1

GS842Z18/36AB-180/166/150/100

JTAG Tap Controller State Diagram

0

Run Test Idle

0

111

Select DR

1

Capture DR

Shift DR

1

Exit1 DR

Pause DR

Exit2 DR

Update DR

1

Select IR

0

1

0

0

Capture IR

0

Shift IR

1

0

0

1

1

Exit1 IR

0

Pause IR

1

1

0

0 0

1

Exit2 IR

1

Update IR

0

10

0

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili
tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.

-

Rev: 1.03a 10/2006 23/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc­tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso­ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ
ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high­Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

-

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

100

TDO.
Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

1

1

1

Rev: 1.03a 10/2006 24/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < V

2. V

3. 0 V ≤ V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

7. I

8. I

9. I

ILJ

OHJ

OLJ

OHJC

OLJC

≤ V

IN

IN

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V
≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

V

V

V

V

I

I

I

V

V

V

V

IHJ3

ILJ3

IHJ2

ILJ2

INHJ

INLJ

OLJ

OHJ

OLJ

OHJC

OLJC

V

DDQ

JTAG Port AC Test Conditions

GS842Z18/36AB-180/166/150/100

V

2.0

–0.3 0.8 V 1

0.6 * V

DD2

–0.3

–300 1 uA 2

–1 100 uA 3

–1 1 uA 4

1.7 — V 5, 6

— 0.4 V 5, 7

– 100 mV

— 100 mV V 5, 9

DD3

V

DD2

0.3 * V

+0.3

+0.3

DD2

V 1

V 1

V 1

— V 5, 8

Parameter Conditions

V

Input high level

– 0.2 V

DD

DQ

JTAG Port AC Test Load

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

V

V

DDQ

DDQ

50Ω

/2

/2

V

/2

* Distributed Test Jig Capacitance

DDQ

30pF

*

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

Rev: 1.03a 10/2006 25/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

TCK

tTH

tTS

TDI

tTH

tTS

TMS

tTKQ

TDO

tTH

tTS

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

GS842Z18/36AB-180/166/150/100

tTKLtTKLtTKHtTKHtTKCtTKC

Rev: 1.03a 10/2006 26/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Output Driver Characteristics

GS842Z18/36AB-180/166/150/100

TBD

Rev: 1.03a 10/2006 27/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Package Dimensions—119-Bump FPBGA (Package B, Variation 1)

Pin #1 Corner

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

1 2 3 4 5 6 7

0.70 REF

Ø0.10
Ø0.30

Ø1.00(3x) REF

19.50

S

S

22±0.20

22±0.20

B

BOTTOM VIEW

C

S

S

C A B

1.27

20.32

A1

Ø0.60~0.90 (119x)

7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

1.27

C

C

0.15

0.15

0.90±0.10

C

0.56±0.05

30 TYP.

12.00

SEATING PLANE

7.62

A

0.20(4x)

C

0.15

2.06.±0.13

0.50~0.70

14±0.20

BPR 1999.05.18

Rev: 1.03a 10/2006 28/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Ordering Information—GSI NBT Synchronous SRAMs

2

Org

256K x 18 GS842Z18AB-180 NBT Pipeline/Flow Through BGA (var. 1) 180/8 C MP

256K x 18 GS842Z18AB-166 NBT Pipeline/Flow Through BGA (var. 1) 166/8.5 C MP

256K x 18 GS842Z18AB-150 NBT Pipeline/Flow Through BGA (var. 1) 150/10 C MP

256K x 18 GS842Z18AB-100 NBT Pipeline/Flow Through BGA (var. 1) 100/12 C MP

128K x 36 GS842Z36AB-180 NBT Pipeline/Flow Through BGA (var. 1) 180/8 C MP

128K x 36 GS842Z36AB-166 NBT Pipeline/Flow Through BGA (var. 1) 166/8.5 C MP

128K x 36 GS842Z36AB-150 NBT Pipeline/Flow Through BGA (var. 1) 150/10 C MP

128K x 36 GS842Z36AB-100 NBT Pipeline/Flow Through BGA (var. 1) 100/12 C MP

256K x 18 GS842Z18AB-180I NBT Pipeline/Flow Through BGA (var. 1) 180/8 I MP

256K x 18 GS842Z18AB-166I NBT Pipeline/Flow Through BGA (var. 1) 166/8.5 I MP

256K x 18 GS842Z18AB-150I NBT Pipeline/Flow Through BGA (var. 1) 150/10 I MP

256K x 18 GS842Z18AB-100I NBT Pipeline/Flow Through BGA (var. 1) 100/12 I MP

128K x 36 GS842Z36AB-180I NBT Pipeline/Flow Through BGA (var. 1) 180/8 I MP

128K x 36 GS842Z36AB-166I NBT Pipeline/Flow Through BGA (var. 1) 166/8.5 I MP

128K x 36 GS842Z36AB-150I NBT Pipeline/Flow Through BGA (var. 1) 150/10 I MP

128K x 36 GS842Z36AB-100I NBT Pipeline/Flow Through BGA (var. 1) 100/12 I MP

256K x 18 GS842Z18AGB-180 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 180/8 C MP

256K x 18 GS842Z18AGB-166 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 166/8.5 C MP

256K x 18 GS842Z18AGB-150 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 150/10 C MP

256K x 18 GS842Z18AGB-100 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 100/12 C MP

128K x 36 GS842Z36AGB-180 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 180/8 C MP

128K x 36 GS842Z36AGB-166 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 166/8.5 C MP

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS842Z36AB-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. MP = Mass Production.

5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

1

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

3

T

Status

A

Rev: 1.03a 10/2006 29/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS842Z18/36AB-180/166/150/100

Ordering Information—GSI NBT Synchronous SRAMs

2

Org

128K x 36 GS842Z36AGB-150 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 150/10 C MP

128K x 36 GS842Z36AGB-100 NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 100/12 C MP

256K x 18 GS842Z18AGB-180I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 180/8 I MP

256K x 18 GS842Z18AGB-166I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 166/8.5 I MP

256K x 18 GS842Z18AGB-150I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 150/10 I MP

256K x 18 GS842Z18AGB-100I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 100/12 I MP

128K x 36 GS842Z36AGB-180I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 180/8 I MP

128K x 36 GS842Z36AGB-166I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 166/8.5 I MP

128K x 36 GS842Z36AGB-150I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 150/10 I MP

128K x 36 GS842Z36AGB-100I NBT Pipeline/Flow Through RoHS-compliant BGA (var. 1) 100/12 I MP

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS842Z36AB-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

4. MP = Mass Production.

5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

1

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

3

T

Status

A

Rev: 1.03a 10/2006 30/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

4Mb Synchronous NBT Datasheet Revision History

GS842Z18/36AB-180/166/150/100

DS/DateRev. Code: Old;

New

842Z18A_r1

842Z18A_r1;

842Z18A_r1_01

842Z18A_r1_01;

842Z18A_r1_02

842Z18A_r1_02;

842Z18A_r1_03

Types of Changes
Format or Content

Content

Content

Format/Content

Page /Revisions/Reason

• Creation of new datasheet

• Updated power numbers in table on page 1 and Operating
Currents table

• Updated pinout for x18

• Updated Pin Description table

• Removed ByteSafe references

• Changed DP and QE to NC

• Delete PE from entire document (changed to NC)

• Removed 200 MHz speed bin

• Removed pin locations from pin description table

• Updated format

• Updated timing diagrams

• Added variation information to package mechanical

• (Rev1.03a: added RoHS-compliant information)

Rev: 1.03a 10/2006 31/31 © 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.