Datasheet GS840Z18AGT-180, GS840Z18AGT-166, GS840Z18AGT-150, GS840Z18AGT-100, GS840Z36AGT-180 Datasheet (GSI TECHNOLOGY)

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Page 1

GS840Z18/36AT-180/166/150/100

100-Pin TQFP

4Mb Pipelined and Flow Through

Commercial Temp Industrial Temp

Synchronous NBT SRAMs

Features

• 256K x 18 and 128K x 36 configurations

• User configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization

• Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs

• Pin-compatible with 2M, 8M and 16M devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO

pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

Functional Description

The GS840Z18/36AT is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

180 MHz–100 MHz

3.3 V V

2.5 V and 3.3 V V

Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS840Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS840Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 100-pin TQFP package.

) must be tied to a power

DDQ

Parameter Synopsis

–180 –166 –150 –100

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tCycle

t IDD

tCycle

5.5 ns

3.2 ns

335 mA

8 ns

9.1 ns

210 mA

6.0 ns

3.5 ns

310 mA

8.5 ns 10 ns

190 mA

6.6 ns

3.8 ns

280 mA

10 ns 12 ns

165 mA

10 ns

4.5 ns

190 mA

12 ns 15 ns

135 mA

Page 2

GS840Z18AT Pinout (Package T)

GS840Z18/36AT-180/166/150/100

NC NC NC

DDQ

NC DQB DQB V

DDQ

DQB DQB

DDQ

DQB DQB

DQPB

DDQ

256K x 18

Top View

10099989796959493929190898887868584838281

2 3

6 7

11 12

15 16

19 20

24 25

28 29

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

CKE

ADV

80 79

78 77

75 74

72 71

70 69

67 66

64 63

62 61

59 58

56 55

54 53

A NC NC V

DDQ

NC DQPA DQA DQA V

DDQ

DQA DQA V

NC V

ZZ DQ

DQA V

DDQ

DQA DQA NC NC V

DDQ

NC NC NC

LBO

A1A0

A A A A A

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 3

GS840Z36AT Pinout (Package T)

GS840Z18/36AT-180/166/150/100

DQPC

DQC DQC

DDQ

DQC DQC DQC DQC V

DDQ

DQC DQC

DQD DQD

DDQ

DQD DQD DQD DQD

DDQ

DQD DQD

DQPD

10099989796959493929190898887868584838281

2 3

6 7

11 12

15 16

19 20

24 25

28 29

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

128K x 36

Top View

CKE

ADV

80 79

78 77

75 74

72 71

70 69

67 66

64 63

62 61

59 58

56 55

54 53

DQPB DQB DQB V

DDQ

DQB DQB DQB DQB V

DDQ

DQB DQB V

NC V

ZZ DQ

DQA V

DDQ

DQA DQA DQA DQA V

DDQ

DQA DQA DQA

LBO

A1A0

A A A A A

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 4

100-Pin TQFP Pin Descriptions

Symbol Type Description

A0, A1 In Burst Address Inputs; preload the burst counter

A In Address Inputs

CK In Clock Input Signal

A In Byte Write signal for data inputs DQA1-DQA9; active low

B In Byte Write signal for data inputs DQB1-DQB9; active low

C In Byte Write signal for data inputs DQC1-DQC9; active low

D In Byte Write signal for data inputs DQD1-DQD9; active low

1 In Chip Enable; active low

2 In Chip Enable; active high; for self decoded depth expansion

3 In Chip Enable; active low, for self decoded depth expansion

ADV In Advance / Load

CKE

A I/O Byte A Data Input and Output pins

B I/O Byte B Data Input and Output pins

C I/O Byte C Data Input and Output pins

D I/O Byte D Data Input and Output pins

ZZ In Power down control; active high

LBO

DDQ

NC — No Connect

In Write Enable; active low

In Output Enable; active low

—Burst address counter control pin

In Clock Input Buffer Enable; active low

In Pipeline/Flow Through Mode Control; active low

In Linear Burst Order; active low

In 3.3 V power supply

In Ground

In 3.3 V output power supply for noise reduction

GS840Z18/36AT-180/166/150/100

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 5

GS840Z18/36AT-180/166/150/100

GS840Z18/36A NBT SRAM Functional Block Diagram

DQa–DQn

SA1’

SA1

SA0’

Burst

SA0

Counter

D Q

Sense Amps

Array

Memory

Write Drivers

Write Da ta

Write Data

Write Address

D Q

Write Address

LBO

ADV

Match

Read, Write and

Control Logic

Data Coherency

CKE

A0–

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 6

GS840Z18/36AT-180/166/150/100

Functional Details

Clocking

Deassertion of the Clock Enable (CKE suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipelined Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load activation is accomplished by asserting all three of the Chip Enable inputs (E inputs will deactivate the device.

) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

pin (ADV) held low, in order to load the new address. Device

1, E2, and E3). Deassertion of any one of the Enable

Function W

BA BB BC BD

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE chip enables (E1

, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address

is asserted low, all three

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B

A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle

with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.

Flow through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 7

Synchronous Truth Table

GS840Z18/36AT-180/166/150/100

Operation Type Address CK CKE

Read Cycle, Begin Burst R External L-H L L H X L H L L L Q

Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10

NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2

Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10

Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3

Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10

Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10

Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z

Deselect Cycle D None L-H L L L H L H L X L High-Z

Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1

Sleep Mode None X X X X X X X X X H High-Z

Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4

ADV W Bx E1 E2 E3 G ZZ DQ Notes

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G

can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx

6. All inputs, except G

7. Wait states can be inserted by setting CKE

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

and ZZ must meet setup and hold times of rising clock edge.

high.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 8

GS840Z18/36AT-180/166/150/100

Pipelined and Flow Through Read-Write Control State Diagram

Deselect

New Read New Write

Burst Read Burst Write

Key Notes

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table.

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 9

Pipeline Mode Data I/O State Diagram

GS840Z18/36AT-180/166/150/100

Intermediate Intermediate

Key

Transition

Current State (n) Next State (n+2)

High Z (Data In)

Input Command Code

Intermediate

Transition

Intermediate State (N+1)

Intermediate

High Z

Intermediate

Data Out

(Q Valid)

Intermediate

Notes

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command codes as indicated in the Truth Tables.

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒƒƒ

Intermediate

Next State

State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 10

GS840Z18/36AT-180/166/150/100

Flow Through Mode Data I/O State Diagram

High Z (Data In)

Key Notes

Current State (n)

Input Command Code

Transition

Next State (n+1)

High Z

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

Data Out

(Q Valid)

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒƒƒ

Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 11

GS840Z18/36AT-180/166/150/100

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables below for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Power Down Control ZZ

Note:

There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

L Linear Burst

H Interleaved Burst

L or NC Active

). When this pin is low, a linear burst

Standby, I

= I

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 12

GS840Z18/36AT-180/166/150/100

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT found on Pin 14. Not all vendors offer this option, however, most mark Pin 14 as V

through parts. GSI NBT SRAMs are fully compatible with these sockets.

tKLtKL

tZZHtZZS

tZZR

signal

or V

on pipelined parts and VSS on flow

DDQ

Pin 66, a No Connect (NC) on GSI’s GS840Z18/36A NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36 NBT SRAM, is often marked as a power pin on other vendor’s NBT-compatible SRAMs. Specifically, it is marked V

pipelined parts and V

on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature

or V

DDQ

may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT SRAMs (GS881Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 13

GS840Z18/36AT-180/166/150/100

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

DDQ

I/O

OUT

STG

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DD3

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 14

Range Logic Levels

DDQ3

GS840Z18/36AT-180/166/150/100

Parameter Symbol Min. Typ. Max. Unit Notes

DDQ

+ 0.3

V1,3

VDD Input High Voltage V

Input Low Voltage V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

DDQ

IHQ

ILQ

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

Notes:

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Range Logic Levels

DDQ2

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

DDQ

IHQ

ILQ

0.6*V

–0.3 —

0.6*V

–0.3 —

—

Notes:

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0.3*V

DDQ

0.3*V

+ 0.3

V1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

2. Input Under/overshoot voltage must be –2 V > Vi < V

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

02570°C2

–40 25 85 °C2

Page 15

GS840Z18/36AT-180/166/150/100

Undershoot Measurement and Timing Overshoot Measurement and Timing

+ 2.0 V

50%

50% tKC

50%

– 2.0 V

50% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note:

These parameters are sample tested.

I/O

AC Test Conditions

Parameter Conditions

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

– 0.2 V

VDD/2

DDQ

OUT

= 0 V

45pF

67pF

Output Load 1

50Ω

DDQ/2

* Distributed Test Jig Capacitance

30pF

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 16

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

Input Current

Output Leakage Current

Output High Voltage

Output Low Voltage

IN1

IN2

OH2

OH3

= 0 to V

DD ≥ VIN ≥ VIH

0 V ≤ V

DD ≥ VIN ≥ VIL

0 V ≤ V

Output Disable, V

= –8 mA, V

= 8 mA

GS840Z18/36AT-180/166/150/100

–1 uA 1 uA

–1 uA –1 uA

–100 uA

–1 uA

–1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

OUT

DDQ

≤ V

= 0 to V

= 2.375 V

= 3.135 V

1 uA

100 uA

1 uA 1 uA

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 17

Operating Currents

Parameter Test Conditions Symbol

Operating

Current

Standby

Current

Deselect

Current

Device Selected;

All other inputs

≥V

IH or ≤ VIL

Output open

ZZ ≥ VDD –

0.2 V

Device Deselected;

All other inputs

≥ V

IH or ≤ VIL

Pipeline

Flow-Thru

Pipeline

Flow-Thru

Pipeline

Flow-Thru

IDD

GS840Z18/36AT-180/166/150/100

-180 -166 -150 -100

0 to

70°C

335 345 310 320 280 290 190 200 mA

210 220 190 200 165 175 135 145 mA

–40 to

85°C

20 30 20 30 20 30 20 30 mA

55 65 50 60 50 60 40 50 mA

40 50 40 50 35 45 35 45 mA

0 to

70°C

–40 to

85°C

0 to

70°C

–40 to

85°C

0 to

70°C

–40 to

85°C

Unit

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 18

AC Electrical Characteristics

GS840Z18/36AT-180/166/150/100

Parameter Symbol

-180 -166 -150 -100 Unit

Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 5.5 — 6.0 — 6.7 — 10 — ns

Clock to Output Valid tKQ — 3.2 — 3.5 — 3.8 — 4.5 ns

Pipeline

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1.5 — 1.5 — 1.5 — 1.5 — ns

Clock Cycle Time tKC 9.1 — 10.0 — 12.0 — 15.0 — ns

Flow

Through

Clock to Output Valid tKQ — 8.0 — 8.5 — 10.0 — 12.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in High-Z

to Output Valid tOE — 3.2 — 3.5 — 3.8 — 5 ns

to output in Low-Z

to output in High-Z

tHZ

tOLZ

tOHZ

1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns

0 — 0 — 0—0—ns

— 3.2 — 3.5 — 3.8 — 5 ns

Setup time tS 1.5 — 1.5 — 1.5 — 2.0 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

ZZ hold time

tZZS

tZZH

5 — 5 — 5—5—ns

1 — 1 — 1—1—ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 19

CKE

ADV

GS840Z18/36AT-180/166/150/100

Pipeline Mode Timing

Write A Read B Suspend Read C Write D writeno-op Read E Deselect

tKHtKH

tKLtKL

AB CD E

D(A) D(D) Q(E)Q(B) Q(C)

tKCtKC

tLZtH

tHZ

tKQXtKQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 20

GS840Z18/36AT-180/166/150/100

Flow Through Mode Timing

Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G

tKLtKL

tKHtKH

tKCtKC

CKE

ADV

A0–An

AB C DEFG

tLZtHZ

tKQ

tKQX

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)

tLZ

tOLZ

tOE

tKQXtKQ

tOHZ

*Note: E

= High(False) if E1 = 1 or E2 = 0 or E3 = 1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 21

TQFP Package Drawing (Package T)

GS840Z18/36AT-180/166/150/100

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15

A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 — 0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch — 0.65 —

L Foot Length 0.45 0.60 0.75

L1 Lead Length — 1.00 —

Y Coplanarity 0.10

θ Lead Angle 0° — 7°

Pin 1

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

BPR 1999.05.18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 22

GS840Z18/36AT-180/166/150/100

Ordering Information—GSI NBT Synchronous SRAMs

Org

256K x 18 GS840Z18AT-180 NBT Pipeline/Flow Through TQFP 180/8 C

256K x 18 GS840Z18AT-166 NBT Pipeline/Flow Through TQFP 166/8.5 C

256K x 18 GS840Z18AT-150 NBT Pipeline/Flow Through TQFP 150/10 C

256K x 18 GS840Z18AT-100 NBT Pipeline/Flow Through TQFP 100/12 C

128K x 36 GS840Z36AT-180 NBT Pipeline/Flow Through TQFP 180/8 C

128K x 36 GS840Z36AT-166 NBT Pipeline/Flow Through TQFP 166/8.5 C

128K x 36 GS840Z36AT-150 NBT Pipeline/Flow Through TQFP 150/10 C

128K x 36 GS840Z36AT-100 NBT Pipeline/Flow Through TQFP 100/12 C

256K x 18 GS840Z18AT-180I NBT Pipeline/Flow Through TQFP 180/8 I

256K x 18 GS840Z18AT-166I NBT Pipeline/Flow Through TQFP 166/8.5 I

256K x 18 GS840Z18AT-150I NBT Pipeline/Flow Through TQFP 150/10 I

256K x 18 GS840Z18AT-100I NBT Pipeline/Flow Through TQFP 100/12 I

128K x 36 GS840Z36AT-180I NBT Pipeline/Flow Through TQFP 180/8 I

128K x 36 GS840Z36AT-166I NBT Pipeline/Flow Through TQFP 166/8.5 I

128K x 36 GS840Z36AT-150I NBT Pipeline/Flow Through TQFP 150/10 I

128K x 36 GS840Z36AT-100I NBT Pipeline/Flow Through TQFP 100/12 I

256K x 18 GS840Z18AGT-180 NBT Pipeline/Flow Through Pb-free TQFP 180/8 C

256K x 18 GS840Z18AGT-166 NBT Pipeline/Flow Through Pb-free TQFP 166/8.5 C

256K x 18 GS840Z18AGT-150 NBT Pipeline/Flow Through Pb-free TQFP 150/10 C

256K x 18 GS840Z18AGT-100 NBT Pipeline/Flow Through Pb-free TQFP 100/12 C

128K x 36 GS840Z36AGT-180 NBT Pipeline/Flow Through Pb-free TQFP 180/8 C

128K x 36 GS840Z36AGT-166 NBT Pipeline/Flow Through Pb-free TQFP 166/8.5 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Status

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 23

GS840Z18/36AT-180/166/150/100

Ordering Information—GSI NBT Synchronous SRAMs

Org

128K x 36 GS840Z36AGT-150 NBT Pipeline/Flow Through Pb-free TQFP 150/10 C

128K x 36 GS840Z36AGT-100 NBT Pipeline/Flow Through Pb-free TQFP 100/12 C

256K x 18 GS840Z18AGT-180I NBT Pipeline/Flow Through Pb-free TQFP 180/8 I

256K x 18 GS840Z18AGT-166I NBT Pipeline/Flow Through Pb-free TQFP 166/8.5 I

256K x 18 GS840Z18AGT-150I NBT Pipeline/Flow Through Pb-free TQFP 150/10 I

256K x 18 GS840Z18AGT-100I NBT Pipeline/Flow Through Pb-free TQFP 100/12 I

128K x 36 GS840Z36AGT-180I NBT Pipeline/Flow Through Pb-free TQFP 180/8 I

128K x 36 GS840Z36AGT-166I NBT Pipeline/Flow Through Pb-free TQFP 166/8.5 I

128K x 36 GS840Z36AGT-150I NBT Pipeline/Flow Through Pb-free TQFP 150/10 I

128K x 36 GS840Z36AGT-100I NBT Pipeline/Flow Through Pb-free TQFP 100/12 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8Z36A-100IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some

Part Number

Type Package

Speed

(MHz/ns)

of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Status

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Page 24

4Mb Synchronous NBT Datasheet Revision History

GS840Z18/36AT-180/166/150/100

DS/DateRev. Code: Old;

New

840Z18A_r1

840Z18A_r1;

840Z18A_r1_01

840Z18A_r1_01;

840Z18A_r1_02

840Z18A_r1_02;

840Z18A_r1_03

Types of Changes Format or Content

Content

Format/Content

Page /Revisions/Reason

• Creation of new datasheet

• Updated power numbers in table on page 1 and Operating Currents table

• Removed 200 MHz speed bin from entire document

• Removed pin locations from pin description table

• Updated format

• Updated timing diagrams

• Added Pb-free information for TQFP

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Datasheet GS840Z18AGT-180, GS840Z18AGT-166, GS840Z18AGT-150, GS840Z18AGT-100, GS840Z36AGT-180 Datasheet (GSI TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

GS840Z18AT Pinout (Package T)

GS840Z36AT Pinout (Package T)

100-Pin TQFP Pin Descriptions

GS840Z18/36A NBT SRAM Functional Block Diagram

Functional Details

Clocking

Pipelined Mode Read and Write Operations

Flow through Mode Read and Write Operations

Synchronous Truth Table

Pipelined and Flow Through Read-Write Control State Diagram

Pipeline Mode Data I/O State Diagram

Flow Through Mode Data I/O State Diagram

Burst Cycles

Burst Order

Mode Pin Functions

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

Sleep Mode

Sleep Mode Timing Diagram

Designing for Compatibility

Absolute Maximum Ratings

Power Supply Voltage Ranges

Recommended Operating Temperatures

Undershoot Measurement and Timing Overshoot Measurement and Timing

Capacitance

AC Test Conditions

DC Electrical Characteristics

Operating Currents

AC Electrical Characteristics

Pipeline Mode Timing

Flow Through Mode Timing

TQFP Package Drawing (Package T)

Ordering Information—GSI NBT Synchronous SRAMs

4Mb Synchronous NBT Datasheet Revision History