Datasheet GS84018AGB-166, GS84018AGB-150, GS84018AGB-100, GS84032AGB-190, GS84032AGB-180 Datasheet (GSI TECHNOLOGY)

GS84018/32/36AT/B-190/180/166/150/100

TQFP, BGA

256K x 18, 128K x 32, 128K x 36

Commercial Temp
Industrial Temp

4Mb Sync Burst SRAMs

Features

• FT pin for user-configurable flow through or pipelined
operation

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-bump BGA
packages

• RoHS-compliant 100-lead TQFP and 119-bump BGA
packages available

Functional Description

Applications

The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2­bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (
(

Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either

ADSP, ADSC, ADV), and write control inputs

G)

ADSP or ADSC inputs. In

Parameter Synopsis

190 MHz–100 MHz

3.3 V V

3.3 V and 2.5 V I/O

Burst mode, subsequent burst addresses are generated
internally and are controlled by
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by
the user via the
bump 5R in the BGA). Holding the
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.

SCD Pipelined Reads

The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using byte write enable
(

BW) input combined with one or more individual byte write
signals (
writing all bytes at one time, regardless of the Byte Write
control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V

from the internal circuit.

FT mode pin/bump (pin 14 in the TQFP and

Bx). In addition, Global Write (GW) is available for

) pins are used to de-couple output noise

DDQ

ADV. The burst address

LBO) input. The

FT mode pin/bump low

FT high places the

DD

–190 –180 –166 –150 –100

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Rev: 1.17a 4/2006 1/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tCycle

tCycle

5.3 ns

t

3.0 ns

KQ

I

370 mA

DD

t

7.5 ns

KQ

8.5 ns

I

245 mA

DD

5.5 ns

3.0 ns

335 mA

8 ns
9 ns

210 mA

6.0 ns

3.5 ns

310 mA

8.5 ns
10 ns

190 mA

6.6 ns

3.8 ns

280 mA

10 ns
12 ns

165 mA

10 ns

4.5 ns

190 mA

12 ns
15 ns

135 mA

GS84018/32/36AT/B-190/180/166/150/100

GS84018A 100-Pin TQFP Pinout (Package T)

NC
NC
NC

V

DDQ

V

SS

NC

NC
DQB
DQB
V

SS

V

DDQ

DQB
DQB

FT

V

DD

NC

V

SS

DQB
DQB

V

DDQ

V

SS

DQB
DQB

DQPB

NC

V

SS

V

DDQ

NC

NC

NC

NC

B

B

BA

NC

256K x 18

1

A

E

A

E2

10099989796959493929190898887868584838281

1

2
3

4

5

6
7

8

9

10

11
12

13

14

15
16

17

18

19
20

21

22

23

24
25

26

27

28
29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DD

E3

SS

V

V

Top View

CK

GW

BW

ADSC

ADV

ADSP

80
79

78
77

76

75
74

73

72
71

70
69

68

67
66

65

64
63

62
61

60

59
58

57

56
55

54
53

52

51

A
NC
NC
V

DDQ

V

SS

NC
DQPA
DQA
DQA
V

SS

VDDQ

A

DQ
DQA
V

SS

NC
VDD
ZZ

A

DQ
DQA
VDDQ
V

SS

DQA
DQA
NC
NC
V

SS

VDDQ
NC
NC
NC

G

A

A

SS

LBO

A

A

A

A

A1A0

NC

NC

DD

NC

V

V

NC

A A A A A

A

A

Rev: 1.17a 4/2006 2/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84032A 100-Pin TQFP Pinout (Package T)

V

V

V

V

NC
DQC
DQ

DDQ

V

SS

DQC
DQ
DQC
DQC

V

SS

DDQ

DQC
DQC

FT

V

DD

NC
V

SS

DQD
DQD

DDQ

V

SS

DQD
DQD
DQD
DQD

V

SS

DDQ

DQD
DQD

NC

1

A

E

A

E2

10099989796959493929190898887868584838281

1

2

C

C

3

4

5

6
7

8

9

10

11
12

13

14

15
16

17

18

19
20

21

22

23

24
25

26

27

28
29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

BB

BA

BC

BD

128K x 32

DD

E3

SS

V

V

Top View

CK

GW

BW

ADSC

ADV

ADSP

80
79

78
77

76

75
74

73

72
71

70
69

68

67
66

65

64
63

62
61

60

59
58

57

56
55

54
53

52

51

NC
DQB
DQ
V

DDQ

V

SS

DQB
DQB
DQB
DQB
V

SS

V

DDQ

DQB
DQB
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SS

DQA
DQA
DQA
DQA
V

SS

V

DDQ

DQA
DQA
NC

B

A

G

A

A

SS

LBO

A

A

A

A

A1A0

NC

NC

DD

NC

V

V

NC

A A A A A

A

A

Rev: 1.17a 4/2006 3/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84036A 100-Pin TQFP Pinout (Package T)

DQPC

DQC
DQC

V

DDQ

V

SS

DQC
DQC
DQC
DQC
V

SS

V

DDQ

DQC
DQC

FT

V

DD

NC
V

SS

DQD
DQD

V

DDQ

V

SS

DQD
DQD
DQD
DQD

V

SS

V

DDQ

DQD
DQD

DQPD

1

A

E

A

E2

10099989796959493929190898887868584838281

1

2
3

4

5

6
7

8

9

10

11
12

13

14

15
16

17

18

19
20

21

22

23

24
25

26

27

28
29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

BB

BA

BC

BD

128K x 36

DD

E3

SS

V

V

Top View

CK

GW

BW

ADSC

ADV

ADSP

80
79

78
77

76

75
74

73

72
71

70
69

68

67
66

65

64
63

62
61

60

59
58

57

56
55

54
53

52

51

DQPB
DQB
DQB
V

DDQ

V

SS

DQB
DQB
DQB
DQB
V

SS

V

DDQ

DQB
DQB
V

SS

NC
V

DD

ZZ

A

DQ
DQA
V

DDQ

V

SS

DQA
DQA
DQA
DQA
V

SS

V

DDQ

DQA
DQA
DQPA

G

A

A

SS

LBO

A

A

A

A

A1A0

NC

NC

DD

NC

V

V

NC

A A A A A

A

A

Rev: 1.17a 4/2006 4/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

TQFP Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter preset Inputs

A I Address Inputs

DQA
DQB
DQC
DQD

BW I Byte Write—Writes all enabled bytes; active low

BA, BB I Byte Write Enable for DQA, DQB Data I/’s; active low

BC, BD I Byte Write Enable for DQC, DQD Data I/Os; active low

CK I Clock Input Signal; active high

GW I Global Write Enable—Writes all bytes; active low

E1, E3 I Chip Enable; active low

E2 I Chip Enable; active high

G I Output Enable; active low

ADV I Burst address counter advance enable; active low

ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep Mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

V

DD

V

SS

V

DDQ

NC - No Connect

I/O Data Input and Output pins

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.17a 4/2006 5/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84018A Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 AADSCAE3 NC

NC A A V

DQB NC V

NC DQB V

V

DDQ

NC DQB BB ADV NC NC DQA

DQB NC V

V

DDQ

NC DQB V

DQB NC NC NC BA DQA NC

A A ADSP AAV

AANC

DQPA NC

SS

SS

SS

SS

NC V

SS

NC DQA

DQA V

DQA NC

DD

NC DQA

NC V

V

DD

SS

SS

SS

SS

NC V

SS

DD

NC V

E1 V

G V

GW V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQB NC V

NC DQPB V

NC A LBO V

NC A A NC A A ZZ

V

DDQ

DQB V

SS

SS

SS

BW V

A1 V

A0 V

DD

SS

SS

SS

NC V

DQA NC

NC DQA

FT ANC

NC NC NC NC NC V

DDQ

DDQ

Rev: 1.17a 4/2006 6/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84032A Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 AADSCAE3 NC

NC A A V

DQC NC V

DQC DQC V

V

DDQ

DQC DQC BC ADV BB DQB DQB

DQC DQC V

V

DDQ

DQD DQD V

DQD DQD BD NC BA DQA DQA

A A ADSP AAV

AANC

SS

SS

SS

SS

NC V

SS

NC DQB

DQB DQB

DQB V

DQB DQB

DD

DQA DQA

DQC V

V

DD

SS

SS

SS

SS

NC V

SS

DD

NC V

E1 V

G V

GW V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQD DQD V

DQD NC V

NC A LBO V

NC NC A A A NC ZZ

V

DDQ

DQD V

NC NC NC NC NC V

SS

SS

SS

BW V

A1 V

A0 V

DD

SS

SS

SS

FT ANC

DQA V

DQA DQA

NC DQA

DDQ

DDQ

Rev: 1.17a 4/2006 7/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84036A Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

B

C

D

E

F

G

H

J

K

L

V

DDQ

NC E2 AADSCAE3 NC

NC A A V

DQC DQPC V

DQC DQC V

V

DDQ

DQC2 DQC BC ADV BB DQB DQB2

DQC DQC V

V

DDQ

DQD DQD V

DQD DQD BD NC BA DQA DQA

A A ADSP AAV

AANC

DQPB DQB

SS

SS

SS

SS

NC V

SS

DQB DQB

DQB V

DQB DQB

DD

DQA DQA

DQC V

V

DD

SS

SS

SS

SS

NC V

SS

DD

NC V

E1 V

G V

GW V

DD

CK V

V

DDQ

DDQ

DDQ

M

N

P

R

T

U

V

DDQ

DQD DQD V

DQD DQPD V

NC A LBO V

NC NC A A A NC ZZ

V

DDQ

DQD V

SS

SS

SS

BW V

A1 V

A0 V

DD

SS

SS

SS

DQA V

DQA DQA

DQPA DQA

FT ANC

NC NC NC NC NC V

DDQ

DDQ

Rev: 1.17a 4/2006 8/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs

DQA
DQB
DQC
DQD

BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low

GW I Global Write Enable—Writes all bytes; active low

E1, E3 I Chip Enable; active low

E2 I Chip Enable; active high

G I Output Enable; active low

ADV I Burst address counter advance enable; active low

ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep Mode control; active high

FT I Flow Through or Pipeline mode; active low

LBO I Linear Burst Order mode; active low

VDD I Core power supply

VSS I I/O and Core Ground

VDDQ I Output driver power supply

NC - No Connect

I/O Data Input and Output pins

Rev: 1.17a 4/2006 9/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

GS84018/32/36A Block Diagram

A0–An

LBO

ADV

CK

ADSC
ADSP

GW
BW
BA

BB

BC

BD

Register

DQ

A0

A1

D0

D1

Counter

Load

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Q0

Q1

A0

A1

A

Memory

Array

QD

36

4

DQ

Register

36

Register

DQ

E1
E3
E2

FT

G

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

Register

DQ

Register

DQ

Register

DQ

1

DQx1–DQx9

Rev: 1.17a 4/2006 10/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Mode Pin Functions

GS84018/32/36AT/B-190/180/166/150/100

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note:

There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Note:

The burst counter wraps to initial state on the 5th clock.

Pin

Name

State Function

L Linear Burst

H or NC Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

Standby, IDD = I

Interleaved Burst Sequence

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Note:

The burst counter wraps to initial state on the 5th clock.

SB

A[1:0] A[1:0] A[1:0] A[1:0]

Rev: 1.17a 4/2006 11/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1

Write byte A H L L H H H 2, 3

Write byte B H L H L H H 2, 3

Write byte C H L H H L H 2, 3, 4

Write byte D H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4

Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Rev: 1.17a 4/2006 12/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Synchronous Truth Table

GS84018/32/36AT/B-190/180/166/150/100

Operation

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q

Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D

Read Cycle, Suspend Burst Current X X H H H F Q

Read Cycle, Suspend Burst Current H X X H H F Q

Write Cycle, Suspend Burst Current X X H H H T D

Write Cycle, Suspend Burst Current H X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low.

2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).

Address

Used

Diagram

5

Key

E1

E

2

ADSP ADSC ADV

W

3

DQ

4

State

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.17a 4/2006 13/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Simplified State Diagram

X

Deselect

WR

Simple Synchronous OperationSimple Burst Synchronous Operation

W

X

First Write

WR

Burst Write

CW CR

R

CR

R

CR

R

First Read

Burst Read

X

CRCW

XX

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G

2. The upper portion of the diagram assumes active use of only the Enable (E
and that ADSP

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC
ADSP

is tied high and ADV is tied low.

Rev: 1.17a 4/2006 14/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

is tied high and ADSC is tied low.

1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs

is tied Low.

control inputs and assumes

GS84018/32/36AT/B-190/180/166/150/100

Simplified State Diagram with G

X

Deselect

WR

W

X

First Write

W

X

Burst Write

CW CR

R

CR

R

CR

W

CW

W

CW

R

First Read

R

Burst Read

X

CRCW

X

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G

2. Use of “Dummy Reads” (Read Cycles with G
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G
Data Input Set Up Time.

Rev: 1.17a 4/2006 15/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

High) may be used to make the transition from Read cycles to Write cycles without passing

has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

.

GS84018/32/36AT/B-190/180/166/150/100

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

–0.5 to 4.6 V

–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V

V

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o

o

C

C

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

V

DD3

V

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

Rev: 1.17a 4/2006 16/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

Range Logic Levels

DDQ3

GS84018/32/36AT/B-190/180/166/150/100

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

IH

IL

IHQ

ILQ

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

VDD + 0.3

V

+ 0.3

DDQ

V 1

V 1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

V

(max) is voltage on V

IHQ

Range Logic Levels

DDQ2

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

IH

IL

IHQ

ILQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

VDD + 0.3

0.3*V

DD

V

+ 0.3

DDQ

0.3*V

DD

V 1

V 1

V 1,3

V 1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. During testing, Case Temperature = Ambient Temperature (TA).

Rev: 1.17a 4/2006 17/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

T

A

T

A

0 25 70 °C 2

–40 25 85 °C 2

GS84018/32/36AT/B-190/180/166/150/100

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

V

+ 2.0 V

DD

V

SS

50%

50% tKC

50%

– 2.0 V

SS

50% tKC

Capacitance

o

(TA = 25 = 2.5 V)

C, f = 1 MHZ, V

DD

Parameter Symbol Test conditions Ty p. Max. Unit

Input Capacitance

Input/Output Capacitance

Note:

These parameters are sample tested.

C

IN

C

I/O

AC Test Conditions

Parameter Conditions

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

VDD – 0.2 V

VDD/2

V

/2

DDQ

V

V

IN

OUT

= 0 V

= 0 V

V

DD

V

IL

4 5 pF

6 7 pF

Output Load 1

DQ

50Ω

V

DDQ/2

* Distributed Test Jig Capacitance

30pF

*

Rev: 1.17a 4/2006 18/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ Input Current

FT Input Current

Output Leakage Current

Output High Voltage

Output High Voltage

Output Low Voltage

Operating Currents

Parameter Test Conditions Symbol

IDD

Pipeline

IDD

Flow

Through

Pipeline

Flow

Through

IDD

Pipeline

IDD

Flow

Through

Operating

Current

Standby

Current

Deselect

Current

Device Selected;

All other

inputs
≥VIH or ≤ VIL
Output open

ZZ ≥ VDD –

0.2 V

Device

Deselected;

All other

inputs

≥ VIH or ≤ VIL

ISB

ISB

GS84018/32/36AT/B-190/180/166/150/100

I

IL

I

IN1

I

IN2

V

V

I

V

OL

OH2

OH3

OL

Output Disable, V

-190 -180 -166 -150 -100

0

–40

to

70°C

370 380 335 345 310 320 280 290 190 200 mA

245 255 210 220 190 200 165 175 135 145 mA

20 30 20 30 20 30 20 30 20 30 mA

20 30 20 30 20 30 20 30 20 30 mA

60 70 55 65 50 60 50 60 40 50 mA

45 55 40 50 40 50 35 45 35 45 mA

to

85°C

0

to

70°C

I

= –8 mA, V

OH

I

= –8 mA, V

OH

–40

to

85°C

V

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V

V

DD ≥ VIN ≥ VIL

0 V ≤ V

I

OL

≤ V

IN

≤ V

IN

OUT

DDQ

DDQ

= 8 mA

0

to

70°C

DD

IH

IL

= 0 to V

= 2.375 V

= 3.135 V

–40

to

85°C

DD

0

to

70°C

–1 uA 1 uA

–1 uA
–1 uA

–100 uA

–1 uA

–1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

–40

to

85°C

70°C

1 uA

100 uA

1 uA
1 uA

0

–40

to

to

85°C

Unit

Rev: 1.17a 4/2006 19/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

GS84018/32/36AT/B-190/180/166/150/100

Parameter Symbol

-190 -180 -166 -150 -100
Unit

Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 5.3 — 5.5 — 6.0 — 6.7 — 10 — ns

Clock to Output Valid tKQ — 3.0 — 3.0 — 3.5 — 3.8 — 4.5 ns

Pipeline

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 —

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

1.5

— 1.5 — ns

Clock Cycle Time tKC 8.5 — 9.0 — 10.0 — 12.0 — 15.0 — ns

Flow

Through

Clock to Output Valid tKQ — 7.5 — 8.0 — 8.5 — 10.0 — 12.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.3 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in High-Z

tHZ

1

1.5 3.0 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns

G to Output Valid tOE — 3.0 — 3.2 — 3.5 — 3.8 — 5 ns

G to output in Low-Z

G to output in High-Z

tOLZ

tOHZ

1

0 — 0 — 0 — 0 — 0 — ns

1

— 3.0 — 3.2 — 3.5 — 3.8 — 5 ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 2.0 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

ZZ hold time

tZZS

tZZH

2

5 — 5 — 5 — 5 — 5 — ns

2

1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Rev: 1.17a 4/2006 20/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

CK

ADSP

ADSC

ADV

A0–An

GW

GS84018/32/36AT/B-190/180/166/150/100

Pipeline Mode Timing

Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect

Burst ReadBurst ReadSingle Write

tKH

tKH

Single WriteSingle Read

tKLtKL

tKCtKC

ADSC initiated read

Single Read

tS

tH

tHtS

tS

tH

ABC

tS

BW

Ba–Bd

E1

E2

E3

DQa–DQd

tHtS

tH

tS

tS

tS

tH

tS

tH

G

tH

E2 and E3 only sampled with ADSP and ADSC

tS

tOHZtOE

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)

E1 masks ADSP

tLZtH

Deselected with E1

tKQXtKQ

tHZ

Rev: 1.17a 4/2006 21/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Flow Through Mode Timing

Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect

tKLtKL

tKHtKH

CK

tKCtKC

ADSP

ADSC

ADV

A0–An

GW

BW

Ba–Bd

E1

Fixed High

tS

tH

tS

tH

tS

tH

ABC

tS

tH

tS

tH

tS

tH

ADSC initiated read

tS

tH

tS

tH

Deselected with E1

tS

tH

E2

tS

tH

E3

G

DQa–DQd

E2 and E3 only sampled with ADSC

tH

tS

tOHZtOE

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)

tKQ

tLZ

tHZ

tKQX

Rev: 1.17a 4/2006 22/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

CK

Setup

Hold

ADSP

ADSC

ZZ

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.

tKLtKL

tZZR

tZZHtZZS

Rev: 1.17a 4/2006 23/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

TQFP Package Drawing (Package T)

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15

A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 — 0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch — 0.65 —

L Foot Length 0.45 0.60 0.75

L1 Lead Length — 1.00 —

Y Coplanarity 0.10

θ Lead Angle 0° — 7°

L1

A1

θ

L

c

Pin 1

D1

D

e

b

A2

Y

E1

E

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Rev: 1.17a 4/2006 24/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Package Dimensions—119-Bump FPBGA (Package B, Variation 1)

Pin #1 Corner

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

1 2 3 4 5 6 7

0.70 REF

Ø0.10
Ø0.30

Ø1.00(3x) REF

19.50

S

S

22±0.20

22±0.20

B

C

S

C A B

20.32

BOTTOM VIEW

S

Ø0.60~0.90 (119x)

7 6 5 4 3 2 1

1.27

A1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

1.27

12.00

A

0.20(4x)

C

30 TYP.

0.15

0.90±0.10

C

0.56±0.05

SEATING PLANE

C

0.15

2.06.±0.13

0.50~0.70

7.62

14±0.20

Rev: 1.17a 4/2006 25/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMs

2

Org

256K x 18 GS84018AT-190 Pipeline/Flow Through TQFP 190/7.5 C

256K x 18 GS84018AT-180 Pipeline/Flow Through TQFP 180/8 C

256K x 18 GS84018AT-166 Pipeline/Flow Through TQFP 166/8.5 C

256K x 18 GS84018AT-150 Pipeline/Flow Through TQFP 150/10 C

256K x 18 GS84018AT-100 Pipeline/Flow Through TQFP 100/12 C

128K x 32 GS84032AT-190 Pipeline/Flow Through TQFP 190/7.5 C

128K x 32 GS84032AT-180 Pipeline/Flow Through TQFP 180/8 C

128K x 32 GS84032AT-166 Pipeline/Flow Through TQFP 166/8.5 C

128K x 32 GS84032AT-150 Pipeline/Flow Through TQFP 150/10 C

128K x 32 GS84032AT-100 Pipeline/Flow Through TQFP 100/12 C

128K x 36 GS84036AT-190 Pipeline/Flow Through TQFP 190/7.5 C

128K x 36 GS84036AT-180 Pipeline/Flow Through TQFP 180/8 C

128K x 36 GS84036AT-166 Pipeline/Flow Through TQFP 166/8.5 C

128K x 36 GS84036AT-150 Pipeline/Flow Through TQFP 150/10 C

128K x 36 GS84036AT-100 Pipeline/Flow Through TQFP 100/12 C

256K x 18 GS84018AT-190I Pipeline/Flow Through TQFP 190/7.5 I

256K x 18 GS84018AT-180I Pipeline/Flow Through TQFP 180/8 I

256K x 18 GS84018AT-166I Pipeline/Flow Through TQFP 166/8.5 I

256K x 18 GS84018AT-150I Pipeline/Flow Through TQFP 150/10 I

256K x 18 GS84018AT-100I Pipeline/Flow Through TQFP 100/12 I

128K x 32 GS84032AT-190I Pipeline/Flow Through TQFP 190/7.5 I

128K x 32 GS84032AT-180I Pipeline/Flow Through TQFP 180/8 I

128K x 32 GS84032AT-166I Pipeline/Flow Through TQFP 166/8.5 I

128K x 32 GS84032AT-150I Pipeline/Flow Through TQFP 150/10 I

128K x 32 GS84032AT-100I Pipeline/Flow Through TQFP 100/12 I

128K x 36 GS84036AT-190I Pipeline/Flow Through TQFP 190/7.5 I

128K x 36 GS84036AT-180I Pipeline/Flow Through TQFP 180/8 I

128K x 36 GS84036AT-166I Pipeline/Flow Through TQFP 166/8.5 I

128K x 36 GS84036AT-150I Pipeline/Flow Through TQFP 150/10 I

128K x 36 GS84036AT-100I Pipeline/Flow Through TQFP 100/12 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (

Part Number

1

Type Package

www.gsitechnology.com) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Status

Rev: 1.17a 4/2006 26/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMs (Continued)

2

Org

256K x 18 GS84018AGT-190 Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 C

256K x 18 GS84018AGT-180 Pipeline/Flow Through RoHS-compliant TQFP 180/8 C

256K x 18 GS84018AGT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 C

256K x 18 GS84018AGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/10 C

256K x 18 GS84018AGT-100 Pipeline/Flow Through RoHS-compliant TQFP 100/12 C

128K x 32 GS84032AGT-190 Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 C

128K x 32 GS84032AGT-180 Pipeline/Flow Through RoHS-compliant TQFP 180/8 C

128K x 32 GS84032AGT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 C

128K x 32 GS84032AGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/10 C

128K x 32 GS84032AGT-100 Pipeline/Flow Through RoHS-compliant TQFP 100/12 C

128K x 36 GS84036AGT-190 Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 C

128K x 36 GS84036AGT-180 Pipeline/Flow Through RoHS-compliant TQFP 180/8 C

128K x 36 GS84036AGT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 C

128K x 36 GS84036AGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/10 C

128K x 36 GS84036AGT-100 Pipeline/Flow Through RoHS-compliant TQFP 100/12 C

256K x 18 GS84018AGT-190I Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 I

256K x 18 GS84018AGT-180I Pipeline/Flow Through RoHS-compliant TQFP 180/8 I

256K x 18 GS84018AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 I

256K x 18 GS84018AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I

256K x 18 GS84018AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I

128K x 32 GS84032AGT-190I Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 I

128K x 32 GS84032AGT-180I Pipeline/Flow Through RoHS-compliant TQFP 180/8 I

128K x 32 GS84032AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 I

128K x 32 GS84032AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I

128K x 32 GS84032AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I

128K x 36 GS84036AGT-190I Pipeline/Flow Through RoHS-compliant TQFP 190/7.5 I

128K x 36 GS84036AGT-180I Pipeline/Flow Through RoHS-compliant TQFP 180/8 I

128K x 36 GS84036AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 I

128K x 36 GS84036AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I

128K x 36 GS84036AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I

256K x 18 GS84018AB-190 Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.

3. T

A = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Status

Rev: 1.17a 4/2006 27/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMs (Continued)

2

Org

256K x 18 GS84018AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C

256K x 18 GS84018AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C

256K x 18 GS84018AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C

256K x 18 GS84018AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C

128K x 32 GS84032AB-190 Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 C

128K x 32 GS84032AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C

128K x 32 GS84032AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C

128K x 32 GS84032AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C

128K x 32 GS84032AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C

128K x 36 GS84036AB-190 Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 C

128K x 36 GS84036AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C

128K x 36 GS84036AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C

128K x 36 GS84036AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C

128K x 36 GS84036AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C

256K x 18 GS84018AB-190I Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 I

256K x 18 GS84018AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I

256K x 18 GS84018AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I

256K x 18 GS84018AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I

256K x 18 GS84018AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I

128K x 32 GS84032AB-190I Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 I

128K x 32 GS84032AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I

128K x 32 GS84032AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I

128K x 32 GS84032AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I

128K x 32 GS84032AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I

128K x 36 GS84036AB-190I Pipeline/Flow Through 119 BGA (var. 1) 190/7.5 I

128K x 36 GS84036AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I

128K x 36 GS84036AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I

128K x 36 GS84036AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I

128K x 36 GS84036AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I

256K x 18 GS84018AGB-190 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 C

256K x 18 GS84018AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.

3. T

A = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Status

Rev: 1.17a 4/2006 28/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS84018/32/36AT/B-190/180/166/150/100

Ordering Information for GSI Synchronous Burst RAMs (Continued)

2

Org

256K x 18 GS84018AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C

256K x 18 GS84018AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C

256K x 18 GS84018AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C

128K x 32 GS84032AGB-190 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 C

128K x 32 GS84032AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C

128K x 32 GS84032AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C

128K x 32 GS84032AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C

128K x 32 GS84032AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C

128K x 36 GS84036AGB-190 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 C

128K x 36 GS84036AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C

128K x 36 GS84036AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C

128K x 36 GS84036AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C

128K x 36 GS84036AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C

256K x 18 GS84018AGB-190I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 I

256K x 18 GS84018AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I

256K x 18 GS84018AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I

256K x 18 GS84018AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I

256K x 18 GS84018AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I

128K x 32 GS84032AGB-190I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 I

128K x 32 GS84032AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I

128K x 32 GS84032AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I

128K x 32 GS84032AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I

128K x 32 GS84032AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I

128K x 36 GS84036AGB-190I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 190/7.5 I

128K x 36 GS84036AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I

128K x 36 GS84036AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I

128K x 36 GS84036AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I

128K x 36 GS84036AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AT-8T.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.

3. T

A = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Status

Rev: 1.17a 4/2006 29/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

9Mb Sync SRAM Datasheet Revision History

GS84018/32/36AT/B-190/180/166/150/100

Rev. Code: Old;

New

GS84018/32/36 Rev 1.02c 5/1999;

GS84018/32/36A 1.00First Release

8/1999D

GS84018/32/36A1.00 8/

1999;GS84018/32/36A1.01 9/

1999E

GS84018/32/36A1.01 9/

1999E;GS84018/32/36A1.02

GS84018/32/36A1.0210-11/

1999;GS84018/32/36A1.032/

2000G

GS84018/32/36A1.032/2000G;

84018A_r1_04

Types of Changes

Format or Content

Format/Typos

Content

Format/Typos

Content

Format

Content

Page /Revisions;Reason

• Document/Continued changing to new format.

• First Datasheet for this part.

• Took “E” out of 840HE...in Core and Interface Voltages.

• Pin outs/New small caps format.

• Timing Diagrams/New format.

• Block Diagrams/New small caps format.

• Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to
DQB3.

• Pin Description/Rearranged Address Inputs to match order on
TQFP Pinout.

• TQFP Package Diagram/Corrected Dimension D Max from

20.1 to 22.1.

• Fixed Ordering information and speed bins.

• Took out Fine Pitch BGA Package. Package change in
progress.

• New GSI Logo

• Took “Pin” out of heading for consistency.

• Corrected all part order numbers

84018A_r1_04; 84018A_r1_05 Content

84018A_r1_05; 84018A_r1_06 Content

84018A_r1_06; 84018A_r1_07 Content/Format

84018A_r1_07; 84018A_r1_08 Content/Format

84018A_r1_08; 84018A_r1_09 Content

84018A_r1_09, 84018A_r1_10 Content

84018A_r1_10; 84018A_r1_11 Content

84018A_r1_11; 84018A_r1_12 Content

84018A_r1_12; 84018A_r1_13 Content

• Updated pin descriptions table

• Updated BGA pin description table to meet JEDEC standard

• Added “non-A” speed bins to Operating Currents table, AC
Electrical Characteristics table, and Ordering Information
table

• Updated format to fit Technical Documentation standards

• Updated font

• Corrected IDD for 150 MHz and 100 MHz on page 1 and page
18

• Updated table on page 1

• Updated Operating Currents table on page 18

• Updated Electrical Characteristics table on page 19

• Reduced IDD by 20 mA in table on page 1 and Operating
Currents table

• Corrected incorrect package type in ordering information table

• Removed 200 MHz references from entire datasheet

• Updated format

• Added 190 MHz speed bin

Rev: 1.17a 4/2006 30/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

9Mb Sync SRAM Datasheet Revision History

GS84018/32/36AT/B-190/180/166/150/100

Rev. Code: Old;

New

84018A_r1_13; 840xxA_r1_14 Content/Format

84018A_r1_14; 840xxA_r1_15 Content/Format

84018A_r1_15; 840xxA_r1_16 Content

84018A_r1_16; 840xxA_r1_17 Content

Types of Changes

Format or Content

Page /Revisions;Reason

• Updated entire format

• Corrected current numbers to match NBT parts

• Removed Preliminary banner

• Added Pb-free TQFP information

• Added variation number to 119 BGA information

• Added Ambient Temperature note (#3) on page 17

• Removed note #2 from Recommended Operating
Temperatures table on page 17

• (Rev. 1.17a): Changed Pb-free to RoHS-compliant, added
119 BGA RoHS part, corrected incorrect temperature
designator in ordering information table

Rev: 1.17a 4/2006 31/31 © 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.