Datasheet GS8324Z72C-250I, GS8324Z72C-250, GS8324Z36C-150, GS8324Z36C-133, GS8324Z36B-250I Datasheet (GSI)

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

119- and 209-Pin BGA

2M x 18, 1M x 36, 512K x 72

Commercial Temp
Industrial Temp

36Mb Sync NBT SRAMs

Features

• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs

• FT pin for user-configurable flow through or pipeline operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

3.3 V

2.5 V

Flow

Through

2-1-1-1

3.3 V

2.5 V

t

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

Curr (x18)
Curr (x36)
Curr (x72)

t

KQ

tCycle

Curr (x18)
Curr (x36)
Curr (x72)

Curr (x18)
Curr (x36)
Curr (x72)

2.3

4.0

365
560
660

360
550
640

6.0

7.0

235
300
350

235
300
340

2.5

4.4

335
510
600

330
500
590

6.5

7.5

230
300
350

230
300
340

3.0

3.5

5.0

6.0

305

265

460

400

540

460

305

260

460

390

530

450

7.5

8.51010101115ns

8.5

210

200

270

270

300

300

210

200

270

270

300

300

3.8

6.6

245
370
430

240
360
420

195
270
300

195
270
300

4.0

7.5nsns

215

mA

330

mA

380

mA

215

mA

330

mA

370

mA

150

mA

200

mA

220

mA

145

mA

190

mA

220

mA

250 MHz–133MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is

ns

retained during Sleep mode.

Core and Interface Voltages

The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V

) pins are used to decouple output noise from the internal

DDQ

circuits and are 3.3 V and 2.5 V compatible.

DD

Functional Description

Applications

The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge­triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated

Rev: 1.00 10/2001 1/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z72B Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A DQG5 DQG1 A13 E2 A14 ADV A15 E3 A17 DQB1 DQB5 A

B DQG6 DQG2 BC BG NC W A16 BB BF DQB2 DQB6 B

C DQG7 DQG3 BH BD NC E1 NC BE BA DQB3 DQB7 C

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G NC NC

V

DDQ

V

V

DDQ

V

V

DDQ

D DQG8 DQG4

E DQPG9 DQPC9

F DQC4 DQC8

G DQC3 DQC7

H DQC2 DQC6

J DQC1 DQC5

K NC NC CK NC

L DQH1 DQH5

M DQH2 DQH6

N DQH3 DQH7

P DQH4 DQH8

R DQPD9 DQPH9

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

ZQ

MCH

MCL

MCH

MCL

FT

MCL

MCH

ZZ

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

DQB4 DQB8 D

DQPF9 DQPB9 E

DQF8 DQF4 F

DQF7 DQF3 G

DQF6 DQF2 H

DQF5 DQF1 J

DQA5 DQA1 L

DQA6 DQA2 M

DQA7 DQA3 N

DQA8 DQA4 P

DQPA9 DQPE9 R

T DQD8 DQD4

V

SS

NC NC LBO PE NC

V

SS

DQE4 DQE8 T

U DQD7 DQD3 NC A12 NC A11 A18 A10 NC DQE3 DQE7 U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 2/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z36C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A13 E2 A14 ADV A15 E3 A17 DQB1 DQB5 A

B NC NC BC NC A19 W A16 BB NC DQB2 DQB6 B

C NC NC NC BD NC E1 NC NC BA DQB3 DQB7 C

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G NC NC

V

DDQ

V

V

DDQ

V

V

DDQ

D NC NC

E NC DQPC9

F DQC4 DQC8

G DQC3 DQC7

H DQC2 DQC6

J DQC1 DQC5

K NC NC CK NC

L NC NC

M NC NC

N NC NC

P NC NC

R DQPD9 NC

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

ZQ

MCH

MCL

MCH

MCL

FT

MCL

MCH

ZZ

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

DQB4 DQB8 D

NC DQPB9 E

NC NC F

NC NC G

NC NC H

NC NC J

DQA5 DQA1 L

DQA6 DQA2 M

DQA7 DQA3 N

DQA8 DQA4 P

DQPA9 NC R

T DQD8 DQD4

V

SS

NC NC LBO PE NC

V

SS

NC NC T

U DQD7 DQD3 NC A12 NC A11 A18 A10 NC NC NC U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 NC NC V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 3/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A13 VDD A14 ADV A15 VSS A17 NC NC A

B NC NC BB NC A19 W A16 NC NC NC NC B

C NC NC NC NC NC E1 A20 NC BA NC NC C

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G NC NC

V

DDQ

V

V

DDQ

V

V

DDQ

D NC NC

E NC DQPB9

F DQB4 DQB8

G DQB3 DQB7

H DQB2 DQB6

J DQB1 DQB5

K NC NC CK NC

L NC NC

M NC NC

N NC NC

P NC NC

R NC NC

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

ZQ

MCH

MCL

MCH

MCL

FT

MCL

VDD

ZZ

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC D

NC NC E

NC NC F

NC NC G

NC NC H

NC NC J

DQA5 DQA1 L

DQA6 DQA2 M

DQA7 DQA3 N

DQA8 DQA4 P

DQPA9 NC R

T NC NC

V

SS

NC NC LBO PE NC

V

SS

NC NC T

U NC NC NC A12 NC A11 A18 A10 NC NC NC U

V NC NC A9 A8 A7 A1 A6 A5 A4 NC NC V

W NC NC TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 4/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

W6, V6 A0, A1 I Address field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,

A3, A5, A7, B7, A9, U7

B5 A19 I Address Inputs (x36/x18 Versions)
C7 A20 I Address Inputs (x18 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

L11, M11, N11, P11, L10, M10, N10, P10, R10

J1, H1, G1, F1, J2, H2, G2, F2, E2

C9, B8

B3, C4

C8, B9, B4, C3

B5 NC — No Connect (x72 Version)
C7 NC — No Connect (x72/x36 Versions)

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,

B4, C3
B3, C4 NC — No Connect (x18 Version)

C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,

K11, T4, T5, T7, T8, U3, U5, U9

K3 CK I Clock Input Signal; active high
C6
A8
A4
D6
A6

An I Address Inputs

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9

DQA1–DQA9
DQB1–DQB9

BA, BB

BC,BD

BE, BF, BG,BH

NC — No Connect (x36/x18 Versions)

NC — No Connect

E1
E3
E2

G

ADV

I/O Data Input and Output pins (x72 Version)

I/O Data Input and Output pins (x36 Version)

I/O Data Input and Output pins (x18 Version)

I Byte Write Enable for DQA, DQB I/Os; active low

I

I

I Chip Enable; active low
I Chip Enable; active low (x72/x36 Versions)
I Chip Enable; active high (x72/x36 Versions)
I Output Enable; active low
I Burst address counter advance enable

Preliminary

Byte Write Enable for DQC, DQD I/Os; active low

(x72/x36 Versions)

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

(x72 Version)

Rev: 1.00 10/2001 5/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

Preliminary

P6
L6
T6

G6, J6

N6

H6, J6, K6, M6

A8, N6

B6

T7

F6

W3
W4
W8
W9

A4, N6

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7

D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9

E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9

ZZ
FT

LBO
MCH
MCH
MCL
MCL

W

PE

ZQ

TMS

TDI

TDO

TCK

V

DD

V

DD

V

SS

V

DDQ

I Sleep Mode control; active high
I Flow Through or Pipeline mode; active low
I Linear Burst Order mode; active low
I Must Connect High
I Must Connect High (x72 and x36 versions)

Must Connect Low

Must Connect Low (x18 version)

I Write Enable; active low

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36

I

FLXDrive Output Impedance Control

I

(Low = Low Impedance [High Drive], High = High Impedance [Low

I Scan Test Mode Select
I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock
I Core power supply (x18 version)

I Core power supply

I I/O and Core Ground

I Output driver power supply

Mode)

Drive])

Rev: 1.00 10/2001 6/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z36B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

Preliminary

A V

DDQ

A6 A7 A18 A8 A9 V

DDQ

B NC E2 A4 ADV A15 E3 NC B
C NC A5 A3 V

D DQC DQPC V

E DQC DQC V

F V

DDQ

DQC V

SS

SS

SS

DD

ZQ V

E1 V

G V

A14 A16 NC C

SS

SS

SS

DQPB DQB D

DQB DQB E

DQB V

DDQ

G DQC DQC BC A17 BB DQB DQB G
H DQC DQC V

J V

DDQ

V

DD

K DQD DQD V

SS

NC V

SS

W V

DD

CK V

SS

NC V

SS

DQB DQB H

DD

V

DDQ

DQA DQA K

L DQD DQD BD NC BA DQA DQA L

M V

DDQ

N DQD DQD V

P DQD DQPD V

DQD V

SS

SS

SS

CKE V

A1 V

A0 V

SS

SS

SS

DQA V

DDQ

DQA DQA N

DQPA DQA P

A

F

J

M

R NC A2 LBO V

DD

FT A13 PE R

T NC NC A10 A11 A12 A19 ZZ T

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 7/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

Preliminary

A V

DDQ

A6 A7 A18 A8 A9 V

DDQ

B NC VDD A4 ADV A15 VSS NC B
C NC A5 A3 V

D DQB NC V

E NC DQB V

F V

DDQ

NC V

SS

SS

SS

DD

ZQ V

E1 V

G V

A14 A16 NC C

SS

SS

SS

DQPA NC D

NC DQA E

DQA V

DDQ

G NC DQB BB A17 NC NC DQA G
H DQB NC V

J V

DDQ

V

DD

K NC DQB V

SS

NC V

SS

W V

DD

CK V

SS

NC V

SS

DQA NC H

DD

V

DDQ

NC DQA K

L DQB NC NC VDD BA DQA NC L

M V

DDQ

N DQB NC V

P NC DQPB V

DQB V

SS

SS

SS

CKE V

A1 V

A0 V

SS

SS

SS

NC V

DDQ

DQA NC N

NC DQA P

A

F

J

M

R NC A2 LBO V

DD

FT A13 PE R

T NC A10 A11 A20 A12 A19 ZZ T

U V

DDQ

TMS TDI TCK TDO NC V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 8/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

R2, C3, B3, C2, A2, A3, A5, A6, T3,

T5, R6, C5, B5, C6, G4, A4

T4, T6 An Address Input (x36 Version)

T2 NC — No Connect (x36 Version)

T2, T6, T4 An I Address Input (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6
H7, G7, E7, D7, H6, G6, F6, E6
H1, G1, E1, D1, H2, G2, F2, E2

K1, L1, N1, P1, K2, L2, M2, N2

P6, D6, D2, P2

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

B1, C1, R1, T1, U6, B7, C7, J3, J5 NC — No Connect

P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3

L4 NC — No Connect (x36 Version)

K4 CK I Clock Input Signal; active high
M4 CKE I Clock Enable; active low
H4 W I Write Enable; active low

E4 E1 I Chip Enable; active low

B6 E3 I Chip Enable; active low (x36 version)

B2 E2 I Chip Enable; active high (x36 version)

F4 G I Output Enable; active low

B4 ADV I Burst address counter advance enable

T7 ZZ I Sleep mode control; active high
R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low

D4 ZQ I

R7 PE I Parity Bit Enable; active low
U2
U3

An I Address Inputs

DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8

DQA9, DQB9,

DQC9, DQD9

DQA1–DQA9
DQB1–DQB9

NC — No Connect (x18 Version)

TMS

TDI

I/O Data Input and Output pins. (x36 Version)

I/O Data Input and Output pins. (x36 Version)

I/O Data Input and Output pins (x18 Version)

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],

High = High Impedance [Low Drive])

I Scan Test Mode Select
I Scan Test Data In

Preliminary

Rev: 1.00 10/2001 9/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

U5
U4

J2, C4, J4, R4, J6

B2, L4

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

B6

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

TDO
TCK

V
V

V

V

V

DDQ

DD

DD

SS

SS

O Scan Test Data Out

I Scan Test Clock
I Core power supply
I Core power supply (x18 version)

I I/O and Core Ground

I I/O and Core Ground (x18 version)

I Output driver power supply

Rev: 1.00 10/2001 10/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18/36/72 Block Diagram

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW

BA

BB

BC

BD

Register

D Q

A0

A1

D0
D1

Counter

Load

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Q0
Q1

A0
A1

A

Memory

Array

Q D

36

4

DQ

Register

36

Register

DQ

E1

FT

G

ZZ

Note: Only x36 version shown for simplicity.

Power Down

Control

Register

D Q

Register

D Q

Register

D Q

36

36

36

DQx0–DQx9

36

Rev: 1.00 10/2001 11/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18 Die Layout

GS8324Z36 Die Layout

Die A

x18

16Mb

Die A

x18

16Mb

Inputs

TDO TDI TDOTDI

Die B

x18

16Mb

18 I/Os

Inputs

TDO TDI TDOTDI

Die B

x18

16Mb

18 I/Os 18 I/Os

GS8324Z72 Die Layout

Inputs

Die A

TDO TDI TDOTDI

x36

32Mb

36 I/Os 36 I/Os

Rev: 1.00 10/2001 12/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Die B

x36

32Mb

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.00 10/2001 13/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Preliminary

Rev: 1.00 10/2001 14/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Synchronous Truth Table (x72 and x36 209-Bump BGA)

Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a
Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write
cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.00 10/2001 15/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA)

Operation Type Address E1 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L L L L H X L L-H High-Z 2,3

Preliminary

Write Abort, Continue Burst B Next X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X L X X X X H L-H - 4
Sleep Mode None X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered
into if a Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs
when the W pin is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off
during write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write
cycle, the bus will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/
Write signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.00 10/2001 16/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pipelined and Flow Through Read Write Control State Diagram

Preliminary

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Rev: 1.00 10/2001 17/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Data I/O State Diagram

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

Intermediate State (N+1)

D

R

Intermediate

Transition

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

D

Clock (CK)

Command

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.00 10/2001 18/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

n n+1 n+2 n+3

ƒ

Current State

Intermediate

ƒ ƒ ƒ

Next State

State

Flow Through Mode Data I/O State Diagram

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

W

B

High Z
(Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.00 10/2001 19/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

Mode Pin Functions

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Parity Enable PE

FLXDrive Output Impedance Control ZQ

Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and a pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.

Pin

Name

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L or NC Activate 9th I/O’s (x18/36 Mode)

H Deactivate 9th I/O’s (x16/32 Mode)

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Standby, IDD = I

SB

Enable/Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Rev: 1.00 10/2001 20/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

x16/32/64 Mode (PE = 0) Read Parity Error Output Timing Diagram

CK

Address A Address B Address C Address D Address E Address F

Preliminary

DQ

D Out A D Out B D Out C D Out D D Out E

tKQ

tLZ

tKQX

tHZ

QE

Flow Through ModePipelined Mode

DQ

Err A Err C

D Out A D Out B D Out C D Out D

tKQ

tLZ

tKQX

tHZ

QE

Err A

Err C

Rev: 1.00 10/2001 21/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Linear Burst Sequence

I

x18/x36 Mode (PE = 1) Write Parity Error Output Timing Diagram

CK

Preliminary

DQ

QE

Flow Through ModePipelined Mode

DQ

QE

Burst Counter Sequences

D In A D In B D In C D In D D In E

tKQ

tLZ

Err A

D In A D In B D In C D In D D In E

tLZ

tKQ

tKQX

tHZ

Err C

tKQX

tHZ

Err A Err C

nterleaved Burst Sequence

BPR 1999.05.18

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Rev: 1.00 10/2001 22/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

ZZ

tZZS

~

Sleep

~

~

~

tZZR

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on . Not all vendors offer this option, however most mark as VDD or V

parts. GSI NBT SRAMs are fully compatible with these sockets.

on pipelined parts and VSS on flow through

DDQ

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

CK

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Voltage on VDD Pins
Voltage in V

Voltage on Clock Input Pin –0.5 to 6 V

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

DDQ

Pins

–0.5 to V

–0.5 to V

–0.5 to 4.6 V
–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V
V

o

o

C
C

Rev: 1.00 10/2001 23/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

V

DD3

V

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.4 2.5 2.7 V

V

Range Logic Levels

DDQ3

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL

IHQ

ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

1.7 —

–0.3 — 0.8 V 1

1.7 —

–0.3 — 0.8 V 1,3

VDD + 0.3

V

+ 0.3

DDQ

V 1

V 1,3

V

Range Logic Levels

DDQ2

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL

IHQ

ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Rev: 1.00 10/2001 24/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

VDD + 0.3

0.3*V

DD

V

+ 0.3

DDQ

0.3*V

DD

V 1
V 1
V 1,3
V 1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Note:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0 25 70 °C 2

–40 25 85 °C 2

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

– 2.0 V

SS

V

50%

IH

V

+ 2.0 V

DD

SS

20% tKC

50%

V

DD

V

IL

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance (x36/x72)

Input/Output Capacitance (x18)

Note: These parameters are sample tested.

C

IN

C

I/O

C

I/O

V
V

V

OUT

OUT

IN

= 0 V

= 0 V
= 0 V

6.5 7.5 pF
6 7 pF

8.5 9.5 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four

Junction to Case (TOP) —

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Rev: 1.00 10/2001 25/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

R
R
R

ΘJA
ΘJA

ΘJC

40 °C/W 1,2
24 °C/W 1,2

9 °C/W 3

AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

4. Device is deselected as defined by the Truth Table.

DQ

and t

OLZ

Output Load 1

OHZ

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Output Load 2

2.5 V

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ and PE Input Current

FT, SCD, ZQ, DP Input Current

Output Leakage Current (x36/x72)

Output Leakage Current (x18)

Output High Voltage
Output High Voltage

Output Low Voltage

50Ω

VT = 1.25 V

I

IL

I

IN1

I

IN2

I

OL

I

OL

V

OH2

V

OH3

V

OL

*

30pF

* Distributed Test Jig Capacitance

V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V
V

DD ≥ VIN ≥ VIL

0 V ≤ V

Output Disable, V
Output Disable, V

I

= –8 mA, V

OH

I

= –8 mA, V

OH

I

OL

= 0 to V

IN

IN

OUT

OUT

DDQ

DDQ

= 8 mA

DQ

DD

≤ V

IH

≤ V

IL

= 0 to V

= 0 to V
= 2.375 V
= 3.135 V

5pF

DD

DD

225Ω

*

225Ω

–2 uA 2 uA
–1 uA

–1 uA

–100 uA

–1 uA

1 uA

100 uA

1 uA
1 uA

–1 uA 1 uA
–2 uA 2 uA

1.7 V —

2.4 V —
— 0.4 V

Rev: 1.00 10/2001 26/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Unit

to

–40

0

to

to

–40

0

to

to

–40

0

to

to

–40

0

to

to

–40

mA

360

85°C

340

70°C

400

85°C

380

70°C

430

85°C

410

70°C

500

85°C

480

70°C

550

85°C

mA

40

220

40

200

50

290

50

270

50

290

50

270

60

290

60

270

70

330

mA

20

330

20

310

30

360

30

340

30

390

30

370

30

450

30

430

40

490

mA

20

200

20

180

30

270

30

250

30

270

30

350

30

270

30

250

40

300

mA

20

220

20

205

20

245

20

230

20

265

20

250

20

305

20

290

20

330

mA

10

150

10

135

15

190

15

175

15

190

15

175

15

190

15

175

20

215

mA

10

360

10

340

10

400

10

380

10

430

10

410

10

500

10

480

10

550

mA

30

220

30

200

40

290

40

270

40

290

40

270

50

290

50

270

60

330

mA

20

330

20

310

30

360

30

340

30

390

30

370

30

450

30

430

30

490

mA

20

200

20

180

20

270

20

250

20

270

20

250

30

270

30

250

30

300

mA

10

220

10

205

20

245

20

230

20

265

20

250

20

305

20

290

20

330

mA

mA

mA

mA

mA

10

10

10

10

10

10

15

15

15

5

150

5

135

10

190

10

175

10

190

10

175

10

190

10

175

10

215

0

to

to

–40

-250 -225 -200 -166 -150 -133
0

to

70

530

70°C

80

560

85°C

80

580

70°C

40

340

40

330

40

310

40

470

40

540

40

520

20

280

20

300

20

280

20

315

20

360

20

345

10

200

10

215

10

200

60

530

60

600

60

580

30

310

30

330

30

310

30

470

30

540

30

520

20

280

20

300

20

280

15

315

15

360

15

345

10

200

10

215

10

40 60 40 60 40 60 40 60 40 60 40 60

200

40 60 40 60 40 60 40 60 40 60 40 60

170 180 160 170 150 160 130 140 120 130 100 110

120 130 120 130 100 110 100 110 100 110 90 100

operation.

DDQ2

, and V

SB

DD

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DDQ

I

SB

DD

I

I

DD

I

I

DDQ3

, V

DD2

, V

Flow

Pipeline

Through

(x72)

Flow

Pipeline

Through

(x36)

IL

Flow

Pipeline

Through

(x18)

Flow

Pipeline

Through

(x72)

Flow

Pipeline

Through

(x36)

IL

Flow

Pipeline

Through

(x18)

Flow

Pipeline

Through

—

Flow

Pipeline

Through

—

IL

DD3

– 0.2 V

or ≤ V

IH

≥V

Device Selected;

Output open

All other inputs

or ≤ V

IH

≥V

Device Selected;

Output open

All other inputs

DD

ZZ ≥ V

or ≤ V

IH

≥ V

All other inputs

Device Deselected;

apply to any combination of V

DDQ

and I

Operating Currents

Parameter Test Conditions Mode Symbol

Operating

Operating

3.3 V

Current

2.5 V

Current

Current

Standby

Current

Deselect

DD

Notes:

1. I

2. All parameters listed are worst case scenario.

Rev: 1.00 10/2001 27/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pipeline

Flow

Through

Parameter Symbol

-250 -225 -200 -166 -150 -133

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns

Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.4 — 3.8 — 4.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock Cycle Time tKC 7.0 — 7.5 — 8.5 — 10.0 — 10.0 — 15.0 — ns

Clock to Output Valid tKQ — 6.0 — 6.0 — 7.5 — 8.5 — 10.0 — 10.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns

Clock to Output in

High-Z

tHZ

1

1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns

G to output in Low-Z
G to output in High-Z

tOLZ

tOHZ

1

0 — 0 — 0 — 0 — 0 — 0 — ns

1

— 2.3 — 2.5 — 3.0 — 3.5 — 3.8 — 4.0 ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

ZZ hold time

tZZS
tZZH

2

5 — 5 — 5 — 5 — 5 — 5 — ns

2

1 — 1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 100 — 100 — 100 — 100 — 100 — 100 — ns

Unit

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Rev: 1.00 10/2001 28/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Read/Write Cycle Timing

1 2 3 4 5 6 7 8 9 10

CK

tH

tS

tKHWtKL tKC

CKE

tH

tS

E*

tH

tS

ADV

tH

tS

tH

tS

Bn

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

tS

tH

A0–An

DQA–DQD

A1

A2 A3

D(A1)

tS

D(A2)

tH

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

A4 A5 A6 A7

tKQLZ

(A2+1)

tKQ

D

tKQHZ

Q(A3)

Q(A4)

tGLQV

Q

(A4+1)

tOEHZ

tOELZ

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE UNDEFINED

tKHQZ

tKQX

Write
D(A7)

D(A5)

Q(A6)

DESELECT

Rev: 1.00 10/2001 29/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pipeline Mode No-Op, Stall and Deselect Timing

Preliminary

CK

CKE

E*

ADV

W

Bn

A0–An

1

tS

tS

tS

tS

tH

A1 A5

2

tH

tH

tH

A2

3

4

A3 A4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

Read
Q(A2)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

D(A1)

Q(A3)

Q(A2)

Write
D(A4)

Q(A3)

STALL

NOP

D(A4)

Read
Q(A5)

DESELECT

DON’T CARE UNDEFINED

Q(A5)

tKQHZ

CONTINUE
DESELECT

Rev: 1.00 10/2001 30/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Read/Write Cycle Timing

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

CK

CKE

E*

ADV

Bn

A0–An

DQ

1 2

tH

tS

tH

tS

tS

tH

tS

tH

tS

tH

tS

3

tKHWtKL

tH

4

5 6

7

tKC

A1 A2 A3 A4 A5 A6

D(A1)

D(A2)

tKQLZ

(A2+1)

tKQ

tKQHZ

D

Q(A3)

tGLQV

Q(A4)

Q

(A4+1)

tKHQZ

8

D(A5)

9

A7

Q(A6)

10

tS

tH

tOEHZ

tOELZ

tKQX

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE

DESELECT

Write
D(A7)

UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.00 10/2001 31/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Flow Through Mode No-Op, Stall and Deselect Timing

Preliminary

CK

CKE

E*

ADV

W

Bn

A0–An

1 2

tH

tS

tH

tS

tH

tS

3

4

A1 A5A2 A3 A4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

D(A1)

Read
Q(A2)

Q(A2)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Q(A3)

Write
D(A4)

Q(A3)

D(A4)

Q(A5)

tKQHZ

STALL

NOP

Read
Q(A5)

DESELECT

DON’T CARE UNDEFINED

CONTINUE
DESELECT

Rev: 1.00 10/2001 32/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Port Operation

Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes
the behavior of each die.

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by V

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

DDQ

.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Rev: 1.00 10/2001 33/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

0

Bypass Register

012

Instruction Register

TDI

ID Code Register

31 30 29

· · · ·

012

TDO

Boundary Scan Register

TMS
TCK

n

Test Access Port (TAP) Controller

· · ·· · ·

· · ·

012

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.00 10/2001 34/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ID Register Contents

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Die

Revision

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

Rev: 1.00 10/2001 35/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Run Test Idle

0

1 1 1

Select DR

1

Capture DR

Shift DR

1

Exit1 DR

Pause DR

Exit2 DR

Update DR

1

Select IR

0

1

0

0

Capture IR

0

Shift IR

1

0

0

1

1

Exit1 IR

0

Pause IR

1

1

0

0 0

1

Exit2 IR

1

Update IR

0

1 0

0

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc­tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift­DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.

Rev: 1.00 10/2001 36/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans­ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

100

TDO.
Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

1

1

1

Rev: 1.00 10/2001 37/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

2. V

3. 0 V ≤ V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

7. I

8. I

9. I

ILJ

OHJ
OLJ
OHJC
OHJC

≤ V

IN
IN

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V

≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

V
V
V
V

I
I

I

V

V

V

OHJC

V

IHJ3

ILJ3

IHJ2

ILJ2

INHJ

INLJ

OLJ

OHJ

OLJ

OLJC

V

DDQ

0.6 * V

Preliminary

V

2.0

–0.3 0.8 V 1

DD2

–0.3

–300 1 uA 2

–1 100 uA 3
–1 1 uA 4

1.7 — V 5, 6
— 0.4 V 5, 7

– 100 mV

— 100 mV V 5, 9

DD3

V

DD2

0.3 * V

+0.3

+0.3

DD2

V 1

V 1
V 1

— V 5, 8

JTAG Port AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

Rev: 1.00 10/2001 38/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DQ

JTAG Port AC Test Load

50Ω

VT = 1.25 V

* Distributed Test Jig Capacitance

30pF

*

JTAG Port Timing Diagram

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

tTKQ

tTKL

tTS tTH

tTKC

tTKH

TCK

TMS

TDI

TDO

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

Rev: 1.00 10/2001 39/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

GS8324Z18/36/72 Boundary Scan Chain Order

Bump

Order x72 x36 x18

x72 x36 x18

1(TBD)

Notes:

1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.

2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.

3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.

4. 1 = no connect, internally set to logic value 1

5. 0 = no connect, internally set to logic value 0

6. X = no connect, value is undefined

Rev: 1.00 10/2001 40/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

209 BGA Package Drawing

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

A1

C

A

aaa

e

∅b

D

D1

E1

e

Side View

E

Bottom View

Symbol Min Typ Max Units

A 1.70 mm

A1 0.40 0.50 0.60 mm

∅b 0.50 0.60 0.70 mm

c 0.31 0.36 0.38 mm

D 21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E 13.9 14.0 14.1 mm

E1 10.0 (BSC) mm

e 1.00 (BSC) mm

aaa 0.15 mm

Rev 1.0

Rev: 1.00 10/2001 41/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Package Dimensions—119-Pin PBGA

119-Bump BGA Package

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Pin 1
Corner

A

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

B

G

D

S

1234567

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

R

Top View

Package Dimensions—119-Pin PBGA

Bottom View

F

C T

Side View

Symbol Description Min. Nom. Max

A Width 13.9 14.0 14.1
B Length 21.9 22.0 22.1
C Package Height (including ball) 1.73 1.86 1.99
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70

F Package Height (excluding balls) 1.16 1.26 1.36

G Width between Balls 1.27

K

E

K Package Height above board 0.65 0.70 0.75
R Width of package between balls 7.62
S Length of package between balls 20.32

T Variance of Ball Height 0.15

Unit: mm

Rev: 1.00 10/2001 42/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Ordering Information for GSI Synchronous NBT SRAMs

2

Org

2M x 18 GS8324Z18B-250 Pipeline/Flow Through 119 BGA 250/6 C
2M x 18 GS8324Z18B-225 Pipeline/Flow Through 119 BGA 225/6.5 C
2M x 18 GS8324Z18B-200 Pipeline/Flow Through 119 BGA 200/7.5 C
2M x 18 GS8324Z18B-166 Pipeline/Flow Through 119 BGA 166/8.5 C
2M x 18 GS8324Z18B-150 Pipeline/Flow Through 119 BGA 150/10 C
2M x 18 GS8324Z18B-133 Pipeline/Flow Through 119 BGA 133/11 C
2M x 18 GS8324Z18C-250 Pipeline/Flow Through 209 BGA 250/6 C
2M x 18 GS8324Z18C-225 Pipeline/Flow Through 209 BGA 225/6.5 C
2M x 18 GS8324Z18C-200 Pipeline/Flow Through 209 BGA 200/7.5 C
2M x 18 GS8324Z18C-166 Pipeline/Flow Through 209 BGA 166/8.5 C
2M x 18 GS8324Z18C-150 Pipeline/Flow Through 209 BGA 150/10 C
2M x 18 GS8324Z18C-133 Pipeline/Flow Through 209 BGA 133/11 C
1M x 36 GS8324Z36B-250 Pipeline/Flow Through 119 BGA 250/6 C
1M x 36 GS8324Z36B-225 Pipeline/Flow Through 119 BGA 225/6.5 C
1M x 36 GS8324Z36B-200 Pipeline/Flow Through 119 BGA 200/7.5 C
1M x 36 GS8324Z36B-166 Pipeline/Flow Through 119 BGA 166/8.5 C
1M x 36 GS8324Z36B-150 Pipeline/Flow Through 119 BGA 150/10 C
1M x 36 GS8324Z36B-133 Pipeline/Flow Through 119 BGA 133/11 C
1M x 36 GS8324Z36C-250 Pipeline/Flow Through 209 BGA 250/6 C
1M x 36 GS8324Z36C-225 Pipeline/Flow Through 209 BGA 225/6.5 C
1M x 36 GS8324Z36C-200 Pipeline/Flow Through 209 BGA 200/7.5 C
1M x 36 GS8324Z36C-166 Pipeline/Flow Through 209 BGA 166/8.5 C
1M x 36 GS8324Z36C-150 Pipeline/Flow Through 209 BGA 150/10 C

1M x 36 GS8324Z36C-133 Pipeline/Flow Through 209 BGA 133/11 C
512K x 72 GS8324Z72C-250 Pipeline/Flow Through 209 BGA 250/6 C
512K x 72 GS8324Z72C-225 Pipeline/Flow Through 209 BGA 225/6.5 C
512K x 72 GS8324Z72C-200 Pipeline/Flow Through 209 BGA 200/7.5 C
512K x 72 GS8324Z72C-166 Pipeline/Flow Through 209 BGA 166/8.5 C
512K x 72 GS8324Z72C-150 Pipeline/Flow Through 209 BGA 150/10 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Part Number

1

Type Package

Speed

(MHz/ns)

T

A

3

Rev: 1.00 10/2001 43/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Ordering Information for GSI Synchronous NBT SRAMs (Continued)

2

Org

512K x 72 GS8324Z72C-133 Pipeline/Flow Through 209 BGA 133/11 C

2M x 18 GS8324Z18B-250I Pipeline/Flow Through 119 BGA 250/6 I
2M x 18 GS8324Z18B-225I Pipeline/Flow Through 119 BGA 225/6.5 I
2M x 18 GS8324Z18B-200I Pipeline/Flow Through 119 BGA 200/7.5 I
2M x 18 GS8324Z18B-166I Pipeline/Flow Through 119 BGA 166/8.5 I
2M x 18 GS8324Z18B-150I Pipeline/Flow Through 119 BGA 150/10 I
2M x 18 GS8324Z18B-133I Pipeline/Flow Through 119 BGA 133/11 I
2M x 18 GS8324Z18C-250I Pipeline/Flow Through 209 BGA 250/6 I
2M x 18 GS8324Z18C-225I Pipeline/Flow Through 209 BGA 225/6.5 I
2M x 18 GS8324Z18C-200I Pipeline/Flow Through 209 BGA 200/7.5 I
2M x 18 GS8324Z18C-166I Pipeline/Flow Through 209 BGA 166/8.5 I
2M x 18 GS8324Z18C-150I Pipeline/Flow Through 209 BGA 150/10 I
2M x 18 GS8324Z18C-133I Pipeline/Flow Through 209 BGA 133/11 I
1M x 36 GS8324Z36B-250I Pipeline/Flow Through 119 BGA 250/6 I
1M x 36 GS8324Z36B-225I Pipeline/Flow Through 119 BGA 225/6.5 I
1M x 36 GS8324Z36B-200I Pipeline/Flow Through 119 BGA 200/7.5 I
1M x 36 GS8324Z36B-166I Pipeline/Flow Through 119 BGA 166/8.5 I
1M x 36 GS8324Z36B-150I Pipeline/Flow Through 119 BGA 150/10 I
1M x 36 GS8324Z36B-133I Pipeline/Flow Through 119 BGA 133/11 I
1M x 36 GS8324Z36C-250I Pipeline/Flow Through 209 BGA 250/6 I
1M x 36 GS8324Z36C-225I Pipeline/Flow Through 209 BGA 225/6.5 I
1M x 36 GS8324Z36C-200I Pipeline/Flow Through 209 BGA 200/7.5 I
1M x 36 GS8324Z36C-166I Pipeline/Flow Through 209 BGA 166/8.5 I
1M x 36 GS8324Z36C-150I Pipeline/Flow Through 209 BGA 150/10 I
1M x 36 GS8324Z36C-133I Pipeline/Flow Through 209 BGA 133/11 I

512K x 72 GS8324Z72C-250I Pipeline/Flow Through 209 BGA 250/6 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Part Number

1

Type Package

Speed

(MHz/ns)

T

A

3

Rev: 1.00 10/2001 44/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

Ordering Information for GSI Synchronous NBT SRAMs (Continued)

2

Org

512K x 72 GS8324Z72C-225I Pipeline/Flow Through 209 BGA 225/6.5 I
512K x 72 GS8324Z72C-200I Pipeline/Flow Through 209 BGA 200/7.5 I
512K x 72 GS8324Z72C-166I Pipeline/Flow Through 209 BGA 166/8.5 I
512K x 72 GS8324Z72C-150I Pipeline/Flow Through 209 BGA 150/10 I
512K x 72 GS8324Z72C-133I Pipeline/Flow Through 209 BGA 133/11 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8324Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Part Number

1

Type Package

Speed

(MHz/ns)

T

A

3

Rev: 1.00 10/2001 45/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

36Mb Sync SRAM Datasheet Revision History

Preliminary

GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)

DS/DateRev. Code: Old;

New

8324Z18_r1

Types of Changes
Format or Content

Page;Revisions;Reason

• Creation of new datasheet

Rev: 1.00 10/2001 46/46 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.