Datasheet GS8322Z18B-250I, GS8322Z18B-225I, GS8322Z18B-200I, GS8322Z18B-166I, GS8322Z18B-150I Datasheet (GSI TECHNOLOGY)

查询GS8322Z18E-133供应商

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

119, 165 & 209 BGA

36Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAM

Features

• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO

pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165- or 209-Bump BGA package

/low output drive

Functional Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

250 MHz–133 MHz 2.5

V or 3.3 V V

DD

2.5 V or 3.3 V I/O

Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge­triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­standard 119-bump, 165-bump or 209-bump BGA package.

) must be tied to a power

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

t

(x18/x36)

KQ

(x72)

t

KQ

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

Rev: 11/1/04 1/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tCycle

Curr

(x18)

Curr (x36)
Curr (x72)

t

KQ

tCycle

Curr

(x18)

Curr (x36)
Curr (x72)

2.5

3.0

4.0

285
350
440

6.5

6.5

205
235
315

2.7

3.0

4.4

265
320
410

7.0

7.0

195
225
295

3.0

3.0

5.0

245
295
370

7.5

7.5

185
210
265

3.5

3.5

6.0

220
260
320

8.0

8.0

175
200
255

3.8

3.8

6.7

210
240
300

8.5

8.5

165
190
240

4.0

4.0

7.5

185

mA

215

mA

265

mA

8.5

8.5nsns

155

mA

175

mA

230

mA

ns
ns
ns

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72C Pad Out—209-Bump BGA—Top View (Package C)

1234567891011

ADQ

BDQ

CDQ

DDQG DQG

E DQP

FDQ

GDQ

HDQ

JDQ

G DQG AE2AADVAE3ADQB DQB A

G DQG BC BG NC W ABBBF DQB DQB B

G DQG BH BD NC E1 NC BE BA DQB DQB C

G DQPC

C DQC

C DQC

C DQC

C DQC

V

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

SS

NC NC G NC NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

KNCNCCKNC

LDQ

MDQ

H DQH

H DQH

V

DDQ

V

SS

V

DDQ

V

SS

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

ZQ

MCH

MCL

MCH

CKE

FT

MCL

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

V

V

V

DDQ

V

DDQ

V

DDQ

SS

SS

NC NC NC NC K

V

DDQ

V

SS

V

DDQ

V

SS

DQB DQB D

DQPF DQPB E

DQF DQF F

DQF DQF G

DQF DQF H

DQF DQF J

DQA DQA L

DQA DQA M

NDQ

PDQ

R DQP

TDQ

UDQ

VDQ

WDQ

H DQH

H DQH

D DQPH

D DQD

D DQD NC A NC A A A NC DQE DQE U

D DQD AAAA1AAADQE DQE V

D DQD TMS TDI A A0 A TDO TCK DQE DQE W

V

V

DDQ

V

DDQ

V

SS

SS

V

DDQ

V

SS

V

DDQ

NC NC LBO NC NC

11 x 19 Bump BGA—14 x 22 mm

V

DD

V

SS

V

DD

MCH

ZZ

V

DD

V

DD

V

SS

V

DD

2

Body—1 mm Bump Pitch

V

V

DDQ

V

DDQ

SS

V

V

DDQ

V

DDQ

V

SS

SS

DQA DQA N

DQA DQA P

DQPA DQPE R

DQE DQE T

Rev: 1.04 11/2004 2/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72 209-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD
DQE
DQF
DQG
DQH

I/O Data Input and Output pins

A, BB

B

B

C,BD

B

E, BF, BG,BH

I Byte Write Enable for DQA, DQB I/Os; active low

I Byte Write Enable for DQC, DQD I/Os; active low

I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

E

1

E

3

E

2

G

ADV

ZZ

FT

LBO

MCH

MCH

MCL

W

I Chip Enable; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Burst address counter advance enable

I Sleep Mode control; active high

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I Must Connect High

I Must Connect High

Must Connect Low

I Write Enable; active low

FLXDrive Output Impedance Control

ZQ

I

Low = Low Impedance [High Drive],
High = High Impedance [Low Drive]

CKE

I Clock Enable; active low

Rev: 1.04 11/2004 3/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z72 209-Bump BGA Pin Description

Symbol Type Description

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 11/2004 4/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z36B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

V

DDQ

AAAAA

BNCE2AADVAE3

CNCA A

DDQCDQPC

EDQCDQC

F

V

DDQ

DQC

V

SS

V

SS

V

SS

V

DD

ZQ

E1

G

AANCC

V

SS

V

SS

V

SS

DQPB DQB D

DQB DQB E

DQB

V

DDQ

NC B

V

DDQ

GDQCDQCBC ABBDQB DQB G

HDQCDQC

J

V

DDQ

V

DD

KDQDDQD

V

NC

V

SS

SS

LDQDDQDBD

M

V

DDQ

DQD

V

SS

W

V

DD

CK

NC BA DQA DQA L

CKE

V

NC

V

V

SS

SS

SS

DQB DQB H

V

DD

V

DDQ

DQA DQA K

DQA

V

DDQ

A

F

J

M

NDQDDQD

PDQDDQPD

V

SS

V

SS

RNCALBO

A1

A0

V

DD

V

SS

V

SS

DQA DQA N

DQPA DQA P

FT ANCR

TNCNCAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.04 11/2004 5/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18B Pad Out—119-Bump BGA—Top View (Package B)

1234567

A

V

DDQ

AAAAA

BNCE2AADVAE3

CNCA A

DDQBNC

ENCDQB

F

V

DDQ

NC

V

SS

V

SS

V

SS

GNCDQBBB

HDQBNC

J

V

DDQ

V

DD

KNCDQB

V

NC

V

SS

SS

L DQB NC NC NC BA

M

V

DDQ

DQB

V

SS

V

ZQ

DD

E1

G

AANCC

V

SS

V

SS

V

SS

DQPA NC D

NC DQA E

DQA

ANCNCDQAG

V

NC

V

SS

SS

DQA NC H

V

DD

NC DQA K

V

CK

W

DD

DQA NC L

CKE

V

SS

NC

V

DDQ

NC B

V

DDQ

V

DDQ

V

DDQ

A

F

J

M

NDQBNC

PNCDQPB

V

SS

V

SS

RNCALBO

A1

A0

V

DD

V

SS

V

SS

DQA NC N

NC DQA P

FT ANCR

TNCAAAAAZZT

U

V

DDQ

TMS TDI TCK TDO NC

7 x 17 Bump BGA—14 x 22 mm

2

Body—1.27 mm Bump Pitch

V

DDQ

U

Rev: 1.04 11/2004 6/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18/36 119-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

DQ

A

DQB
DQC
DQD

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

B

NC — No Connect

CK I Clock Input Signal; active high

I/O Data Input and Output pins

CKE

W

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

G

I Clock Enable; active low

I Write Enable; active low

I Output Enable; active low

ADV I Burst address counter advance enable

ZZ I Sleep mode control; active high

FT

LBO

ZQ I

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

BPR1999.05.18

Rev: 1.04 11/2004 7/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

165 Bump BGA—x18 Common I/O—Top View (Package E)

1234567891011

ANC

BNC

CNCNC

DNC

ENC

FNC

GNC

HFT

J

K

L

DQB NC V

DQB NC V

DQB NC V

AE1BB NC E3 CKE ADV A A AA

AE2NCBACK W G A ANC B

V

DQB V

DQB V

DQB V

DQB V

MCH NC V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA NC J

DQA NC K

DQA NC L

M

N

DQB NC V

DQPB NC V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

V

DDQ

DDQ

DQA NC M

NC NC N

A ATDIA1 TDO A A ANC P

Rev: 1.04 11/2004 8/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

165 Bump BGA—x36 Common I/O—Top View (Package E)

1234567891011

ANC

BNC

C

D

E

F

G

H FT

K

L

DQPC NC V

DQC DQC V

DQC DQC V

DQC DQC V

DQC DQC V

MCH NC V

J

DQD DQD V

DQD DQD V

DQD DQD V

AE1BC BB E3 CKE ADV A A NC A

AE2BDBA CK W G A ANC B

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

V

V

V

V

V

V

V

SS

DD

DD

DD

DD

DD

DD

DD

DD

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC DQPB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

V

V

DDQ

DDQ

DDQ

DQA DQA J

DQA DQA K

DQA DQA L

M

N

DQD DQD V

DQPD NC V

PNCNC

RLBO

A A ATMSA0 TCK A A A AR

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

DDQ

DDQ

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

V

DDQ

DDQ

DQA DQA M

NC DQPA N

A ATDIA1 TDO A A ANC P

Rev: 1.04 11/2004 9/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

GS8322Z18/36E 165-Bump BGA Pin Description

Symbol Type Description

A0, A1 I Address field LSBs and Address Counter Preset Inputs

An I Address Inputs

A

18 I Address Input

DQ

A

DQB
DQC
DQD

B

A, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

NC — No Connect

CK I Clock Input Signal; active high

CKE

W

E

1 I Chip Enable; active low

E

3 I Chip Enable; active low

E

2 I Chip Enable; active high

I/O Data Input and Output pins

I Clock Enable; active low

I Write Enable; active low

FT

G

I Flow Through / Pipeline Mode Control

I Output Enable; active low

ADV I Burst address counter advance enable; active high

ZQ I

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

FLXDrive Output Impedance Control

ZZ I Sleep mode control; active high

LBO

TMS

TDI

TDO

TCK

MCH

V

DD

V

SS

V

DDQ

I Linear Burst Order mode; active low

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

— Must Connect High

I Core power supply

I I/O and Core Ground

I Output driver power supply

Rev: 1.04 11/2004 10/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load
activation is accomplished by asserting all three of the Chip Enable inputs (E
inputs will deactivate the device.

) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

pin (ADV) held low, in order to load the new address. Device

1, E2, and E3). Deassertion of any one of the Enable

Function W

BA BB BC BD

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE
chip enables (E

1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

is asserted low, all three

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B

A, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.04 11/2004 11/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Synchronous Truth Table

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Operation Type Address CK CKE

Read Cycle, Begin Burst R External L-H L L H X L H L L L Q

Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10

NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2

Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10

Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3

Write Cycle, Continue Burst B Next L-H L H X L X X X X L D 1,3,10

Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10

Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z

Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z

Deselect Cycle D None L-H L L L H L H L X L High-Z

Deselect Cycle, Continue D None L-H L H X X X X X X L High-Z 1

Sleep Mode None X X X X X X X X X H High-Z

Clock Edge Ignore, Stall Current L-H H X X X X X X X L - 4

ADV W Bx E1 E2 E3 G ZZ DQ Notes

1

Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese­lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G

can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during

write cycles.

4. If CKE

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx

6. All inputs, except G

7. Wait states can be inserted by setting CKE

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write

signals are Low

and ZZ must meet setup and hold times of rising clock edge.

high.

Rev: 1.04 11/2004 12/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

R

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Rev: 1.04 11/2004 13/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Pipeline Mode Data I/O State Diagram

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

R

D

Intermediate

Transition

Intermediate State (N+1)

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

D

Notes

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒƒƒ

Intermediate

Next State

State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.04 11/2004 14/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Flow Through Mode Data I/O State Diagram

W

B

High Z
(Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒƒƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.04 11/2004 15/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

). When this pin is Low, a linear burst

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

FLXDrive Output Impedance Control ZQ

Note:

There are pull-up devices on the ZQ and FT
operate in the default states as specified in the above tables.

Burst Counter Sequences

Pin

Name

pins and a pull-down devices on the ZZ pin, so those input pins can be unconnected and the chip will

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Linear Burst Sequence

Table 1:

A[1:0] A[1:0] A[1:0] A[1:0]

1st address00011011

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address11000110

Standby, I

DD

= I

SB

Interleaved Burst Sequence

Table 2:

A[1:0] A[1:0] A[1:0] A[1:0]

1st address00011011

2nd address 01 00 11 10

3rd address10110001

4th address11100100

Note:

The burst counter wraps to initial state on the 5th clock.

Rev: 1.04 11/2004 16/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

2. The duration of

SB

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKHtKH

tKCtKC

CK

ZZ

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT
all vendors offer this option, however most mark the pin V

SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal
pull-up device on the FT

pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode
part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device,
the pin will need to be pulled low for correct operation.

tKLtKL

DD

or V

tZZHtZZS

tZZR

signal. Not

on pipelined parts and VSS on flow through parts. GSI NBT

DDQ

Rev: 1.04 11/2004 17/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

Note:

V

I

T

T

V

DDQ

V

V

I

OUT

P

STG

BIAS

DD

I/O

IN

IN

D

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to V

–0.5 to 4.6 V

–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

V

V

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o

o

C

C

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

V

DD3

3.0 3.3 3.6 V

2.5 V Supply Voltage

3.3 V V

2.5 V V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

V

DD2

DDQ3

DDQ2

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

Rev: 1.04 11/2004 18/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

Range Logic Levels

DDQ3

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

V

DD

I/O Input High Voltage V

V

DDQ

I/O Input Low Voltage V

V

DDQ

IH

IL

IHQ

ILQ

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

V

V

DD

DDQ

+ 0.3

+ 0.3

V1

V1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

V

Range Logic Levels

DDQ2

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

V

DD

V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

V

DDQ

IH

IL

IHQ

ILQ

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

V

DD

0.3*V

V

DDQ

0.3*V

+ 0.3

DD

+ 0.3

DD

V1

V1

V1,3

V1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

Rev: 1.04 11/2004 19/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

02570°C2

–40 25 85 °C2

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

V

+ 2.0 V

DD

V

SS

50%

20% tKC

50%

– 2.0 V

SS

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note:

These parameters are sample tested.

C

IN

C

I/O

AC Test Conditions

Parameter Conditions

V

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

DQ

– 0.2 V

DD

V

/2

DDQ

V

/2

DDQ

Output Load 1

V

V

OUT

IN

= 0 V

= 0 V

V

DD

V

IL

45pF

67pF

30pF

*

V

DDQ/2

50Ω

* Distributed Test Jig Capacitance

Rev: 1.04 11/2004 20/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Input Leakage Current

(except mode pins)

ZZ Input Current

FT

, SCD, ZQ Input Current

Output Leakage Current (x36/x72)

Output Leakage Current (x18)

Output High Voltage

Output High Voltage

Output Low Voltage

V

V

I

I

IN1

I

IN2

I

OL

I

OL

OH2

OH3

V

OL

V

IL

Output Disable, V

Output Disable, V

I

OH

I

OH

= 0 to V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V

V

DD ≥ VIN ≥ VIL

0 V ≤ V

= –8 mA, V

= –8 mA, V

I

= 8 mA

OL

IN

IN

OUT

OUT

DDQ

DDQ

DD

≤ V

IH

≤ V

IL

= 0 to V

= 0 to V

= 2.375 V

= 3.135 V

DD

DD

–2 uA 2 uA

–1 uA
–1 uA

–100 uA

–1 uA

1 uA

100 uA

1 uA
1 uA

–1 uA 1 uA

–1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

Rev: 1.04 11/2004 21/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

–40

0

–40

0

–40

0

–40

0

–40

85°C

70°C

85°C

70°C

85°C

70°C

85°C

70°C

85°C

mA

255

235

280

260

300

280

340

320

370

Unit

to

to

to

to

to

to

to

to

to

30

30

40

40

40

40

50

50

60

220

210

220

210

235

225

245

235

265

mA

20

20

30

30

30

30

30

30

40

mA

210

190

230

210

245

225

275

255

295

25

25

30

30

35

35

40

40

45

170

160

180

170

190

180

200

190

210

mA

15

15

20

20

20

20

20

20

25

mA

190

170

210

190

220

200

245

225

260

15

15

20

20

20

20

20

20

25

mA

150

140

160

150

170

160

180

170

190

15

15

15

15

15

15

15

15

15

mA

mA

mA

mA

0

to

to

–40

-250 -225 -200 -166 -150 -133
0

to

Operating Currents

Parameter Test Conditions Mode Symbol

70°C

85°C

70°C

350

400

380

DD

I

Pipeline

60

60

60

I

DDQ

255

285

275

DD

I

Flow

(x72)

40

275

40

320

40

300

DD

I

DDQ

I

Through

Device Selected;

45

50

50

I

DDQ

I

Pipeline

(x36)

IL

or ≤ V

IH

≥V

All other inputs

Current

Operating

200

220

210

DD

Flow

Output open

25

240

25

280

25

260

DD

I

DDQ

I

Through

25

25

25

DDQ

I

Pipeline

(x18)

180

200

190

DD

I

Flow

15

15

60 80 60 80 60 80 60 80 60 80 60 80

15

SB

I

DDQ

I

Pipeline

Through

60 80 60 80 60 80 60 80 60 80 60 80

SB

I

Flow

Through

—

– 0.2 V

DD

ZZ ≥ V

Current

Standby

100 115 95 110 90 105 85 100 85 100 80 95

DD

I

Flow

Pipeline

—

All other inputs

Device Deselected;

Deselect

85 100 85 100 80 95 80 95 75 90 70 85

DD

I

Through

IL

or ≤ V

IH

≥ V

Current

operation.

DDQ2

, and V

DDQ3

, V

DD2

, V

DD3

apply to any combination of V

DDQ

and I

DD

Notes:

1. I

2. All parameters listed are worst case scenario.

Rev: 1.04 11/2004 22/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Parameter Symbol

-250 -225 -200 -166 -150 -133

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns

Pipeline

Clock to Output Valid

(x18/x36)

Clock to Output Valid

(x72)

tKQ — 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns

tKQ — 3.0 — 3.0 — 3.0 — 3.5 — 3.8 — 4.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Setup time tS 1.2 — 1.3 — 1.4 — 1.5 — 1.5 — 1.5 — ns

Clock Cycle Time tKC 6.5 — 7.0 — 7.5 — 8.0 — 8.5 — 8.5 — ns

Clock to Output Valid tKQ — 6.5 — 7.0 — 7.5 — 8.0 — 8.5 — 8.5 ns

Flow

Through

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns

Clock to Output in

High-Z

tHZ

1

1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns

(x18/x36)

Clock to Output in

1

High-Z

tHZ

1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns

(x72)

to Output Valid

G

(x18/x36)

G

to Output Valid

(x72)

to output in Low-Z

G

to output in High-Z

G

(x18/x36)

G

to output in High-Z

(x72)

ZZ setup time

ZZ hold time

tOE — 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns

tOE — 3.0 — 3.0 — 3.0 — 3.5 — 3.8 — 4.0 ns

1

tOLZ

tOHZ

tOHZ

tZZS

tZZH

0 — 0 — 0 — 0 — 0 — 0 — ns

1

— 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns

1

— 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 ns

2

5 — 5 — 5 — 5 — 5 — 5 — ns

2

1 — 1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Unit

Rev: 1.04 11/2004 23/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

CK

CKE

E*

ADV

Bn

A0–An

DQa–DQd

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Pipeline Mode Timing (NBT)

Write A Write B Write B+1 Read C Cont Read D Write E Read F DESELECT

tKL

tKL

tKHtKH

tH

tS

tH

tS

tH

tS

tH

tS

W

tH

tS

tH

tS

AB C DEFG

tS

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F)

tKC

tKC

tLZtH

tHZ

tKQXtKQ

tOLZ

tOEtOHZ

G

*Note: E

=High(False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.04 11/2004 24/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

CK

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Flow Through Mode Timing (NBT)

Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G

tKLtKL

tKHtKH

tKCtKC

CKE

ADV

Bn

A0–An

DQ

tS

tS

E

tS

tS

W

tS

tS

tH

tH

tH

tH

tH

tH

AB C DEFG

tLZtHZ

tKQ

tKQX

tH

tS

D(A) D(B) D(B+1) Q(C) Q(D) D(E) Q(F) D(G)

tLZ

tOLZ

tOE

tKQXtKQ

tOHZ

G

*Note: E

= High(False) if E1 = 1 or E2 = 0 or E3 = 1

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or VSS. TDO should be left unconnected.

DD

Rev: 1.04 11/2004 25/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

. The JTAG output

DD

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

Rev: 1.04 11/2004 26/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TDI

·· ······

·

·

108

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG TAP Block Diagram

Boundary Scan Register

0

Bypass Register

012

Instruction Register

ID Code Register

31 30 29 12

····

0

·

1

0

TDO

Control Signals

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Rev: 1.04 11/2004 27/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ID Register Contents

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Die

Revision

Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x72 XXXX0000000000001001000110110011

x36 XXXX000X100100001000000110110011

x32 XXXX0000000000001100000110110011

x18 XXXX000X100100001010000110110011

x16 XXXX0000000000001110000110110011

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

Rev: 1.04 11/2004 28/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Test Logic Reset

1

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG Tap Controller State Diagram

0

Run Test Idle

0

111

Select DR

1

Capture DR

Shift DR

1

Exit1 DR

Pause DR

Exit2 DR

Update DR

1

Select IR

0

1

0

0

Capture IR

0

Shift IR

1

0

0

1

1

Exit1 IR

0

Pause IR

1

1

0

0 0

1

Exit2 IR

1

Update IR

0

10

0

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili­tate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.

Rev: 1.04 11/2004 29/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc­tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso­ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ­ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high­Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

100

TDO.
Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

1

1

1

Rev: 1.04 11/2004 30/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

≤ V

2. V

ILJ

3. 0 V ≤ V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

OHJ

7. I

OLJ

8. I

OHJC

9. I

OHJC

IN

IN

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V

≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

JTAG Port AC Test Conditions

V

IHJ3

V

ILJ3

V

IHJ2

V

ILJ2

I

INHJ

I

INLJ

I

OLJ

V

OHJ

V

OLJ

V

OHJC

V

OLJC

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

2.0

–0.3 0.8 V 1

0.6 * V

DD2

–0.3

–300 1 uA 2

–1 100 uA 3

–11uA4

1.7 — V5, 6

— 0.4 V 5, 7

V

– 100 mV

DDQ

— 100 mV V 5, 9

V

DD3

V

DD2

0.3 * V

+0.3

+0.3

DD2

V1

V1

V1

— V5, 8

Parameter Conditions

V

Input high level

– 0.2 V

DD

DQ

JTAG Port AC Test Load

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

V

V

DDQ

DDQ

50Ω

/2

/2

* Distributed Test Jig Capacitance

V

DDQ

/2

30pF

*

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

Rev: 1.04 11/2004 31/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TCK

TDI

TMS

TDO

Parallel SRAM input

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

JTAG Port Timing Diagram

tTKLtTKLtTKHtTKHtTKCtTKC

tTH

tTS

tTH

tTS

tTKQ

tTH

tTS

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: [e-mail]

.

Rev: 1.04 11/2004 32/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

209 BGA Package Drawing (Package C)

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

A1

C

A

aaa

e

∅b

D

D1

E1

e

Side View

E

Bottom View

Symbol Min Typ Max Units

A 1.70 mm

A1 0.40 0.50 0.60 mm

∅b 0.50 0.60 0.70 mm

c 0.31 0.36 0.38 mm

D 21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E 13.9 14.0 14.1 mm

E1 10.0 (BSC) mm

e 1.00 (BSC) mm

aaa 0.15 mm

Rev 1.0

Rev: 1.04 11/2004 33/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Package Dimensions—165-Bump FPBGA (Package E; Variation 1)

A1

TOP VIEW

1 2 3 4 5 6 7 8 9 10 11

A

B
C
D

E
F
G

H
I
J

K
L
M

N
P
R

C

0.35

0.53 REF

M

Ø0.10

C

M

Ø0.25

C AB

Ø0.44~0.64(165x)

BOTTOM VIEW

A1

11 10 9 8 7 6 5 4 3 2 1

A

B
C
D

E

1.01.0

F
G

17±0.05

14.0

H
J
K

L
M
N

P
R

A

C

0.20

B

0.20(4x)

1.0 1.0

10.0

15±0.05

C

0.36 REF

SEATING PLANE

0.36~0.46

1.40 MAX.

Rev: 1.04 11/2004 34/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

A1

1 2 3 4 5 6 7

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

Package Dimensions—119-Bump FPBGA (Package B, Variation 2

TOP VIEW

Ø0.10
Ø0.30

S

C

S

C A B

BOTTOM VIEW

S

S

Ø0.60~0.90 (119x)

7 6 5 4 3 2 1

1.27

22±0.10

20.32

)

A1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

B

C

0.15

0.70±0.05

C

0.56±0.05

SEATING PLANE

C

0.15

1.86.±0.13

0.50~0.70

A

0.20(4x)

14±0.10

1.27

7.62

BPR 1999.05.18

Rev: 1.04 11/2004 35/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Ordering Information for GSI Synchronous Burst RAMs

2

Org

2M x 18 GS8322Z18B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 C

2M x 18 GS8322Z18B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 C

2M x 18 GS8322Z18B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 C

2M x 18 GS8322Z18B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 C

2M x 18 GS8322Z18B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 C

2M x 18 GS8322Z18B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C

2M x 18 GS8322Z18E-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 C

2M x 18 GS8322Z18E-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 C

2M x 18 GS8322Z18E-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 C

2M x 18 GS8322Z18E-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 C

2M x 18 GS8322Z18E-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 C

2M x 18 GS8322Z18E-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C

1M x 36 GS8322Z36B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 C

1M x 36 GS8322Z36B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 C

1M x 36 GS8322Z36B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 C

1M x 36 GS8322Z36B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 C

1M x 36 GS8322Z36B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 C

1M x 36 GS8322Z36B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C

1M x 36 GS8322Z36E-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 C

1M x 36 GS8322Z36E-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 C

1M x 36 GS8322Z36E-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 C

1M x 36 GS8322Z36E-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 C

1M x 36 GS8322Z36E-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 C

1M x 36 GS8322Z36E-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C

512K x 72 GS8322Z72C-250 NBT Pipeline/Flow Through 209 BGA 250/6.5 C

512K x 72 GS8322Z72C-225 NBT Pipeline/Flow Through 209 BGA 225/7 C

512K x 72 GS8322Z72C-200 NBT Pipeline/Flow Through 209 BGA 200/7.5 C

512K x 72 GS8322Z72C-166 NBT Pipeline/Flow Through 209 BGA 166/8 C

512K x 72 GS8322Z72C-150 NBT Pipeline/Flow Through 209 BGA 150/8.5 C

512K x 72 GS8322Z72C-133 NBT Pipeline/Flow Through 209 BGA 133/8.5 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Rev: 1.04 11/2004 36/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

Ordering Information for GSI Synchronous Burst RAMs (Cont.)

2

Org

2M x 18 GS8322Z18B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 I

2M x 18 GS8322Z18B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 I

2M x 18 GS8322Z18B-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 I

2M x 18 GS8322Z18B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 I

2M x 18 GS8322Z18B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 I

2M x 18 GS8322Z18B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 I

2M x 18 GS8322Z18E-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 I

2M x 18 GS8322Z18E-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 I

2M x 18 GS8322Z18E-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 I

2M x 18 GS8322Z18E-166I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 I

2M x 18 GS8322Z18E-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 I

2M x 18 GS8322Z18E-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I

1M x 36 GS8322Z36B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/6.5 I

1M x 36 GS8322Z36B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/7 I

1M x 36 GS8322Z36B-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/7.5 I

1M x 36 GS8322Z36B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/8 I

1M x 36 GS8322Z36B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 150/8.5 I

1M x 36 GS8322Z36B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 I

1M x 36 GS8322Z36E-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/6.5 I

1M x 36 GS8322Z36E-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 225/7 I

1M x 36 GS8322Z36E-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/7.5 I

1M x 36 GS8322Z36E-166I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/8 I

1M x 36 GS8322Z36E-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/8.5 I

1M x 36 GS8322Z36E-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I

512K x 72 GS8322Z72C-250I NBT Pipeline/Flow Through 209 BGA 250/6.5 I

512K x 72 GS8322Z72C-225I NBT Pipeline/Flow Through 209 BGA 225/7 I

512K x 72 GS8322Z72C-200I NBT Pipeline/Flow Through 209 BGA 200/7.5 I

512K x 72 GS8322Z72C-166I NBT Pipeline/Flow Through 209 BGA 166/8 I

512K x 72 GS8322Z72C-150I NBT Pipeline/Flow Through 209 BGA 150/8.5 I

512K x 72 GS8322Z72C-133I NBT Pipeline/Flow Through 209 BGA 133/8.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings.

Speed

(MHz/ns)

3

T

A

Rev: 1.04 11/2004 37/38 © 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

36Mb Sync SRAM Datasheet Revision History

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)

DS/DateRev. Code: Old;

New

8322Z18_r1

8322Z18_r1.01 C

8322Z18_r1.02 C

8322Z18_r1_03 Content

8322Z18_r1_04 Format/Content

Types of Changes
Format or Content

Page;Revisions;Reason

• Creation of new datasheet

• Add 165 BGA

• Fix missing address at B9 and ZQ at H10 in 165 pinouts

• Added 165-BGA package

• Updated all power numbers on page 1 and page 26

• Updated AC Characteristics table

• Removed all references to parity

• Updated tables on page 23

• Updated FT power numbers

• Updated Absolute Maximum Ratings table

• Corrected Capacitance table

• Updated tKQ (PL) numbers in table on page 1

• Updated DC Electrical Characteristics table

• Removed Output Load 2 diagram on page 15

• Updated standby current numbers in Operating Current table

• Updated timing diagrams

• Updated format

• Added variation information to package mechanicals

Rev: 1.04 11/2004 38/38 © 2002, GSI Technology

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