Datasheet GS832272C-250, GS832272C-225, GS832272C-200, GS832272C-166, GS832272C-150 Datasheet (GSI)

Rev: 1.00 10/2001 1/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

2M x 18, 1M x 36, 512K x 72

36Mb S/DCD Sync Burst SRAMs

250 MHz–133MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

119- and 209-Pin BGA
Commercial Temp
Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• On-chip parity encoding and error detection

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 209-bump BGA package

Functional Description

Applications

The GS832218/36/72 is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge­triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.

SCD and DCD Pipelined Reads

The GS832218/36/72 is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.

Core and Interface Voltages

The GS832218/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V

DDQ

) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

t

KQ

tCycle

2.3

4.0

2.5

4.4

3.0

5.0

3.5

6.0

3.8

6.6

4.0

7.5nsns

3.3 V

Curr (x18)
Curr (x36)
Curr (x72)

365
560
660

335
510
600

305
460
540

265
400
460

245
370
430

215
330
380

mA
mA
mA

2.5 V

Curr (x18)
Curr (x36)
Curr (x72)

360
550
640

330
500
590

305
460
530

260
390
450

240
360
420

215
330
370

mA
mA
mA

Flow

Through

2-1-1-1

t

KQ

tCycle

6.0

7.0

6.5

7.5

7.5

8.5

8.51010101115ns
ns

3.3 V

Curr (x18)
Curr (x36)
Curr (x72)

235
300
350

230
300
350

210
270
300

200
270
300

195
270
300

150
200
220

mA
mA
mA

2.5 V

Curr (x18)
Curr (x36)
Curr (x72)

235
300
340

230
300
340

210
270
300

200
270
300

195
270
300

145
190
220

mA
mA
mA

Rev: 1.00 10/2001 2/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832272B Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A

B DQG6 DQG2 BC BG NC BW A16 BB BF DQB2 DQB6 B

C DQG7 DQG3 BH BD NC E1 NC BE BA DQB3 DQB7 C

D DQG8 DQG4

V

SS

NC NC G GW NC

V

SS

DQB4 DQB8 D

E DQPG9 DQPC9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPF9 DQPB9 E

F DQC4 DQC8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

DQF8 DQF4 F

G DQC3 DQC7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

DQF7 DQF3 G

H DQC2 DQC6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQF6 DQF2 H

J DQC1 DQC5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

DQF5 DQF1 J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L DQH1 DQH5

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M DQH2 DQH6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N DQH3 DQH7

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P DQH4 DQH8

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R DQPD9 DQPH9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 DQPE9 R

T DQD8 DQD4

V

SS

NC NC LBO NC NC

V

SS

DQE4 DQE8 T

U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 DQE3 DQE7 U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 3/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832236C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 A

B NC NC BC NC A19 BW A16 BB NC DQB2 DQB6 B

C NC NC NC BD NC E1 NC NC BA DQB3 DQB7 C

D NC NC

V

SS

NC NC G GW NC

V

SS

DQB4 DQB8 D

E NC DQPC9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

NC DQPB9 E

F DQC4 DQC8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

NC NC F

G DQC3 DQC7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

NC NC G

H DQC2 DQC6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

NC NC H

J DQC1 DQC5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

NC NC J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L NC NC

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M NC NC

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N NC NC

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P NC NC

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R DQPD9 NC

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 NC R

T DQD8 DQD4

V

SS

NC NC LBO NC NC

V

SS

NC NC T

U DQD7 DQD3 NC A14 A13 A12 A11 A10 A18 NC NC U

V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 NC NC V

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 4/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218C Pad Out

209-Bump BGA—Top View

1 2 3 4 5 6 7 8 9 10 11

A NC NC A15 E2 ADSP ADSC ADV E3 A17 NC NC A

B NC NC BB NC A19 BW A16 NC NC NC NC B

C NC NC NC NC NC E1 A20 NC BA NC NC C

D NC NC

V

SS

NC NC G GW NC

V

SS

NC NC D

E NC DQPB9

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

NC NC E

F DQB4 DQB8

V

SS

V

SS

V

SS

ZQ

V

SS

V

SS

V

SS

NC NC F

G DQB3 DQB7

V

DDQ

V

DDQ

V

DD

MCH

V

DD

V

DDQ

V

DDQ

NC NC G

H DQB2 DQB6

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

NC NC H

J DQB1 DQB5

V

DDQ

V

DDQ

V

DD

MCL

V

DD

V

DDQ

V

DDQ

NC NC J

K NC NC CK NC

V

SS

MCL

V

SS

NC NC NC NC K

L NC NC

V

DDQ

V

DDQ

V

DD

FT

V

DD

V

DDQ

V

DDQ

DQA5 DQA1 L

M NC NC

V

SS

V

SS

V

SS

MCL

V

SS

V

SS

V

SS

DQA6 DQA2 M

N NC NC

V

DDQ

V

DDQ

V

DD

SCD

V

DD

V

DDQ

V

DDQ

DQA7 DQA3 N

P NC NC

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

DQA8 DQA4 P

R NC NC

V

DDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQPA9 NC R

T NC NC

V

SS

NC NC LBO NC NC

V

SS

NC NC T

U NC NC NC A14 A13 A12 A11 A10 A18 NC NC U

V NC NC A9 A8 A7 A1 A6 A5 A4 NC NC V

W NC NC TMS TDI A3 A0 A2 TDO TCK NC NC W

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

Rev: 1.00 10/2001 5/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

W6, V6 A0, A1 I Address field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,

U5, U4, A3, B7, A9, U9

An I Address Inputs

B5 A19 I Address Inputs (x36/x18 Versions)
C7 A20 I Address Inputs (x18 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9

I/O Data Input and Output pins (x72 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9

I/O Data Input and Output pins (x36 Version)

L11, M11, N11, P11, L10, M10, N10, P10, R10

J1, H1, G1, F1, J2, H2, G2, F2, E2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

C9, B8

BA, BB

I Byte Write Enable for DQA, DQB I/Os; active low

B3, C4

BC,BD

I

Byte Write Enable for DQC, DQD I/Os; active low

(x72/x36 Versions)

C8, B9, B4, C3

BE, BF, BG,BH

I

Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low

(x72 Version)
B5 NC — No Connect (x72 Version)
C7 NC — No Connect (x72/x36 Versions)

W10, V10, U10, T10, W11, V11, U11, T11, R11

J11, H11, G11, F11, J10, H10, G10, F10, E10

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,

B4, C3

NC — No Connect (x36/x18 Versions)

B3, C4 NC — No Connect (x18 Version)

C5, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11,

T4, T5, T7, T8, U3

NC — No Connect

K3 CK I Clock Input Signal; active high
D7

GW

I Global Write Enable—Writes all bytes; active low

C6

E1

I Chip Enable; active low

A8

E3

I Chip Enable; active low

A4

E2

I Chip Enable; active high

Rev: 1.00 10/2001 6/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

D6

G

I Output Enable; active low

A7

ADV

I Burst address counter advance enable; active low

A5, A6

ADSP, ADSC

I Address Strobe (Processor, Cache Controller); active low

P6

ZZ

I Sleep Mode control; active high

L6

FT

I Flow Through or Pipeline mode; active low

T6

LBO

I Linear Burst Order mode; active low

N6

SCD

I Single Cycle Deselect/Dual Cycle Deselect Mode Control

G6

MCH

I Must Connect High

H6, J6, K6, M6

MCL

Must Connect Low

B6

BW

I Byte Enable; active low

F6

ZQ

I

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

W3

TMS

I Scan Test Mode Select

W4

TDI

I Scan Test Data In

W8

TDO

O Scan Test Data Out

W9

TCK

I Scan Test Clock

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7

V

DD

I Core power supply

D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9

V

SS

I I/O and Core Ground

E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9

V

DDQ

I Output driver power supply

GS832218/36/72 209-Bump BGA Pin Description

Pin Location Symbol Type Description

Rev: 1.00 10/2001 7/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832236B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9

V

DDQ

A

B NC A18 A4 ADSC A15 A17 NC B

C NC A5 A3

V

DD

A14 A16 NC C

D DQC4 DQPC9

V

SS

ZQ

V

SS

DQPB9 DQB4 D

E DQC3 DQC8

V

SS

E1

V

SS

DQB8 DQB3 E

F

V

DDQ

DQC7

V

SS

G

V

SS

DQB7

V

DDQ

F

G DQC2 DQC6 BC ADV BB DQB6 DQB2 G

H DQC1 DQC5

V

SS

GW

V

SS

DQB5 DQB1 H

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

J

K DQD1 DQD5

V

SS

CK

V

SS

DQA5 DQA4 K

L DQD2 DQD6 BD SCD BA DQA6 DQA3 L

M

V

DDQ

DQD7

V

SS

BW

V

SS

DQA7

V

DDQ

M

N DQD3 DQD8

V

SS

A1

V

SS

DQA8 DQA2 N

P DQD4 DQPD9

V

SS

A0

V

SS

DQPA9 DQA1 P

R NC A2 LBO

V

DD

FT A13 NC R

T NC NC A10 A11 A12 A19 ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 8/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218B Pad Out

119-Bump BGA—Top View

1 2 3 4 5 6 7

A

V

DDQ

A6 A7 ADSP A8 A9

V

DDQ

A

B NC A18 A4 ADSC A15 A17 NC B

C NC A5 A3

V

DD

A14 A16 NC C

D DQB1 NC

V

SS

ZQ

V

SS

DQPA9 NC D

E NC DQB2

V

SS

E1

V

SS

NC DQA8 E

F

V

DDQ

NC

V

SS

G

V

SS

DQA7

V

DDQ

F

G NC DQB3 BB ADV NC NC DQA6 G

H DQB4 NC

V

SS

GW

V

SS

DQA5 NC H

J

V

DDQ

V

DD

NC

V

DD

NC

V

DD

V

DDQ

J

K NC DQB5

V

SS

CK

V

SS

NC DQA4 K

L DQB6 NC NC SCD BA DQA3 NC L

M

V

DDQ

DQB7

V

SS

BW

V

SS

NC

V

DDQ

M

N DQB8 NC

V

SS

A1

V

SS

DQA2 NC N

P NC DQPB9

V

SS

A0

V

SS

NC DQA1 P

R NC A2 LBO

V

DD

FT A13 NC R

T NC A10 A11 A20 A12 A19 ZZ T

U

V

DDQ

TMS TDI TCK TDO NC

V

DDQ

U

7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch

Rev: 1.00 10/2001 9/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs

R2, C3, B3, C2, A2, A3, A5, A6, T3,

T5, R6, C5, B5, C6, B6, B2

An I Address Inputs

T4, T6 An Address Input (x36 Version)

T2 NC — No Connect (x36 Version)

T2, T6, T4 An I Address Input (x18 Version)

K7, L7, N7, P7, K6, L6, M6, N6
H7, G7, E7, D7, H6, G6, F6, E6
H1, G1, E1, D1, H2, G2, F2, E2

K1, L1, N1, P1, K2, L2, M2, N2

DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8

I/O Data Input and Output pins. (x36 Version)

P6, D6, D2, P2

DQA9, DQB9,

DQC9, DQD9

I/O Data Input and Output pins. (x36 Version)

L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

DQA1–DQA9
DQB1–DQB9

I/O Data Input and Output pins (x18 Version)

L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version)

B1, C1, R1, T1, U6, B7, C7, J3, J5,

R7

NC — No Connect

P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3

NC — No Connect (x18 Version)

K4 CK I Clock Input Signal; active high
M4 BW I Byte Write—Writes all enabled bytes; active low
H4 GW I Global Write Enable—Writes all bytes; active low

E4 E1 I Chip Enable; active low

F4 G I Output Enable; active low
G4 ADV I Burst address counter advance enable; active low

A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low

T7 ZZ I Sleep mode control; active high
R5 FT I Flow Through or Pipeline mode; active low
R3 LBO I Linear Burst Order mode; active low

D4 ZQ I

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],

High = High Impedance [Low Drive])

L4 SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control
U2

TMS

I Scan Test Mode Select

Rev: 1.00 10/2001 10/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

U3

TDI

I Scan Test Data In

U5

TDO

O Scan Test Data Out

U4

TCK

I Scan Test Clock

J2, C4, J4, R4, J6

V

DD

I Core power supply

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

V

SS

I I/O and Core Ground

L4

V

SS

I I/O and Core Ground

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

V

DDQ

I Output driver power supply

GS832218/36 119-Bump BGA Pin Description

Pin Location Symbol Type Description

Rev: 1.00 10/2001 11/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS832218/36 (PE = 0) Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW

E1

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx9

NC

Parity

NC

Parity

Encode

Compare

36

4

36

36

4

32

Note: Only x36 version shown for simplicity.

SCD

36

36

D Q

Register

4

BA

BB

BC

BD

Rev: 1.00 10/2001 12/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

GS816218/36 (PE = 1) x32 Mode Block Diagram

A1

A0

A0

A1

D0
D1

Q1

Q0

Counter

Load

D Q

D Q

Register

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

DQ

Register

DQ

Register

A0–An

LBO
ADV

CK
ADSC

ADSP
GW

BW
BA

BB

BC

BD

E1

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

Q D

DQx0–DQx8

NC

Parity

NC

Parity

Encode

Compare

32

4

32

36

4

32

Note: Only x36 version shown for simplicity.

SCD

D Q

Register

D Q

Register

Parity

Encode

32

4

32

36

Rev: 1.00 10/2001 13/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the PE and ZZ pins, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

BPR 1999.05.18

Mode Pin Functions

Mode Name

Pin

Name

State Function

Burst Order Control LBO

L Linear Burst

H Interleaved Burst

Output Register Control FT

L Flow Through

H or NC Pipeline

Power Down Control ZZ

L or NC Active

H

Standby, IDD = I

SB

Single/Dual Cycle Deselect Control SCD

L Dual Cycle Deselect

H or NC Single Cycle Deselect

Parity Enable PE

L or NC Activate 9th I/O’s (x18/36 Mode)

H Deactivate 9th I/O’s (x16/32 Mode)

FLXDrive Output Impedance Control ZQ

L High Drive (Low Impedance)

H or NC Low Drive (High Impedance)

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

I

nterleaved Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Rev: 1.00 10/2001 14/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Rev: 1.00 10/2001 15/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Synchronous Truth Table

Operation Address Used

State

Diagram

Key

5

E1 ADSP ADSC ADV

W

3

DQ

4

Deselect Cycle, Power Down None X H X L X X High-Z

Read Cycle, Begin Burst External R L L X X X Q

Read Cycle, Begin Burst External R L H L X F Q

Write Cycle, Begin Burst External W L H L X T D

Read Cycle, Continue Burst Next CR X H H L F Q

Read Cycle, Continue Burst Next CR H X H L F Q

Write Cycle, Continue Burst Next CW X H H L T D

Write Cycle, Continue Burst Next CW H X H L T D
Read Cycle, Suspend Burst Current X H H H F Q
Read Cycle, Suspend Burst Current H X H H F Q
Write Cycle, Suspend Burst Current X H H H T D
Write Cycle, Suspend Burst Current H X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.00 10/2001 16/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W R

XX

X

Simple Synchronous OperationSimple Burst Synchronous Operation

CR

R

CW CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.

Rev: 1.00 10/2001 17/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CRCW

X

X

W R

R

W

R

X

X

X

CR

R

CW CR

CR

W

CW

W

CW

Simplified State Diagram with G

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.

Rev: 1.00 10/2001 18/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi­tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

Voltage on VDD Pins –0.5 to 4.6 V

V

DDQ

Voltage in V

DDQ

Pins –0.5 to 4.6 V

V

CK

Voltage on Clock Input Pin –0.5 to 6 V

V

I/O

Voltage on I/O Pins –0.5 to V

DDQ

+0.5 (≤ 4.6 V max.) V

V

IN

Voltage on Other Input Pins –0.5 to V

DD

+0.5 (≤ 4.6 V max.) V

I

IN

Input Current on Any Pin +/–20 mA

I

OUT

Output Current on Any I/O Pin +/–20 mA

P

D

Package Power Dissipation 1.5 W

T

STG

Storage Temperature –55 to 125

o

C

T

BIAS

Temperature Under Bias –55 to 125

o

C

Rev: 1.00 10/2001 19/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

3.3 V Supply Voltage

V

DD3

3.0 3.3 3.6 V

2.5 V Supply Voltage

V

DD2

2.3 2.5 2.7 V

3.3 V V

DDQ

I/O Supply Voltage V

DDQ3

3.0 3.3 3.6 V

2.5 V V

DDQ

I/O Supply Voltage V

DDQ2

2.4 2.5 2.7 V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

V

DDQ3

Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

IH

1.7 —

VDD + 0.3

V 1

V

DD

Input Low Voltage V

IL

–0.3 — 0.8 V 1

V

DDQ

I/O Input High Voltage V

IHQ

1.7 —

V

DDQ

+ 0.3

V 1,3

V

DDQ

I/O Input Low Voltage V

ILQ

–0.3 — 0.8 V 1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

V

DDQ2

Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

IH

0.6*V

DD

—

VDD + 0.3

V 1

V

DD

Input Low Voltage V

IL

–0.3 —

0.3*V

DD

V 1

V

DDQ

I/O Input High Voltage V

IHQ

0.6*V

DD

—

V

DDQ

+ 0.3

V 1,3

V

DDQ

I/O Input Low Voltage V

ILQ

–0.3 —

0.3*V

DD

V 1,3

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V

IHQ

(max) is voltage on V

DDQ

pins plus 0.3 V.

Rev: 1.00 10/2001 20/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Note: These parameters are sample tested.

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions)

T

A

0 25 70 °C 2

Ambient Temperature (Industrial Range Versions)

T

A

–40 25 85 °C 2

Note:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

C

IN

V

IN

= 0 V

4 5 pF

Input/Output Capacitance

C

I/O

V

OUT

= 0 V

6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single

R

ΘJA

40 °C/W 1,2

Junction to Ambient (at 200 lfm) four

R

ΘJA

24 °C/W 1,2

Junction to Case (TOP) —

R

ΘJC

9 °C/W 3

20% tKC

SS

– 2.0 V

50%

V

SS

V

IH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

V

DD

+ 2.0 V

50%

V

DD

V

IL

Rev: 1.00 10/2001 21/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

AC Test Conditions

Parameter Conditions

Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
Output load Fig. 1& 2
Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

OLZ

and t

OHZ

4. Device is deselected as defined by the Truth Table.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current
(except mode pins)

I

IL

V

IN

= 0 to V

DD

–1 uA 1 uA

ZZ and PE Input Current

I

IN1

V

DD ≥ VIN ≥ VIH

0 V ≤ V

IN

≤ V

IH

–1 uA
–1 uA

1 uA

100 uA

FT, SCD, ZQ Input Current

I

IN2

V

DD ≥ VIN ≥ VIL

0 V ≤ V

IN

≤ V

IL

–100 uA

–1 uA

1 uA
1 uA

Output Leakage Current

I

OL

Output Disable, V

OUT

= 0 to V

DD

–1 uA 1 uA

Output High Voltage

V

OH2

I

OH

= –8 mA, V

DDQ

= 2.375 V

1.7 V —

Output High Voltage

V

OH3

I

OH

= –8 mA, V

DDQ

= 3.135 V

2.4 V —

Output Low Voltage

V

OL

I

OL

= 8 mA

— 0.4 V

DQ

VT = 1.25 V

50Ω

30pF

*

DQ

2.5 V

Output Load 1

Output Load 2

225Ω

225Ω

5pF

*

* Distributed Test Jig Capacitance

Rev: 1.00 10/2001 22/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Operating Currents

Notes:

1. I

DD

and I

DDQ

apply to any combination of V

DD3

, V

DD2

, V

DDQ3

, and V

DDQ2

operation.

2. All parameters listed are worst case scenario.

Parameter Test Conditions Mode Symbol

-250 -225 -200 -166 -150 -133

Unit

0

to

70°C

–40

to

85°C

0

to

70°C

–40

to

85°C

0

to

70°C

–40

to

85°C

0

to

70°C

–40

to

85°C

0

to

70°C

–40

to

85°C

0

to

70°C

–40

to

85°C

Operating

Current

3.3 V

Device Selected;

All other inputs

≥V

IH

or ≤ V

IL

Output open

(x72)

Pipeline

I

DD

I

DDQ

580

80

560

80

530

70

550

70

480

60

500

60

410

50

430

50

380

50

400

50

340

40

360

40

mA

Flow

Through

I

DD

I

DDQ

310

40

330

40

340

40

330

40

270

30

290

30

270

30

290

30

270

30

290

30

200

20

220

20

mA

(x36)

Pipeline

I

DD

I

DDQ

520

40

540

40

470

40

490

40

430

30

450

30

370

30

390

30

340

30

360

30

310

20

330

20

mA

Flow

Through

I

DD

I

DDQ

280

20

300

20

280

20

300

20

250

20

270

20

350

20

270

20

250

20

270

20

180

20

200

20

mA

(x18)

Pipeline

I

DD

I

DDQ

345

20

360

20

315

20

330

20

290

15

305

15

250

15

265

15

230

15

245

15

205

10

220

10

mA

Flow

Through

I

DD

I

DDQ

200

10

215

10

200

10

215

10

175

10

190

10

175

10

190

10

175

10

190

10

135

10

150

10

mA

Operating

Current

2.5 V

Device Selected;

All other inputs

≥V

IH

or ≤ V

IL

Output open

(x72)

Pipeline

I

DD

I

DDQ

580

60

600

60

530

60

550

60

480

50

500

50

410

40

430

40

380

40

400

40

340

30

360

30

mA

Flow

Through

I

DD

I

DDQ

310

30

330

30

310

30

330

30

270

30

290

30

270

30

290

30

270

30

290

30

200

20

220

20

mA

(x36)

Pipeline

I

DD

I

DDQ

520

30

540

30

470

30

490

30

430

30

450

30

370

20

390

20

340

20

360

20

310

20

330

20

mA

Flow

Through

I

DD

I

DDQ

280

20

300

20

280

20

300

20

250

20

270

20

250

20

270

20

250

20

270

20

180

10

200

10

mA

(x18)

Pipeline

I

DD

I

DDQ

345

15

360

15

315

15

330

15

290

15

305

15

250

10

265

10

230

10

245

10

205

10

220

10

mA

Flow

Through

I

DD

I

DDQ

200

10

215

10

200

10

215

10

175

10

190

10

175

10

190

10

175

10

190

10

135

5

150

5

mA

Standby

Current

ZZ ≥ V

DD

– 0.2 V

—

Pipeline

I

SB

40 60 40 60 40 60 40 60 40 60 40 60

mA

Flow

Through

I

SB

40 60 40 60 40 60 40 60 40 60 40 60

mA

Deselect

Current

Device Deselected;

All other inputs

≥ V

IH

or ≤ V

IL

—

Pipeline

I

DD

170 180 160 170 150 160 130 140 120 130 100 110

mA

Flow

Through

I

DD

120 130 120 130 100 110 100 110 100 110 90 100

mA

Rev: 1.00 10/2001 23/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

AC Electrical Characteristics

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Parameter Symbol

-250 -225 -200 -166 -150 -133
Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns

Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.4 — 3.8 — 4.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Flow

Through

Clock Cycle Time tKC 7.0 — 7.5 — 8.5 — 10.0 — 10.0 — 15.0 — ns

Clock to Output Valid tKQ — 6.0 — 6.0 — 7.5 — 8.5 — 10.0 — 10.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns

Clock to Output in

High-Z

tHZ

1

1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns

G to output in Low-Z

tOLZ

1

0 — 0 — 0 — 0 — 0 — 0 — ns

G to output in High-Z

tOHZ

1

— 2.3 — 2.5 — 3.0 — 3.5 — 3.8 — 4.0 ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

tZZS

2

5 — 5 — 5 — 5 — 5 — 5 — ns

ZZ hold time

tZZH

2

1 — 1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 100 — 100 — 100 — 100 — 100 — 100 — ns

Rev: 1.00 10/2001 24/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

CK

ADSP

ADSC

ADV

GW

BW

WR2 WR3

WR1

WR1

WR2 WR3

tKC

Single Write

Burst Write

tKL

tKH

tS

tH

tS

tH

tS

tH

tS

tH

tS tH

tS

tH

tS

tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

ADV must be inactive for ADSP Write

ADSC initiated write

ADSP is blocked by E inactive

A0–An

BA–BD

DQA–DQD

Write

Deselected

WR1 WR2 WR3

Write Cycle Timing

E1

tS

tH

E1 only sampled with ADSP or ADSC

E1 masks ADSP

G

D2A D2B

D2C D2D D3A

D1A

Hi-Z

tS

tH

Rev: 1.00 10/2001 25/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Q1A

Q3A

Q2D

Q2cQ2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2 RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BA–BD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

Suspend Burst

Flow Through Read Cycle Timing

tH

E1 masks ADSP

E1

tS

Rev: 1.00 10/2001 26/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Flow Through Read-Write Cycle Timing

CK

ADSP

ADV

GW

BW

G

Q1A D1A

Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE

tOHZ

tS

tH

tS

tH

tH

tS

tH

tS tH

tKH

DQA–DQD

BA–BD

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Q2A

Burst wrap around to it’s initial state

WR1

E1

tS

E1 masks ADSP

tH

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS

tH

ADSC initiated read

Rev: 1.00 10/2001 27/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Pipelined SCD Read Cycle Timing

Q1A

Q3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

ADSC

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tS

tH

tH

tS

tH

tS

tH

ADSC initiated read

Suspend Burst

Single Read

ADSP is blocked by E inactive

A0–An

BWA–BWD

tKH

tKC

tS

tH

tS

tS

tH

DQA–DQD

RD1

Hi-Z

tH

E1 masks ADSP

E1

tS

Rev: 1.00 10/2001 28/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

CK

ADSP

ADV

GW

BW

G

Q1A

D1A Q2A

Q2B Q2c

Q2D

Single Read Burst Read

tOE tOHZ

tS

tH

tS tH

tH

tS tH

tS

tH

tKH

DQA–DQD

BWA– BWD

tKL

tKC

tS

Single Write

ADSP is blocked by E inactive

tKQ

tS

tH

Hi-Z

Pipelined SCD Read-Write Cycle Timing

WR1

E1

tS

E1 masks ADSP

tH

RD1

WR1

RD2

tS

tH

A0–An

ADSC

tS tH

ADSC initiated read

Rev: 1.00 10/2001 29/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Pipelined DCD Read Cycle Timing

Q1A

Q3A

Q2D

Q2c

Q2B

Q2A

tKQ

tLZ

tOE

tOHZ

tOLZ

tKQX

tHZ

tKQX

CK

ADSP

BW

G

GW

ADV

Burst Read

RD2

RD3

tKL

tH

tS

tH

tH

tS

tH

tS

tH

Suspend Burst

E1 masks ADSP

Single Read

ADSP is blocked by E1 inactive

A0–An

BA–BD

E1

tKH

tKC

tS

tS

tH

DQA–DQD

tS

RD1

Hi-Z

ADSC

tS

tH

ADSC initiated read

Rev: 1.00 10/2001 30/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Pipelined DCD Read-Write Cycle Timing

CK

ADSP

ADSC

ADV

GW

BW

E1

G

WR1

Q1A

D1A Q2A

Q2B Q2c

Q2D

Single Read

Burst Read

tOE tOHZ

tS

tS

tH

tS tH

tH

tS

tH

tS

tH

tS

tH

tKH

ADSC initiated read

E1 masks ADSP

DQA–DQD

tKL

tKC

tS

tH

Single Write

ADSP is blocked by E1 inactive

tKQ

tS

tH

Hi-Z

BA–BD

RD1 RD2

tS

tH

A0–An

WR1

Rev: 1.00 10/2001 31/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

CK

ADSP

ADSC

tH

tKH

tKL

tKC

tS

ZZ

tZZR

tZZH

tZZS

~

~

~

~

~

~

~

~

~

~

~

~

Snooze

Sleep Mode Timing Diagram

Rev: 1.00 10/2001 32/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.

TMS Test Mode Select In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.

TDO Test Data Out Out

Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.

Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Rev: 1.00 10/2001 33/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1
x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Instruction Register

ID Code Register

Boundary Scan Register

012

012

· · · ·

31 30 29

012

· · ·

· · ·· · ·

n

0

Bypass Register

TDI

TDO

TMS

TCK

Test Access Port (TAP) Controller

Rev: 1.00 10/2001 34/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc­tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle

0

0

1

0

1

1

0

0

1

1

1

0

0

1

1

0

0

0

0

1

1

0 0

1

1 0

0

0

1

1 1 1

Rev: 1.00 10/2001 35/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS832218(B/C)/GS832236(B/C)/GS832272(C)

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift­DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans­ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the
Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.

1

RFU 011

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.

1

GSI 101 GSI private instruction. 1

RFU 110

Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Rev: 1.00 10/2001 36/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

V

IHJ3

2.0

V

DD3

+0.3

V 1

3.3 V Test Port Input Low Voltage

V

ILJ3

–0.3 0.8 V 1

2.5 V Test Port Input High Voltage

V

IHJ2

0.6 * V

DD2

V

DD2

+0.3

V 1

2.5 V Test Port Input Low Voltage

V

ILJ2

–0.3

0.3 * V

DD2

V 1

TMS, TCK and TDI Input Leakage Current

I

INHJ

–300 1 uA 2

TMS, TCK and TDI Input Leakage Current

I

INLJ

–1 100 uA 3

TDO Output Leakage Current

I

OLJ

–1 1 uA 4

Test Port Output High Voltage

V

OHJ

1.7 — V 5, 6

Test Port Output Low Voltage

V

OLJ

— 0.4 V 5, 7

Test Port Output CMOS High

V

OHJC

V

DDQ

– 100 mV

— V 5, 8

Test Port Output CMOS Low

V

OLJC

— 100 mV V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

DDn

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. V

ILJ

≤ V

IN

≤ V

DDn

3. 0 V ≤ V

IN

≤ V

ILJn

4. Output Disable, V

OUT

= 0 to V

DDn

5. The TDO output driver is served by the V

DDQ

supply.

6. I

OHJ

= –4 mA

7. I

OLJ

= + 4 mA

8. I

OHJC

= –100 uA

9. I

OHJC

= +100 uA

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level 2.3 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level 1.25 V

Output reference level 1.25 V

DQ

VT = 1.25 V

50Ω

30pF

*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

Rev: 1.00 10/2001 37/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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JTAG Port Timing Diagram

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

tTKQ

tTS tTH

tTKH

tTKL

TCK

TMS

TDI

TDO

tTKC

Rev: 1.00 10/2001 38/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Notes:

1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,
PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1.

2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.

3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control
is effective after JTAG EXTEST instruction is executed.

4. 1 = no connect, internally set to logic value 1

5. 0 = no connect, internally set to logic value 0

6. X = no connect, value is undefined

GS832218/36/72 Boundary Scan Chain Order

Order x72 x36 x18

Bump

x72 x36 x18

TBD

Rev: 1.00 10/2001 39/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

209 BGA Package Drawing

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

Symbol Min Typ Max Units

A 1.70 mm

A1 0.40 0.50 0.60 mm

∅b 0.50 0.60 0.70 mm

c 0.31 0.36 0.38 mm

D 21.9 22.0 22.1 mm

D1 18.0 (BSC) mm

E 13.9 14.0 14.1 mm

E1 10.0 (BSC) mm

e 1.00 (BSC) mm

aaa 0.15 mm

Rev 1.0

A

A1

C

∅b

e

e

E

E1

D1

D

aaa

Bottom View

Side View

Rev: 1.00 10/2001 40/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Package Dimensions—119-Pin PBGA

A

B

Pin 1
Corner

K

E

F

C T

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

G

S

D

1234567

Package Dimensions—119-Pin PBGA

Unit: mm

Symbol Description Min. Nom. Max

A Width 13.9 14.0 14.1
B Length 21.9 22.0 22.1
C Package Height (including ball) 1.73 1.86 1.99
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70

F Package Height (excluding balls) 1.16 1.26 1.36
G Width between Balls 1.27
K Package Height above board 0.65 0.70 0.75
R Width of package between balls 7.62
S Length of package between balls 20.32

T Variance of Ball Height 0.15

Bottom View

R

Top View

Side View

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

119-Bump BGA Package

Rev: 1.00 10/2001 41/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

Ordering Information for GSI Synchronous Burst RAMs

Org

Part Number

1

Type Package

Speed

2

(MHz/ns)

T

A

3

2M x 18 GS832218B-250 DCD Pipeline/Flow Through 119 BGA 250/6 C
2M x 18 GS832218B-225 DCD Pipeline/Flow Through 119 BGA 225/6.5 C
2M x 18 GS832218B-200 DCD Pipeline/Flow Through 119 BGA 200/7.5 C
2M x 18 GS832218B-166 DCD Pipeline/Flow Through 119 BGA 166/8.5 C
2M x 18 GS832218B-150 DCD Pipeline/Flow Through 119 BGA 150/10 C
2M x 18 GS832218B-133 DCD Pipeline/Flow Through 119 BGA 133/11 C
2M x 18 GS832218C-250 DCD Pipeline/Flow Through 209 BGA 250/6 C
2M x 18 GS832218C-225 DCD Pipeline/Flow Through 209 BGA 225/6.5 C
2M x 18 GS832218C-200 DCD Pipeline/Flow Through 209 BGA 200/7.5 C
2M x 18 GS832218C-166 DCD Pipeline/Flow Through 209 BGA 166/8.5 C
2M x 18 GS832218C-150 DCD Pipeline/Flow Through 209 BGA 150/10 C
2M x 18 GS832218C-133 DCD Pipeline/Flow Through 209 BGA 133/11 C
1M x 36 GS832236B-250 SCD/DCD Pipeline/Flow Through 119 BGA 250/6 C
1M x 36 GS832236B-225 SCD/DCD Pipeline/Flow Through 119 BGA 225/6.5 C
1M x 36 GS832236B-200 SCD/DCD Pipeline/Flow Through 119 BGA 200/7.5 C
1M x 36 GS832236B-166 SCD/DCD Pipeline/Flow Through 119 BGA 166/8.5 C
1M x 36 GS832236B-150 SCD/DCD Pipeline/Flow Through 119 BGA 150/10 C
1M x 36 GS832236B-133 SCD/DCD Pipeline/Flow Through 119 BGA 133/11 C
1M x 36 GS832236C-250 SCD/DCD Pipeline/Flow Through 209 BGA 250/6 C
1M x 36 GS832236C-225 SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 C
1M x 36 GS832236C-200 SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 C
1M x 36 GS832236C-166 SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 C
1M x 36 GS832236C-150 SCD/DCD Pipeline/Flow Through 209 BGA 150/10 C

1M x 36 GS832236C-133 SCD/DCD Pipeline/Flow Through 209 BGA 133/11 C
512K x 72 GS832272C-250 SCD/DCD Pipeline/Flow Through 209 BGA 250/6 C
512K x 72 GS832272C-225 SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 C
512K x 72 GS832272C-200 SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 C
512K x 72 GS832272C-166 SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 C
512K x 72 GS832272C-150 SCD/DCD Pipeline/Flow Through 209 BGA 150/10 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.00 10/2001 42/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

512K x 72 GS832272C-133 SCD/DCD Pipeline/Flow Through 209 BGA 133/11 C

2M x 18 GS832218B-250I DCD Pipeline/Flow Through 119 BGA 250/6 I
2M x 18 GS832218B-225I DCD Pipeline/Flow Through 119 BGA 225/6.5 I
2M x 18 GS832218B-200I DCD Pipeline/Flow Through 119 BGA 200/7.5 I
2M x 18 GS832218B-166I DCD Pipeline/Flow Through 119 BGA 166/8.5 I
2M x 18 GS832218B-150I DCD Pipeline/Flow Through 119 BGA 150/10 I
2M x 18 GS832218B-133I DCD Pipeline/Flow Through 119 BGA 133/11 I
2M x 18 GS832218C-250I DCD Pipeline/Flow Through 209 BGA 250/6 I
2M x 18 GS832218C-225I DCD Pipeline/Flow Through 209 BGA 225/6.5 I
2M x 18 GS832218C-200I DCD Pipeline/Flow Through 209 BGA 200/7.5 I
2M x 18 GS832218C-166I DCD Pipeline/Flow Through 209 BGA 166/8.5 I
2M x 18 GS832218C-150I DCD Pipeline/Flow Through 209 BGA 150/10 I
2M x 18 GS832218C-133I DCD Pipeline/Flow Through 209 BGA 133/11 I
1M x 36 GS832236B-250I SCD/DCD Pipeline/Flow Through 119 BGA 250/6 I
1M x 36 GS832236B-225I SCD/DCD Pipeline/Flow Through 119 BGA 225/6.5 I
1M x 36 GS832236B-200I SCD/DCD Pipeline/Flow Through 119 BGA 200/7.5 I
1M x 36 GS832236B-166I SCD/DCD Pipeline/Flow Through 119 BGA 166/8.5 I
1M x 36 GS832236B-150I SCD/DCD Pipeline/Flow Through 119 BGA 150/10 I
1M x 36 GS832236B-133I SCD/DCD Pipeline/Flow Through 119 BGA 133/11 I
1M x 36 GS832236C-250I SCD/DCD Pipeline/Flow Through 209 BGA 250/6 I
1M x 36 GS832236C-225I SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 I
1M x 36 GS832236C-200I SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 I
1M x 36 GS832236C-166I SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 I
1M x 36 GS832236C-150I SCD/DCD Pipeline/Flow Through 209 BGA 150/10 I
1M x 36 GS832236C-133I SCD/DCD Pipeline/Flow Through 209 BGA 133/11 I

512K x 72 GS832272C-250I SCD/DCD Pipeline/Flow Through 209 BGA 250/6 I

Ordering Information for GSI Synchronous Burst RAMs (Continued)

Org

Part Number

1

Type Package

Speed

2

(MHz/ns)

T

A

3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.00 10/2001 43/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

512K x 72 GS832272C-225I SCD/DCD Pipeline/Flow Through 209 BGA 225/6.5 I
512K x 72 GS832272C-200I SCD/DCD Pipeline/Flow Through 209 BGA 200/7.5 I
512K x 72 GS832272C-166I SCD/DCD Pipeline/Flow Through 209 BGA 166/8.5 I
512K x 72 GS832272C-150I SCD/DCD Pipeline/Flow Through 209 BGA 150/10 I
512K x 72 GS832272C-133I SCD/DCD Pipeline/Flow Through 209 BGA 133/11 I

Ordering Information for GSI Synchronous Burst RAMs (Continued)

Org

Part Number

1

Type Package

Speed

2

(MHz/ns)

T

A

3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IB.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.00 10/2001 44/44 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS832218(B/C)/GS832236(B/C)/GS832272(C)

36M Sync SRAM Data Sheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes
Format or Content

Page;Revisions;Reason

832218_r1

• Creation of new datasheet