Datasheet GS8320Z36T-250I, GS8320Z36T-250, GS8320Z36T-225I, GS8320Z36T-225, GS8320Z36T-200I Datasheet (GSI)

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GS8320Z18/36T-250/225/200/166/150/133

100-Pin TQFP

36Mb Pipelined and Flow Through

Commercial Temp
Industrial Temp

Synchronous NBT SRAM

Features

• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

3.3 V

2.5 V
Flow

Through

2-1-1-1

3.3 V

2.5 V

t

KQ

tCycle

Curr (x18)

Curr (x32/x36)

Curr (x18)

Curr (x32/x36)

t

KQ

tCycle

Curr (x18)

Curr (x32/x36)

Curr (x18)

Curr (x32/x36)

2.3

2.5

3.0

3.5

3.8

4.0

4.0

4.4

5.0

6.0

6.6

7.5nsns

365

335

300

265

240

220

430

390

350

305

280

245mAmA

360

330

295

260

235

215

420

380

340

295

270

235mAmA

6.0

6.5

7.5

8.51010101115ns

7.0

7.5

8.5

200

200

180

180

180

135

230

230

195

195

195

145mAmA

200

200

180

180

180

130

225

225

195

195

195

145mAmA

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

ns

250 MHz–133 MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

Functional Description

The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off­chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.

The GS8320Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.

The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC­standard 100-pin TQFP package.

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Rev: 1.01 10/2001 1/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

A B C D E F

R W R W R W

Q

A

D

B

Q

A

Q

C

D

B

D

D

Q

C

Q

E

D

D

Q

E

GS8320Z18T Pinout

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

DD

A6

E1

A7

E2

NC

NC

E3

BB

BA

SS

V

V

CKE

W

G

CK

ADV

A8

A17

A18

A9

NC
NC
NC

V

DDQ

V

NC

NC
DQB1
DQB2

V

V

DDQ

DQB3
DQB4

V
V

V
DQB5
DQB6

V

DDQ

V
DQB7
DQB8

DQB9

NC

V

V

DDQ

NC
NC
NC

SS

SS

FT

DD

DD

SS

SS

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

2M x 18

Top View

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A20
NC
NC
V

DDQ

V

SS

NC
DQA9
DQA8
DQA7
V

SS

V

DDQ

DQA6
DQA5
V

SS

NC
V

DD

ZZ
DQA4
DQA3
V

DDQ

V

SS

DQA2
DQA1
NC
NC
V

SS

V

DDQ

NC
NC
NC

SS

A5

A4

A3

A2

A1

A0

NC

LBO

NC

DD

A19

NC

V

V

A11

A10

A12

A13

A14

A16

A15

Rev: 1.01 10/2001 2/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8320Z36T Pinout

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GS8320Z18/36T-250/225/200/166/150/133

DD

A6

E1

A7

E2

BC

BD

E3

BB

BA

SS

V

V

CKE

W

G

CK

ADV

A8

A17

A18

A9

DQC9
DQC8
DQC7

V

DDQ

V

SS

DQC6
DQC5
DQC4
DQC3

V

SS

V

DDQ

DQC2
DQC1

FT
V
V

DD

V

SS

DQD1
DQD2

V

DDQ

V

DQD3
DQD4
DQD5
DQD6

V

V

DDQ

DQD7
DQD8
DQD9

DD

SS

SS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1M x 36

Top View

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQB9
DQB8
DQB7
V

DDQ

V

SS

DQB6
DQB5
DQB4
DQB3
V

SS

V

DDQ

DQB2
DQB1
V

SS

NC
V

DD

ZZ
DQA1
DQA2
V

DDQ

V

SS

DQA3
DQA4
DQA5
DQA6
V

SS

V

DDQ

DQA7
DQA8
DQA9

SS

A5

A4

A3

A2

A1

A0

NC

LBO

NC

DD

NC

V

A19

V

A11

A10

A12

A13

A14

A16

A15

Rev: 1.01 10/2001 3/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

100-Pin TQFP Pin Descriptions

Pin Location Symbol Type Description

37, 36 A0, A1 In Burst Address Inputs; Preload the burst counter

35, 34, 33, 32, 100, 99, 82, 81,

44, 45, 46,47, 48, 49, 50, 83, 84, 43A2–A19 In Address Inputs

80 A20 In Address Input (x18 Version Only)
89 CK In Clock Input Signal
93 BA In Byte Write signal for data inputs DQA1-DQA9; active low
94 BB In Byte Write signal for data inputs DQB1-DQB9; active low
95 BC In Byte Write signal for data inputs DQC1-DQC9; active low (x36 Version Only)
96 BD In Byte Write signal for data inputs DQD1-DQD9; active low (x36 Version Only)
88 W In Write Enable; active low
98 E1 In Chip Enable; active low
97 E2 In Chip Enable; Active High. For self decoded depth expansion
92 E3 In Chip Enable; Active Low. For self decoded depth expansion
86 G In Output Enable; active low
85 ADV In Advance/Load; Burst address counter control pin
87 CKE In Clock Input Buffer Enable; active low

58, 59, 62,63, 68, 69, 72, 73, 74 DQA1–DQA9 I/O Byte A Data Input and Output pins (x18 Version Only)

8, 9, 12, 13, 18, 19, 22, 23, 24 DQB1–DQB9 I/O Byte B Data Input and Output pins (x18 Version Only)

51, 52, 53, 56, 57, 75, 78, 79,

1, 2, 3, 6, 7, 25, 28, 29, 30

63, 62, 59, 58, 57, 56, 53, 52, 51 DQA1–DQA9 I/O Byte A Data Input and Output pins (x36 Version Only)

68, 69, 72, 73, 74, 75,

78, 79, 80

13, 12, 9, 8, 7, 6, 3, 2, 1 DQC1–DQC9 I/O Byte C Data Input and Output pins (x36 Version Only)

18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1–DQD9 I/O Byte D Data Input and Output pins (x36 Version Only)

64 ZZ In Power down control; active high
14 FT In Pipeline/Flow Through Mode Control; active low
31 LBO In Linear Burst Order; active low

15, 16, 41, 65, 91

5,10, 17, 21, 26, 40, 55, 60, 67,

71, 76, 90

4, 11, 20, 27, 54, 61, 70, 77

38, 39, 42, 66 NC — No Connect

NC — No Connect (x18 Version Only)

DQB1–DQB9 I/O Byte B Data Input and Output pins (x36 Version Only)

V

V
V

DDQ

DD

SS

In Core power supply
In Ground
In Output driver power supply

Rev: 1.01 10/2001 4/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8320Z18/36 NBT SRAM Functional Block Diagram

A

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GS8320Z18/36T-250/225/200/166/150/133

DQa–DQn

FT

D Q

K

Sense Amps

Array

Memory

Write Drivers

Write Data

Write Data

K

Register 1

K

Register 2

FT

SA1’

SA0’

Burst

Counter

Register 2

Write Address

SA1

SA0

D Q

0–An

K

Register 1

Write Address

K

LBO

ADV

K K

Match

Read, Write and

W

BA

Control Logic

Data Coherency

K

BB

BC

E1

BD

CK

E3

E2

G

CKE

Rev: 1.01 10/2001 5/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8320Z18/36T-250/225/200/166/150/133

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.

Function W BA BB BC BD

Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.

Rev: 1.01 10/2001 6/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8320Z18/36T-250/225/200/166/150/133

Synchronous Truth Table

Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:

1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese­lect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.

3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.

4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low

6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.

7. Wait states can be inserted by setting CKE high.

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

Rev: 1.01 10/2001 7/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline and Flow Through Read Write Control State Diagram

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GS8320Z18/36T-250/225/200/166/150/133

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

W

D

R

R

Burst Read Burst Write

B

Key Notes:

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B and D represent input command

codes ,as indicated in the Synchronous Truth Table.

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram

Rev: 1.01 10/2001 8/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Data I/O State Diagram

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GS8320Z18/36T-250/225/200/166/150/133

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z
(Data In)

Input Command Code

Intermediate State (N+1)

R

D

Transition

Intermediate

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

Notes:

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒ ƒ ƒ

Intermediate

State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.01 10/2001 9/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Data I/O State Diagram

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GS8320Z18/36T-250/225/200/166/150/133

W

B

High Z
(Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not
shown because it prevents any state change.

2. W, R, B and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒ ƒ ƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.01 10/2001 10/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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Linear Burst Sequence

I

GS8320Z18/36T-250/225/200/166/150/133

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.

L Linear Burst
H Interleaved Burst
L Flow Through

H or NC Pipeline

L or NC Active

H

Standby, IDD = I

SB

Burst Counter Sequences

nterleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01
4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01
4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

BPR 1999.05.18

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.

Rev: 1.01 10/2001 11/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8320Z18/36T-250/225/200/166/150/133

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

ZZ

tZZS

Sleep

~

~

~

~

tZZR

tZZH

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal
found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or V

through parts. GSI NBT SRAMs are fully compatible with these sockets.

Pin 66, a No Connect (NC) on GSI’s GS8320Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8321Z18/36
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked VDD or V

on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode

applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT
SRAMs (GS8321Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active
low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.

on pipelined parts and VSS on flow

DDQ

DDQ

Rev: 1.01 10/2001 12/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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GS8320Z18/36T-250/225/200/166/150/133

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

DD

V

DDQ

V

CK

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi­tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

Voltage on VDD Pins –0.5 to 4.6 V

Voltage in V

Pins –0.5 to 4.6 V

DDQ

Voltage on Clock Input Pin –0.5 to 6 V

Voltage on I/O Pins –0.5 to V

Voltage on Other Input Pins –0.5 to V

+0.5 (≤ 4.6 V max.) V

DDQ

+0.5 (≤ 4.6 V max.) V

DD

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

o
o

C
C

Rev: 1.01 10/2001 13/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

V

DD3

V

DD2
DDQ3
DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.4 2.5 2.7 V

V

Range Logic Levels

DDQ3

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL
IHQ
ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

2.0 —

–0.3 — 0.8 V 1

1.7 —

–0.3 — 0.8 V 1,3

V

Range Logic Levels

DDQ2

VDD + 0.3

V

+ 0.3

DDQ

V 1

V 1,3

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

V

Input Low Voltage V

DD

V

I/O Input High Voltage V

DDQ

V

I/O Input Low Voltage V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL
IHQ
ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Rev: 1.01 10/2001 14/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

—

VDD + 0.3

0.3*V

V

+ 0.3

DDQ

0.3*V

DD

DD

V 1
V 1
V 1,3
V 1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Note:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

0 25 70 °C 2

–40 25 85 °C 2

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

SS

V

50%

– 2.0 V

IH

V

+ 2.0 V

DD

SS

20% tKC

50%

V

DD

V

IL

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance
Input/Output Capacitance

Note: These parameters are sample tested.

C

IN

C

I/O

V

V

OUT

IN

= 0 V

= 0 V

4 5 pF
6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four
Junction to Case (TOP) —

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Rev: 1.01 10/2001 15/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

R

ΘJA

R

ΘJA

R

ΘJC

40 °C/W 1,2
24 °C/W 1,2

9 °C/W 3

AC Test Conditions

Parameter Conditions

Input high level 2.3 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level 1.25 V
Output reference level 1.25 V
Output load Fig. 1& 2
Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

4. Device is deselected as defined by the Truth Table.

DQ

and t

OLZ

Output Load 1

OHZ

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Output Load 2

2.5 V

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current
(except mode pins)

ZZ and PE Input Current

FT, SCD, ZQ Input Current
Output Leakage Current

Output High Voltage
Output High Voltage
Output Low Voltage

50Ω

VT = 1.25 V

I

IL

I

IN1

I

IN2

I

OL

V

OH2

V

OH3

V

OL

*

30pF

* Distributed Test Jig Capacitance

V

IN

V

DD ≥ VIN ≥ VIH

0 V ≤ V
V

DD ≥ VIN ≥ VIL

0 V ≤ V

Output Disable, V

I

= –8 mA, V

OH

I

= –8 mA, V

OH

I

OL

= 0 to V

IN

IN

OUT
DDQ
DDQ

= 8 mA

DQ

DD

≤ V

IH

≤ V

IL

= 0 to V
= 2.375 V
= 3.135 V

5pF

DD

225Ω

*

225Ω

–1 uA 1 uA
–1 uA

–1 uA

–100 uA

–1 uA

1 uA

100 uA

1 uA
1 uA

–1 uA 1 uA

1.7 V —

2.4 V —
— 0.4 V

Rev: 1.01 10/2001 16/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Unit

to

–40

0

to

to

–40

0

to

to

–40

0

to

to

–40

0

to

to

–40

mA

230

85°C

220

70°C

260

85°C

250

70°C

280

85°C

270

70°C

320

85°C

310

70°C

355

85°C

mA

25

140

25

130

30

185

30

175

35

185

35

175

40

185

40

175

45

215

mA

15

215

15

205

20

230

20

220

20

255

20

245

20

290

20

280

25

320

mA

15

130

15

120

20

175

20

165

20

175

20

165

20

175

20

165

25

195

mA

15

230

15

220

15

260

15

250

15

280

15

270

15

320

15

310

15

355

mA

15

140

15

130

20

185

20

175

25

185

25

175

30

185

30

175

35

215

mA

15

215

15

205

20

230

20

220

20

255

20

245

20

290

20

280

20

320

mA

mA

10

10

15

15

15

15

15

15

20

10

130

10

120

15

175

15

165

15

175

15

165

15

175

15

165

15

195

mA

0

to

to

–40

-250 -225 -200 -166 -150 -133
0

to

45

345

70°C

50

390

85°C

50

380

70°C

25

205

25

215

25

205

25

310

25

350

25

340

15

185

15

195

15

185

35

345

40

390

40

380

20

205

20

215

20

205

20

310

20

350

20

340

15

185

15

195

15

25 35 25 35 25 35 25 35 25 35 25 35

185

25 35 25 35 25 35 25 35 25 35 25 35 mA

80 85 80 85 70 75 70 75 70 75 65 70 mA

115 120 110 115 105 110 100 105 95 100 90 95

operation.

DDQ2

, and V

SB

DD

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DD

I

DDQ

I

DDQ

I

SB

DD

I

I

DD

I

I

DDQ3

, V

DD2

, V

Flow

Pipeline

Through

(x36)

IL

Flow

Pipeline

Through

(x18)

Flow

Pipeline

Through

(x36)

IL

Flow

Pipeline

Through

(x18)

Flow

Pipeline

Through

—

Flow

Pipeline

Through

—

IL

DD3

– 0.2 V

or ≤ V

IH

≥V

Device Selected;

Output open

All other inputs

or ≤ V

IH

≥V

Device Selected;

Output open

All other inputs

DD

ZZ ≥ V

or ≤ V

IH

≥ V

All other inputs

Device Deselected;

apply to any combination of V

DDQ

and I

Operating Currents

Parameter Test Conditions Mode Symbol

Operating

Operating

3.3 V

Current

2.5 V

Current

Current

Standby

Current

Deselect

DD

Notes:

1. I

2. All parameters listed are worst case scenario.

Rev: 1.01 10/2001 17/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Electrical Characteristics

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Parameter Symbol

-250 -225 -200 -166 -150 -133

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns

Clock to Output Valid tKQ — 2.3 — 2.5 — 3.0 — 3.4 — 3.8 — 4.0 ns

Pipeline

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Clock Cycle Time tKC 7.0 — 7.5 — 8.5 — 10.0 — 10.0 — 15.0 — ns

Flow

Through

Clock to Output Valid tKQ — 6.0 — 6.0 — 7.5 — 8.5 — 10.0 — 10.0 ns

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns

Clock to Output in

High-Z

tHZ

1

1.5 2.3 1.5 2.5 1.5 3.0 1.5 3.5 1.5 3.8 1.5 4.0 ns

G to Output Valid tOE — 2.3 — 2.5 — 3.2 — 3.5 — 3.8 — 4.0 ns

G to output in Low-Z

G to output in High-Z

tOLZ

tOHZ

1

0 — 0 — 0 — 0 — 0 — 0 — ns

1

— 2.3 — 2.5 — 3.0 — 3.5 — 3.8 — 4.0 ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

ZZ setup time

ZZ hold time

tZZS
tZZH

2

5 — 5 — 5 — 5 — 5 — 5 — ns

2

1 — 1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 100 — 100 — 100 — 100 — 100 — 100 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Unit

Rev: 1.01 10/2001 18/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Read/Write Cycle Timing

1 2 3 4 5 6 7 8 9 10

CK

tH

CKE

E*

ADV

Bn

tS

tS

tS

tS

tS

tH

tH

tH

tH

tKHWtKL tKC

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

tS

tH

A0–An

DQA–DQD

A1

A2 A3

D(A1)

tS

D(A2)

tH

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

A4 A5 A6 A7

tKQLZ

(A2+1)

tKQ

D

tKQHZ

Q(A3)

Q(A4)

tGLQV

(A4+1)

tOEHZ

tOELZ

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE UNDEFINED

tKHQZ

Q

tKQX

Write
D(A7)

D(A5)

Q(A6)

DESELECT

Rev: 1.01 10/2001 19/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode No-Op, Stall and Deselect Timing

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

CK

CKE

E*

ADV

W

Bn

A0–An

1

tS

tS

tS

tS

tH

A1 A5

2

tH

tH

tH

A2 A3 A4

3

4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

Read
Q(A2)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

D(A1)

Q(A3)

Q(A2)

Write
D(A4)

STALL

Q(A3)

NOP

D(A4)

Read
Q(A5)

DESELECT

DON’T CARE UNDEFINED

Q(A5)

tKQHZ

CONTINUE
DESELECT

Rev: 1.01 10/2001 20/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Read/Write Cycle Timing

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

CK

CKE

E*

ADV

Bn

A0–An

DQ

1 2

tH

tS

tS

tS

tH

tS

tH

tS

tH

tS

3

tKHWtKL

tH

tH

4

5 6

7

tKC

A1 A2 A3 A4 A5 A6

D(A1)

D(A2)

tKQLZ

(A2+1)

tKQ

D

tKQHZ

Q(A3)

tGLQV

Q(A4)

tKHQZ

Q

(A4+1)

8

D(A5)

9

A7

Q(A6)

10

tS

tH

tOEHZ

tOELZ

tKQX

G

COMMAND

Write
D(A1)

Write
D(A2)

BURST
Write
D(A2+1)

Read
Q(A3)

Read
Q(A4)

BURST
Read
Q(A4+1)

Write
D(A5)

Read
Q(A6)

DON’T CARE

DESELECT

Write
D(A7)

UNDEFINED

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Rev: 1.01 10/2001 21/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode No-Op, Stall and Deselect Timing

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

CK

CKE

E*

ADV

W

Bn

A0–An

1 2

tH

tS

tH

tS

tH

tS

A1 A5A2 A3 A4

3

4

5 6

7

8

9

10

tKHQZ

DQ

COMMAND

Write
D(A1)

D(A1)

Read
Q(A2)

STALL Read

*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1

Q(A2)

Q(A3)

Write
D(A4)

Q(A3)

STALL

D(A4)

NOP

Read
Q(A5)

Q(A5)

tKQHZ

DESELECT

DON’T CARE UNDEFINED

CONTINUE
DESELECT

Rev: 1.01 10/2001 22/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Package Drawing

D

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 — 0.20

D Terminal Dimension 21.9 22.0 20.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75

L1 Lead Length — 1.00 —

Y Coplanarity — — 0.10
θ Lead Angle 0° — 7°

L1

A1

θ

L

c

Pin 1

e

D1

b

A2

Y

E1

E

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

BPR 1999.05.18

Rev: 1.01 10/2001 23/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information—GSI NBT Synchronous SRAM

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

Org

2M x 18 GS8320Z18T-250 NBT Pipeline/Flow Through TQFP 250/6 C
2M x 18 GS8320Z18T-225 NBT Pipeline/Flow Through TQFP 225/6.5 C
2M x 18 GS8320Z18T-200 NBT Pipeline/Flow Through TQFP 200/7.5 C
2M x 18 GS8320Z18T-166 NBT Pipeline/Flow Through TQFP 166/8.5 C
2M x 18 GS8320Z18T-150 NBT Pipeline/Flow Through TQFP 150/10 C
2M x 18 GS8320Z18T-133 NBT Pipeline/Flow Through TQFP 133/11 C
1M x 36 GS8320Z36T-250 NBT Pipeline/Flow Through TQFP 250/6 C
1M x 36 GS8320Z36T-225 NBT Pipeline/Flow Through TQFP 225/6.5 C
1M x 36 GS8320Z36T-200 NBT Pipeline/Flow Through TQFP 200/7.5 C
1M x 36 GS8320Z36T-166 NBT Pipeline/Flow Through TQFP 166/8.5 C
1M x 36 GS8320Z36T-150 NBT Pipeline/Flow Through TQFP 150/10 C
1M x 36 GS8320Z36T-133 NBT Pipeline/Flow Through TQFP 133/11 C
2M x 18 GS8320Z18T-250I NBT Pipeline/Flow Through TQFP 250/6 I Not Available
2M x 18 GS8320Z18T-225I NBT Pipeline/Flow Through TQFP 225/6.5 I Not Available
2M x 18 GS8320Z18T-200I NBT Pipeline/Flow Through TQFP 200/7.5 I Not Available
2M x 18 GS8320Z18T-166I NBT Pipeline/Flow Through TQFP 166/8.5 I
2M x 18 GS8320Z18T-150I NBT Pipeline/Flow Through TQFP 150/10 I
2M x 18 GS8320Z18T-133I NBT Pipeline/Flow Through TQFP 133/11 I
1M x 36 GS8320Z36T-250I NBT Pipeline/Flow Through TQFP 250/6 I Not Available
1M x 36 GS8320Z36T-225I NBT Pipeline/Flow Through TQFP 225/6.5 I Not Available
1M x 36 GS8320Z36T-200I NBT Pipeline/Flow Through TQFP 200/7.5 I Not Available
1M x 36 GS8320Z36T-166I NBT Pipeline/Flow Through TQFP 166/8.5 I
1M x 36 GS8320Z36T-150I NBT Pipeline/Flow Through TQFP 150/10 I
1M x 36 GS8320Z36T-133I NBT Pipeline/Flow Through TQFP 133/11 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings

Part Number

1

Type Package

Speed

(MHz/ns)

2

3

T

A

Status

Rev: 1.01 10/2001 24/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

36Mb Sync SRAM Datasheet Revision History

Product Preview

GS8320Z18/36T-250/225/200/166/150/133

DS/DateRev. Code: Old;

New

8320Z18_r1

8320Z18_r1; 8320Z18_r1_01 Content

Types of Changes

Format or Content

Page;Revisions;Reason

• Creation of new datasheet

• Corrected pinouts—moved A19 from pin 39 to pin 43; changed pin 39
to NC

Rev: 1.01 10/2001 25/25 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.