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GS8320E36GT-225I
Datasheet (GSI TECHNOLOGY)
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Datasheet GS8320E18T-250, GS8320E18T-225, GS8320E18T-200, GS8320E18T-166, GS8320E18T-150 Datasheet (GSI TECHNOLOGY)

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Page 1
查询GS8320E18GT-133供应商
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
2M x 18, 1M x 32, 1M x 36
Commercial Temp Industrial Temp
36Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO
pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
) and/or Global Write (GW) operation
Functional Description
Applications
The GS8320E18/32/36T is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1 control inputs (ADSP (Bx
, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP Burst mode, subsequent burst addresses are generated internally and are controlled by ADV counter may be configured to count in either linear or
, ADSC, ADV), and write control inputs
, E2, E3), address burst
)
or ADSC inputs. In
. The burst address
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
interleave order with the Linear Burst Order (LBO Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising­edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8320E18/32/36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW
) input combined with one or more individual byte write signals (Bx writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8320E18/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
mode pin (Pin 14). Holding the FT mode
). In addition, Global Write (GW) is available for
) pins are used to decouple output noise
DDQ
) input. The
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
t
KQ
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.01 10/2004 1/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
tCycle
Curr
Curr (x32/x36)
t
KQ
tCycle
Curr
Curr (x32/x36)
(x18)
(x18)
2.5
4.0
285 350
6.5
6.5
205 235
2.7
4.4
265 320
7.0
7.0
195 225
3.0
5.0
245 295
7.5
7.5
185 210
3.5
6.0
220 260
8.0
8.0
175 200
3.8
6.6
210 240
8.5
8.5
165 190
4.0
7.5nsns
185 215mAmA
8.5
8.5nsns
155 175mAmA
Page 2
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E18 100-Pin TQFP Pinout
Preliminary
NC NC NC
V
DDQ
V
SS
NC
NC DQB DQB V
SS
V
DDQ
DQB DQB
FT
V
DD
NC
V
SS
DQB DQB
V
DDQ
V
SS
DQB DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
B
B
BA
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2 3
4
5
6 7
8
9
10
11 12
13
14
15 16
17
18
19 20
21
22
23
24 25
26
27
28 29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
2M x 18
CK
GW
BW
ADSC
ADV
ADSP
80 79
78 77
76
75 74
73
72 71
70 69
68
67 66
65
64 63
62 61
60
59 58
57
56 55
54 53
52
51
A NC NC V
DDQ
V
SS
NC DQPA DQA DQA V
SS
V
DDQ
DQA DQA V
SS
NC V
DD
ZZ DQ
A
DQA V
DDQ
V
SS
DQA DQA NC NC V
SS
V
DDQ
NC NC NC
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
A
V
V
A A A A A
A
A
Rev: 1.01 10/2004 2/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 3
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E32 100-Pin TQFP Pinout
Preliminary
NC DQC DQ
V
DDQ
V
SS
DQC DQ DQC DQC
V
V
DDQ
DQC DQC
FT
V
DD
NC V
SS
DQD DQD
V
DDQ
V
DQD3
DQD DQD DQD
V
V
DDQ
DQD DQD
NC
SS
SS
SS
1
A
A
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6 7
8
9
10
11 12
13
14
15 16
17
18
19 20
21
22
23
24 25
26
27
28 29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
Top View
DD
E3
SS
V
V
1M x 32
CK
GW
BW
ADSC
ADV
ADSP
80 79
78 77
76
75 74
73
72 71
70 69
68
67 66
65
64 63
62 61
60
59 58
57
56 55
54 53
52
51
NC DQB DQ V
DDQ
V
SS
DQB DQB DQB DQB V
SS
V
DDQ
DQB DQB V
SS
NC V
DD
ZZ DQ DQA V
DDQ
V
SS
DQA DQA DQA DQA V
SS
V
DDQ
DQA DQA NC
B
A
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
V
V
A
A A A A A
A
A
Rev: 1.01 10/2004 3/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 4
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E36 100-Pin TQFP Pinout
Preliminary
DQPC
DQC DQC
V
DDQ
V
SS
DQC DQC DQC DQC
V
SS
V
DDQ
DQC DQC
FT
V
DD
NC V
SS
DQD DQD
V
DDQ
V
SS
DQD3
DQD DQD DQD
V
SS
V
DDQ
DQD DQD
DQPD
1
A
A
10099989796959493929190898887868584838281
1
2 3
4
5
6 7
8
9
10
11 12
13
14
15 16
17
18
19 20
21
22
23
24 25
26
27
28 29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D
E
E2
BB
BA
BC
B
Top View
DD
E3
SS
V
V
1M x 32
CK
GW
BW
ADSC
ADV
ADSP
80 79
78 77
76
75 74
73
72 71
70 69
68
67 66
65
64 63
62 61
60
59 58
57
56 55
54 53
52
51
DQPB DQB DQB V
DDQ
V
SS
DQB DQB DQB DQB V
SS
V
DDQ
DQB DQB V
SS
NC V
DD
ZZ DQ
A
DQA V
DDQ
V
SS
DQA DQA DQA DQA V
SS
V
DDQ
DQA DQA DQPA
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
A
DD
A
V
V
A
A A A A A
A
A
Rev: 1.01 10/2004 4/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 5
GS8320E18/32/36T-250/225/200/166/150/133
TQFP Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQ
A
DQB1
DQC DQD
NC No Connect
I/O Data Input and Output pins
Preliminary
BW
B
A, BB I Byte Write Enable for DQA, DQB Data I/Os; active low
B
C, BD I Byte Write Enable for DQC, DQD Data I/Os; active low
IByte Write—Writes all enabled bytes; active low
CK I Clock Input Signal; active high
GW
E
1, E3 I Chip Enable; active low
E
2 I Chip Enable; active high
G
ADV
ADSP
, ADSC I Address Strobe (Processor, Cache Controller); active low
I Global Write Enable—Writes all bytes; active low
I Output Enable; active low
I Burst address counter advance enable; active low
ZZ I Sleep Mode control; active high
FT
LBO
V
V
V
DDQ
DD
SS
I Flow Through or Pipeline mode; active low
I Linear Burst Order mode; active low
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.01 10/2004 5/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 6
GS8320E18/32/36T-250/225/200/166/150/133
GS8320E18/32/36 Block Diagram
Preliminary
A0–An
LBO
ADV
CK
ADSC ADSP
GW BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1 E2 E3
FT
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.01 10/2004 6/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 7
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Note:
There is a pull-up device on the FT the default states as specified in the above tables.
Burst Counter Sequences
pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
Standby, I
DD
= I
SB
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 10/2004 7/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 8
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read HLHHHH1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytesHLLLLL2, 3, 4
Write all bytesLXXXXX
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “
C” and “D” are only available on the x32 and x36 versions.
A, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
Rev: 1.01 10/2004 8/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 9
Synchronous Truth Table
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Operation
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Address
Used
Diagram
5
Key
E1
E
2
ADSP ADSC ADV
W
3
DQ
State
4
Write Cycle, Suspend Burst Current H X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G
is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP
7. Tying ADSP
2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 10/2004 9/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 10
GS8320E18/32/36T-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
WR
Preliminary
Simple Synchronous OperationSimple Burst Synchronous Operation
W
X
First Write
WR
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G
2. The upper portion of the diagram assumes active use of only the Enable (E1 that ADSP
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC assumes ADSP
Rev: 1.01 10/2004 10/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
is tied high and ADSC is tied low.
is tied high and ADV is tied low.
) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
is tied low.
control inputs, and
Page 11
GS8320E18/32/36T-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
WR
Preliminary
W
X
X
First Write
W
Burst Write
CW CR
R
CR
R
CR
W
CW
W
CW
R
First Read
R
Burst Read
X
CRCW
X
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G
2. Use of “Dummy Reads” (Read Cycles with G through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G Data Input Set Up Time.
Rev: 1.01 10/2004 11/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
High) may be used to make the transition from Read cycles to Write cycles without passing
has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
.
Page 12
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
V
DD
V
DDQ
V
I/O
V
IN
I
IN
I
OUT
P
D
T
STG
T
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Voltage on VDD Pins
Voltage in V
DDQ
Pins
Voltage on I/O Pins
Voltage on Other Input Pins
–0.5 to V
–0.5 to V
–0.5 to 4.6 V
–0.5 to 4.6 V
+0.5 (≤ 4.6 V max.)
DDQ
+0.5 (≤ 4.6 V max.)
DD
V
V
Input Current on Any Pin +/–20 mA
Output Current on Any I/O Pin +/–20 mA
Package Power Dissipation 1.5 W
Storage Temperature –55 to 125
Temperature Under Bias –55 to 125
o
o
C
C
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage
2.5 V Supply Voltage
3.3 V V
2.5 V V
I/O Supply Voltage V
DDQ
I/O Supply Voltage V
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
V
DD3
V
DD2
DDQ3
DDQ2
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
3.0 3.3 3.6 V
2.3 2.5 2.7 V
3.0 3.3 3.6 V
2.3 2.5 2.7 V
Rev: 1.01 10/2004 12/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 13
V
Range Logic Levels
DDQ3
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Parameter Symbol Min. Typ. Max. Unit Notes
V
V
DDQ
DD
+ 0.3
+ 0.3
V1
V1,3
VDD Input High Voltage V
Input Low Voltage V
V
DD
I/O Input High Voltage V
V
DDQ
I/O Input Low Voltage V
V
DDQ
IH
IL
IHQ
ILQ
2.0 —
–0.3 — 0.8 V 1
2.0 —
–0.3 — 0.8 V 1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
V
Range Logic Levels
DDQ2
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
Input Low Voltage V
V
DD
V
I/O Input High Voltage V
DDQ
I/O Input Low Voltage V
V
DDQ
IH
IL
IHQ
ILQ
0.6*V
DD
–0.3 —
0.6*V
DD
–0.3 —
—
—
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
V
0.3*V
V
DDQ
0.3*V
DD
+ 0.3
DD
+ 0.3
DD
V1
V1
V1,3
V1,3
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica­tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
Rev: 1.01 10/2004 13/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
T
A
T
A
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
DDn
02570°C2
–40 25 85 °C2
Page 14
GS8320E18/32/36T-250/225/200/166/150/133
Undershoot Measurement and Timing Overshoot Measurement and Timing
V
IH
V
+ 2.0 V
DD
V
SS
50%
20% tKC
Preliminary
50%
– 2.0 V
SS
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, V
DD
= 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance
Input/Output Capacitance
Note:
These parameters are sample tested.
C
IN
C
I/O
AC Test Conditions
Parameter Conditions
V
Input high level
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level
Output reference level
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DQ
– 0.2 V
DD
V
/2
DDQ
V
/2
DDQ
Output Load 1
V
V
OUT
IN
= 0 V
= 0 V
V
DD
V
IL
45pF
67pF
30pF
*
V
DDQ/2
50Ω
* Distributed Test Jig Capacitance
Rev: 1.01 10/2004 14/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 15
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins)
ZZInput Current
FT
Input Current
Output Leakage Current (x36/x72)
Output Leakage Current (x18)
Output High Voltage
Output High Voltage
Output Low Voltage
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
I
IL
I
IN1
I
IN2
I
OL
I
OL
V
OH2
V
OH3
V
OL
Output Disable, V
Output Disable, V
I
= –8 mA, V
OH
I
= –8 mA, V
OH
V
= 0 to V
IN
V
DD ≥ VIN ≥ VIH
0 V ≤ V
V 0 V ≤ V
IN
DD ≥ VIN ≥ VIL
IN
OUT
OUT
DDQ
DDQ
I
= 8 mA
OL
DD
≤ V
IH
≤ V
IL
= 0 to V
= 0 to V
= 2.375 V
= 3.135 V
DD
DD
–2 uA 2 uA
–1 uA –1 uA
–100 uA
–1 uA
1 uA
100 uA
1 uA 1 uA
–1 uA 1 uA
–1 uA 1 uA
1.7 V —
2.4 V —
— 0.4 V
Rev: 1.01 10/2004 15/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 16
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
–40
0
–40
0
–40
0
–40
0
–40
85°C
70°C
85°C
70°C
85°C
70°C
85°C
70°C
85°C
mA
210
190
230
210
245
225
275
255
295
Unit
to
to
to
to
to
to
to
to
to
25
25
30
30
35
35
40
40
45
170
160
180
170
190
180
200
190
210
mA
15
15
20
20
20
20
20
20
25
190
170
210
190
220
200
245
225
260
mA
15
15
20
20
20
20
20
20
25
150
140
160
150
170
160
180
170
190
mA
15
15
15
15
15
15
15
15
15
mA
mA
mA
mA
0
to
70°C
to
–40
85°C
-250 -225 -200 -166 -150 -133 0
to
70°C
Operating Currents
Parameter Test Conditions Mode Symbol
275
320
300
DD
I
Pipeline
45
50
50
DDQ
I
(x32/
200
220
210
DD
I
Flow
x36)
25
25
25
DDQ
I
Through
Device Selected;
All other inputs
Operating
240
280
260
DD
I
Pipeline
IL
or ≤ V
IH
≥V
Output open
Current
25
25
25
DDQ
I
I
(x18)
180
200
190
DD
Flow
15
15
60 80 60 80 60 80 60 80 60 80 60 80
15
I
DDQ
I
Pipeline
Through
SB
—
– 0.2 V
ZZ ≥ V
Standby
60 80 60 80 60 80 60 80 60 80 60 80
SB
I
Flow
DD
Current
100 115 95 110 90 105 85 100 85 100 80 95
DD
I
Pipeline
Through
Device Deselected;
—
All other inputs
Deselect
85 100 85 100 80 95 80 95 75 90 70 85
DD
I
Flow
Through
IL
or ≤ V
IH
≥ V
Current
operation.
DDQ2
, and V
DDQ3
, V
DD2
, V
DD3
apply to any combination of V
DDQ
and I
DD
Notes:
1. I
2. All parameters listed are worst case scenario.
Rev: 1.01 10/2004 16/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 17
AC Electrical Characteristics
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Pipeline
Flow
Through
Parameter Symbol
-250 -225 -200 -166 -150 -133
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns
Clock to Output Valid tKQ — 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns
Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
1
Clock to Output in Low-Z
tLZ
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Setup time tS 1.2 — 1.3 — 1.4 — 1.5 — 1.5 — 1.5 — ns
Hold time tH 0.2 — 0.3 — 0.4 — 0.5 — 0.5 — 0.5 — ns
Clock Cycle Time tKC 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 — ns
Clock to Output Valid tKQ — 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 ns
Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Clock to Output in Low-Z
tLZ
1
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns
Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns
Unit
Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns
Clock to Output in
High-Z
G
to Output Valid tOE — 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns
to output in Low-Z
G
to output in High-Z
G
ZZ setup time
ZZ hold time
tHZ
tOLZ
tOHZ
tZZS
tZZH
1
1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns
1
0 — 0 — 0 — 0 — 0 — 0 — ns
1
— 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns
2
5 — 5 — 5 — 5 — 5 — 5 — ns
2
1 — 1 — 1 — 1 — 1 — 1 — ns
ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.01 10/2004 17/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 18
GS8320E18/32/36T-250/225/200/166/150/133
Pipeline Mode Timing (DCD)
Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2Read C+3 Cont Deselect Deselect
tKLtKL
tKCtKC
ADSC initiated read
tHtS
tH
tS
CK
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
tKHtKH
tS
tH
tHtS
tS
tH
ABC
tS
tS
tS
tH
tS
tH
tH
E2 and E3 only sampled with ADSC
Preliminary
Deselected with E1
G
tHZ
tKQX
DQa–DQd
Hi-Z
tOHZtOE
tS
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
tKQ
tLZtH
Rev: 1.01 10/2004 18/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 19
GS8320E18/32/36T-250/225/200/166/150/133
Flow Through Mode Timing (DCD)
Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tKLtKL
tKHtKH
CK
tKCtKC
Preliminary
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
Fixed High
tS
tH
tH
tS
tS
tH
ABC
tS
tH
tS
tS
tH
tS
tH
tH
E2 and E3 only sampled with ADSP and ADSC
tS
tH
ADSC initiated read
tS
tH
tH
tS
E1 masks ADSP
E1 masks ADSP
tHtS
Deselected with E1
G
DQa–DQd
tOE
tKQ
tH
tS
tOHZ
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tLZ
tKQX
tHZ
Rev: 1.01 10/2004 19/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 20
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKHtKH
tKCtKC
CK
Setup
Hold
ADSP
ADSC
ZZ
tKLtKL
tZZR
tZZHtZZS
Rev: 1.01 10/2004 20/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 21
TQFP Package Drawing (Package T)
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 — 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length — 1.00 —
Y Coplanarity 0.10
θ Lead Angle 0° — 7°
L1
A1
θ
L
c
Pin 1
D1
D
e
b
A2
Y
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.01 10/2004 21/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 22
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Org
2M x 18 GS8320E18T-250 Pipeline/Flow Through TQFP 250/6.5 C
2M x 18 GS8320E18T-225 Pipeline/Flow Through TQFP 225/7 C
2M x 18 GS8320E18T-200 Pipeline/Flow Through TQFP 200/7.5 C
2M x 18 GS8320E18T-166 Pipeline/Flow Through TQFP 166/8 C
2M x 18 GS8320E18T-150 Pipeline/Flow Through TQFP 150/8.5 C
2M x 18 GS8320E18T-133 Pipeline/Flow Through TQFP 133/8.5 C
1M x 32 GS8320E32T-250 Pipeline/Flow Through TQFP 250/6.5 C
1M x 32 GS8320E32T-225 Pipeline/Flow Through TQFP 225/7 C
1M x 32 GS8320E32T-200 Pipeline/Flow Through TQFP 200/7.5 C
1M x 32 GS8320E32T-166 Pipeline/Flow Through TQFP 166/8 C
1M x 32 GS8320E32T-150 Pipeline/Flow Through TQFP 150/8.5 C
1M x 32 GS8320E32T-133 Pipeline/Flow Through TQFP 133/8.5 C
1M x 36 GS8320E36T-250 Pipeline/Flow Through TQFP 250/6.5 C
1M x 36 GS8320E36T-225 Pipeline/Flow Through TQFP 225/7 C
1M x 36 GS8320E36T-200 Pipeline/Flow Through TQFP 200/7.5 C
1M x 36 GS8320E36T-166 Pipeline/Flow Through TQFP 166/8 C
1M x 36 GS8320E36T-150 Pipeline/Flow Through TQFP 150/8.5 C
1M x 36 GS8320E36T-133 Pipeline/Flow Through TQFP 133/8.5 C
2M x 18 GS8320E18T-250I Pipeline/Flow Through TQFP 250/6.5 I
2M x 18 GS8320E18T-225I Pipeline/Flow Through TQFP 225/7 I
2M x 18 GS8320E18T-200I Pipeline/Flow Through TQFP 200/7.5 I
2M x 18 GS8320E18T-166I Pipeline/Flow Through TQFP 166/8 I
2M x 18 GS8320E18T-150I Pipeline/Flow Through TQFP 150/8.5 I
2M x 18 GS8320E18T-133I Pipeline/Flow Through TQFP 133/8.5 I
1M x 32 GS8320E32T-250I Pipeline/Flow Through TQFP 250/6.5 I
1M x 32 GS8320E32T-225I Pipeline/Flow Through TQFP 225/7 I
1M x 32 GS8320E32T-200I Pipeline/Flow Through TQFP 200/7.5 I
1M x 32 GS8320E32T-166I Pipeline/Flow Through TQFP 166/8 I
1M x 32 GS8320E32T-150I Pipeline/Flow Through TQFP 150/8.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings.
Speed
(MHz/ns)
3
T
A
Status
Rev: 1.01 10/2004 22/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 23
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Org
1M x 32 GS8320E32T-133I Pipeline/Flow Through TQFP 133/8.5 I
1M x 36 GS8320E36T-250I Pipeline/Flow Through TQFP 250/6.5 I
1M x 36 GS8320E36T-225I Pipeline/Flow Through TQFP 225/7 I
1M x 36 GS8320E36T-200I Pipeline/Flow Through TQFP 200/7.5 I
1M x 36 GS8320E36T-166I Pipeline/Flow Through TQFP 166/8 I
1M x 36 GS8320E36T-150I Pipeline/Flow Through TQFP 150/8.5 I
1M x 36 GS8320E36T-133I Pipeline/Flow Through TQFP 133/8.5 I
2M x 18 GS8320E18GT-250 Pipeline/Flow Through Pb-free TQFP 250/6.5 C
2M x 18 GS8320E18GT-225 Pipeline/Flow Through Pb-free TQFP 225/7 C
2M x 18 GS8320E18GT-200 Pipeline/Flow Through Pb-free TQFP 200/7.5 C
2M x 18 GS8320E18GT-166 Pipeline/Flow Through Pb-free TQFP 166/8 C
2M x 18 GS8320E18GT-150 Pipeline/Flow Through Pb-free TQFP 150/8.5 C
2M x 18 GS8320E18GT-133 Pipeline/Flow Through Pb-free TQFP 133/8.5 C
1M x 32 GS8320E32GT-250 Pipeline/Flow Through Pb-free TQFP 250/6.5 C
1M x 32 GS8320E32GT-225 Pipeline/Flow Through Pb-free TQFP 225/7 C
1M x 32 GS8320E32GT-200 Pipeline/Flow Through Pb-free TQFP 200/7.5 C
1M x 32 GS8320E32GT-166 Pipeline/Flow Through Pb-free TQFP 166/8 C
1M x 32 GS8320E32GT-150 Pipeline/Flow Through Pb-free TQFP 150/8.5 C
1M x 32 GS8320E32GT-133 Pipeline/Flow Through Pb-free TQFP 133/8.5 C
1M x 36 GS8320E36GT-250 Pipeline/Flow Through Pb-free TQFP 250/6.5 C
1M x 36 GS8320E36GT-225 Pipeline/Flow Through Pb-free TQFP 225/7 C
1M x 36 GS8320E36GT-200 Pipeline/Flow Through Pb-free TQFP 200/7.5 C
1M x 36 GS8320E36GT-166 Pipeline/Flow Through Pb-free TQFP 166/8 C
1M x 36 GS8320E36GT-150 Pipeline/Flow Through Pb-free TQFP 150/8.5 C
1M x 36 GS8320E36GT-133 Pipeline/Flow Through Pb-free TQFP 133/8.5 C
2M x 18 GS8320E18GT-250I Pipeline/Flow Through Pb-free TQFP 250/6.5 I
2M x 18 GS8320E18GT-225I Pipeline/Flow Through Pb-free TQFP 225/7 I
2M x 18 GS8320E18GT-200I Pipeline/Flow Through Pb-free TQFP 200/7.5 I
2M x 18 GS8320E18GT-166I Pipeline/Flow Through Pb-free TQFP 166/8 I
2M x 18 GS8320E18GT-150I Pipeline/Flow Through Pb-free TQFP 150/8.5 I
2M x 18 GS8320E18GT-133I Pipeline/Flow Through Pb-free TQFP 133/8.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings.
Speed
(MHz/ns)
3
T
A
Status
Rev: 1.01 10/2004 23/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 24
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Org
1M x 32 GS8320E32GT-250I Pipeline/Flow Through Pb-free TQFP 250/6.5 I
1M x 32 GS8320E32GT-225I Pipeline/Flow Through Pb-free TQFP 225/7 I
1M x 32 GS8320E32GT-200I Pipeline/Flow Through Pb-free TQFP 200/7.5 I
1M x 32 GS8320E32GT-166I Pipeline/Flow Through Pb-free TQFP 166/8 I
1M x 32 GS8320E32GT-150I Pipeline/Flow Through Pb-free TQFP 150/8.5 I
1M x 32 GS8320E32GT-133I Pipeline/Flow Through Pb-free TQFP 133/8.5 I
1M x 36 GS8320E36GT-250I Pipeline/Flow Through Pb-free TQFP 250/6.5 I
1M x 36 GS8320E36GT-225I Pipeline/Flow Through Pb-free TQFP 225/7 I
1M x 36 GS8320E36GT-200I Pipeline/Flow Through Pb-free TQFP 200/7.5 I
1M x 36 GS8320E36GT-166I Pipeline/Flow Through Pb-free TQFP 166/8 I
1M x 36 GS8320E36GT-150I Pipeline/Flow Through Pb-free TQFP 150/8.5 I
1M x 36 GS8320E36GT-133I Pipeline/Flow Through Pb-free TQFP 133/8.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings.
Speed
(MHz/ns)
3
T
A
Status
Rev: 1.01 10/2004 24/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 25
36Mb Sync SRAM Datasheet Revision History
Preliminary
GS8320E18/32/36T-250/225/200/166/150/133
DS/DateRev. Code: Old;
New
8320E18_r1
8320
E18_r1;
8320E18_r1_01
Types of Changes Format or Content
Content/Format
Page;Revisions;Reason
• Creation of new datasheet
• Updated format
• Added Pb-free information for TQFP package
Rev: 1.01 10/2004 25/25 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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