Datasheet GS820E32T-6I, GS820E32T-6, GS820E32T-5I, GS820E32T-5, GS820E32T-4I Datasheet (GSI)

GS820E32T/Q-150/138/133/117/100/66

TQFP, QFP

64K x 32

Commercial Temp
Industrial Temp

2M Synchronous Burst SRAM

Features

• FT pin for user configurable flow through or pipelined operation.

• Dual Cycle Deselect (DCD) Operation.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or QFP package.

-150 -138 -133 -117 -100 -66

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

tCycle

tKQ
IDD

tCycle

tKQ
IDD

6.6ns

3.8ns

270mA

10.5ns
9ns

170mA

7.25ns
4ns

245mA

15ns

9.7ns

120mA

7.5ns
4ns

240mA

15ns
10ns

120mA

8.5ns

4.5

210mA

15ns
11ns

120mA

10ns

5ns

180mA

15ns
12ns

120mA

12.5ns
6ns

150mA

20ns
18ns

95mA

Functional Description

Applications

The GS820E32 is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.

Controls

Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.

150Mhz - 66Mhz

9ns - 18ns

3.3V VDD

3.3V & 2.5V I/O

Flow Through / Pipeline Reads

The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP­BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.

DCD Pipelined Reads

The GS820E32 is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.

Core and Interface Voltages

The GS820E32 operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ)
pins are used to de-couple output noise from the internal circuit.

Rev: 1.03 2/2000 1/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32 100 Pin TQFP and QFP Pinout

GS820E32T/Q-150/138/133/117/100/66

NC

DQC8
DQC7

VDDQ

VSS
DQC6
DQC5
DQC4
DQC3

VSS

VDDQ
DQC2
DQC1

FT
VDD
NC

VSS
DQD1
DQD2

VDDQ

VSS
DQD3
DQD4
DQD5
DQD6

VSS

VDDQ
DQD7
DQD8

NC

A6

E1

A7

E2

BC

BD

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

E3

BB

BA

64K x 32

Top View

VDD

VSS

BW

GW

CK

G

ADV

ADSP

ADSC

A8

A9

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC

A5

A4

A3

A2

A1

A0

NC

LBO

NC

NC

VSS

VDD

A11

NC

A10

A12

A13

NC

A14

A15

Rev: 1.03 2/2000 2/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

TQFP Pin Description

Pin Location Symbol Type Description

37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs

35, 34, 33, 32, 100, 99, 82, 81, 44, 45,

46, 47, 48, 49

52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79

2, 3, 6, 7, 8, 9, 12, 13

18, 19, 22, 23, 24, 25, 28, 29

16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 NC No Connect

87 BW I Byte Write. Writes all enabled bytes. Active Low.
93, 94 BA, BB I Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/O’s. Active Low.

89 CK I Clock Input Signal. Active High.

88 GW I Global Write Enable. Writes all bytes. Active Low.
98, 92 E1, E3 I Chip Enable. Active Low.

97 E2 I Chip Enable. Active High.

86 G I Output Enable. Active Low.

83 ADV I Burst address counter advance enable. Active Low.
84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low.

64 ZZ I Sleep Mode control. Active High.

14 FT I Flow Through or Pipeline mode. Active Low.

31 LBO I Linear Burst Order mode. Active Low.

15, 41, 65, 91 VDD I Core power supply.

5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground.

4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply.

A2-15 I Address Inputs

DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8

I/O Data Input and Output pins.

E

Rev: 1.03 2/2000 3/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E18/32/36 Block Diagram

A0-An

LBO

ADV
CK

ADSC
ADSP

GW

BW
BA

Register

D Q

A0

A1

D0
D1

Counter

Load

Register

D Q

Q0
Q1

GS820E32T/Q-150/138/133/117/100/66

A0
A1

A

Memory

Array

Q D

BB

BC

BD

E1
E2
E3

FT
G

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

Register

D Q

32

4

DQ

Register

32

Register

DQ

ZZ

Power Down

Control

0

DQx1-DQx8

Rev: 1.03 2/2000 4/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

Linear Burst Sequence

I

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.

Burst Counter Sequences

A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

L Linear Burst

H or NC Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

Standby, IDD = I

nterleaved Burst Sequence

1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

SB

A[1:0] A[1:0] A[1:0] A[1:0]

Byte Write Truth Table

Function GW BW BA BB BC BD Notes

Read H H X X X X 1

Read H L H H H H 1
Write byte A H L L H H H 2, 3
Write byte B H L H L H H 2, 3
Write byte C H L H H L H 2, 3, 4
Write byte D H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X

Note:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

Rev: 1.03 2/2000 5/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

Synchronous Truth Table

State

Operation Address Used

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D

Note:

1. X = Don’t Care, H = High, L = Low.

2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).

Diagram

5

Key

E1

2

E

ADSP ADSC ADV

W

3

DQ

4

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.03 2/2000 6/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

Simplified State Diagram

X

Deselect

W R

W

X

Simple Synchronous OperationSimple Burst Synchronous Operation

First Write

W R

Burst Write

CW CR

R

CR

R

CR

R

First Read

Burst Read

X

CRCW

XX

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.

Rev: 1.03 2/2000 7/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

Simplified State Diagram with G

GS820E32T/Q-150/138/133/117/100/66

X

Deselect

W R

W

X

First Write

W

X

Burst Write

CW CR

R

CR

R

CR

W

CW

W

CW

R

First Read

R

Burst Read

X

CRCW

X

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.

Rev: 1.03 2/2000 8/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

V

I

T

T

V

DDQ

V
V

V

I

OUT

P

STG

BIAS

DD

CK
I/O

IN

IN

D

Voltage on VDD Pins -0.5 to 4.6 V
Voltage in V

Pins -0.5 to V

DDQ

DD

V
Voltage on Clock Input Pin -0.5 to 6 V
Voltage on I/O Pins -0.5 to V

+0.5 (≤ 4.6 V max.) V

DDQ

Voltage on Other Input Pins -0.5 to VDD+0.5 (≤ 4.6 V max.) V
Input Current on Any Pin +/- 20 mA
Output Current on Any I/O Pin +/- 20 mA
Package Power Dissipation 1.5 W
Storage Temperature -55 to 125
Temperature Under Bias -55 to 125

o
o

C
C

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.

Recommended Operating Conditions

Parameter Symbol Min. Typ. Max. Unit Notes

V

V

DDQ

V

V

T
T

DD

IH
IL
A
A

3.135 3.3 3.6 V

2.375 2.5

1.7 ---

V

DD

VDD+0.3

V 1
V 2

-0.3 --- 0.8 V 2
0 25 70 °C 3

-40 25 85 °C 3

Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)

Note:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.

2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.

3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.

4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.

Rev: 1.03 2/2000 9/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

IH

VDD+-2.0V

V

SS

50%

20% tKC

50%

VSS-2.0V

20% tKC

V

DD

V

IL

Capacitance

(TA=25oC, f=1MHZ, VDD=3.3V)

Parameter Symbol Test conditions Typ. Max. Unit

Control Input Capacitance
Input Capacitance
Output Capacitance

Note: This parameter is sample tested.

C

C

C

OUT

I

IN

VDD=3.3V

VIN=0V

V

=0V

OUT

3 4 pF
4 5 pF
6 7 pF

Package Thermal Characteristics

Rating Layer Board Symbol TQFP Max QFP Max Unit Notes

Junction to Ambient (at 200 lfm) single
Junction to Ambient (at 200 lfm) four
Junction to Case (TOP)

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper­ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87.

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.

R
R
R

ΘJA
ΘJA
ΘJC

40 TBD °C/W 1,2,4
24 TBD °C/W 1,2,4

9 TBD °C/W 3,4

Rev: 1.03 2/2000 10/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

AC Test Conditions

Parameter Conditions

Input high level 2.3V
Input low level 0.2V
Input slew rate 1V/ns
Input reference level 1.25V
Output reference level 1.25V
Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, t

4. Device is deselected as defined by the Truth Table.

DQ

and t

OLZ

Output Load 1

OHZ

.

Output Load 2

2.5V

50Ω

30pF

VT=1.25V

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current
(except mode pins)

ZZ Input Current

Mode Pin Input Current

Output Leakage Current
Output High Voltage

Output High Voltage
Output Low Voltage

I

INZZ

I

INM

I

V
V

V

I

IL

OL

OH
OH

OL

V

V

DD ≥ VIN ≥ VIH

0V ≤ V

V

DD ≥ VIN ≥ VIL

0V ≤ V

Output Disable,

V

OUT

I

= - 4mA, V

OH

I

= - 4mA, V

OH

= 0 to V

IN

= 0 to V

I

OL

≤ V

IN

≤ V

IN

DDQ
DDQ

= 4mA

DD

IH

IL

DD

=2.375V
=3.135V

*

-1uA 1uA

-1uA

-1uA

300uA

-300uA

-1uA

-1uA 1uA

1.7V

2.4V

1uA

1uA
1uA

0.4V

DQ

5pF

225Ω

*

225Ω

Rev: 1.03 2/2000 11/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

Operating Currents

Parameter Test Conditions Symbol

Device Selected;

Operating

Current

All other inputs

≥VIH or ≤ VIL

Output open

IDD

Pipeline

IDD

Flow-Thru

GS820E32T/Q-150/138/133/117/100/66

-150 -138 -133

0 to 70°C -40 to

85°C

270mA 275mA 245mA 250mA 240mA 245mA

170mA 175mA 120mA 125mA 120mA 125mA

0 to 70°C -40 to

85°C

0 to 70°C -40 to

85°C

Standby

ZZ ≥ VDD - 0.2V

Current

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

Operating Currents

Parameter Test Conditions Symbol

Device Selected;

Operating

Current

Standby

All other inputs

≥VIH or ≤ VIL

Output open

ZZ ≥ VDD - 0.2V

Current

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

ISB

Flow-Thru

IDD

Pipeline

IDD

Flow-Thru

IDD

Pipeline

IDD

Flow-Thru

ISB

Flow-Thru

IDD

Pipeline

IDD

Flow-Thru

10mA 15mA 10mA 15mA 10mA 15mA

90mA 95mA 80mA 85mA 80mA 85mA

45mA 50mA 40mA 45mA 40mA 45mA

-117 -100 -66

0 to 70°C -40 to

85°C

210mA 215mA 180mA 185mA 150mA 155mA

120mA 125mA 120mA 125mA 95mA 100mA

10mA 15mA 10mA 15mA 10mA 15mA

70mA 75mA 60mA 65mA 50mA 55mA

40mA 45mA 40mA 45mA 40mA 45mA

0 to 70°C -40 to

85°C

0 to 70°C -40 to

85°C

Rev: 1.03 2/2000 12/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

AC Electrical Characteristics

GS820E32T/Q-150/138/133/117/100/66

Pipeline

Flow-

Thru

Parameter Symbol

Clock Cycle Time tKC 6.6 --- 7.25 --- 7.5 --- 8.5 --- 10 12.5 ns

Clock to Output Valid tKQ --- 3.8 --- 4 --- 4 --- 4.5 5 6 ns

Clock to Output Invalid tKQX 1.5 --- 2 --- 2 --- 2 --- 2 2 ns

Clock to Output in Low-Z

Clock Cycle Time tKC 10.5 --- 15 --- 15 --- 15 --- 15 20 ns

Clock to Output Valid tKQ --- 9.0 --- 9.7 --- 10 --- 11 12 18 ns

Clock to Output Invalid tKQX 3 --- 3 --- 3 --- 3 --- 3 3 ns

Clock to Output in Low-Z

Clock HIGH Time tKH 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns

Clock LOW Time tKL 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns

Clock to Output in High-Z

G to Output Valid tOE --- 3.8 --- 4 --- 4 --- 4 5 6 ns

G to output in Low-Z

G to output in High-Z

Setup time tS 1.7 --- 2 --- 2 --- 2 --- 2 2 ns

Hold time tH 0.5 --- 0.5 --- 0.5 --- 0.5 --- 0.5 0.5 ns

ZZ setup time

ZZ hold time

ZZ recovery tZZR 20 --- 20 --- 20 --- 20 --- 20 20 ns

tLZ

tLZ

tHZ

tOLZ
tOHZ

tZZS

tZZH

1

1

1

1

1

2
2

-150 -138 -133 -117 -100 -66

Min Max Min Max Min Max Min Max Min Max Min Max

1.5 --- 2 --- 2 --- 2 --- 2 2 ns

3 --- 3 --- 3 --- 3 --- 3 3 ns

1.5 3.8 1.5 4 1.5 4 1.5 4 5 6 ns

0 --- 0 --- 0 --- 0 --- 0 0 ns

--- 4 --- 4 --- 4 --- 4 5 6 ns

5 --- 5 --- 5 --- 5 --- 5 5 ns
1 --- 1 --- 1 --- 1 --- 1 1 ns

Unit

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.

Rev: 1.03 2/2000 13/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

Write Cycle Timing

GS820E32T/Q-150/138/133/117/100/66

CK

ADSP

ADSC

ADV

A0-An

GW

BW

BA - BD

Single Write

tH

tS

tH

tS

WR1

tS

tH

Burst Write

ADSP is blocked by E1 inactive

tKC

tKL

tKH

tS tH

tH

tS

ADV must be inactive for ADSP Write

WR2 WR3

tS tH

tH

tS

tS

tH

WR1 WR2 WR3

WR1

WR2 WR3

E1 masks ADSP

Write

ADSC initiated write

Deselected

E1

tH

tS

Deselected with E2

E2

tS tH

E2 and E3 only sampled with ADSP or ADSC

E3

G

tS

tH

DQA - DQD

Hi-Z

D1A

Rev: 1.03 2/2000 14/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

Write specified byte for 2A and all bytes for 2B, 2C& 2D

D2A D2B

D2C D2D D3A

GS820E32T/Q-150/138/133/117/100/66

Flow Through Read Cycle Timing

CK

ADSP

ADSC

ADV

A0-An

GW

BW

BA - BD

Single Read

tS

tH

tS

tS

tH

RD1

tS

tS

tH

tS

tKL

tKH

tS

tH

tH

RD2 RD3

Burst Read

ADSP is blocked by E1 inactive

tKC

Suspend Burst

E1 masks ADSP

ADSC initiated read

Suspend Burst

tH

tH

E1

tH

tS

E2 and E3 only sampled with ADSP or ADSC

Deselected with E2

E2

tS

tH

E3

tOE

tOHZ

G

DQA-DQD

tOLZ

Hi-Z

Q1A

tLZ

tKQ

Q2A

tKQX

Q2CQ2B

Q2D

Rev: 1.03 2/2000 15/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

tKQX

Q3A

tHZ

GS820E32T/Q-150/138/133/117/100/66

Flow Through Read-Write Cycle Timing

CK

ADSP

ADSC

ADV

A0-An

GW

BW

BA - BD

E1

E2

E3

tKL

Single Write

tKC

tH

Single Read

tH

tS

tS tH

tS

tH

RD1 WR1

tS

tH

tS

tS

tH

tH

tS

tH

tS

tOE

tOHZ

tKH

E2 and E3 only sampled with ADSP and ADSC

tS

tS

WR1

ADSP is blocked by E inactive

tH

ADSC initiated read

RD2

tH

Burst Read

E1 masks ADSP

Deselected with E3

G

DQA - DQD

Hi-Z

Rev: 1.03 2/2000 16/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

tKQ

tS

Q1A D1A

tH

Q2A

Burst wrap around to it’s initial state

Q2B Q2C

Q2D

Q2A

GS820E32T/Q-150/138/133/117/100/66

Pipelined DCD Read Cycle Timing

CK

ADSP

ADSC

ADV

A0-An

GW

BW

BA - BD

E1

Single Read

tH

tS

tS

tH

RD1

tH

tS

tH

tS

Burst Read

tKL

ADSP is blocked by E1 inactive

tKH

tS

tH

tS

tH

RD2

tS

tS

E2 and E3 only sampled with ADSP or ADSC

tKC

Suspend Burst

E1 masks ADSP

ADSC initiated read

RD3

tH

tH

E2

tS

tH

Deselected with E2

E3

tOE

G

tOHZ

Q1a

DQA-DQD

Hi-Z

tOLZ

tLZ

tKQ

Rev: 1.03 2/2000 17/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

tKQX

tKQX

Q2BQ2A

Q2C

Q2D

Q3A

tHZ

GS820E32T/Q-150/138/133/117/100/66

Pipelined DCD Read-Write Cycle Timing

CK

ADSP

ADSC

ADV

A0-An

GW

BW

BA - BD

E1

Single Read

tS

tH

tS

tH

tS

tH

RD1 WR1

tS

tH

tS

tS

tH

tS tH

tKH

E2 and E3 only sampled with ADSP and ADSC

Single Write

tKL

tKC

tH

tS tH

tH

tS

WR1

Burst Read

ADSP is blocked by E1 inactive

ADSC initiated read

RD2

E1 masks ADSP

E2

tS

tH

Deselected with E3

E3

tOE tOHZ

G

tS

DQA - DQD

Hi-Z

tKQ

Q1A

Rev: 1.03 2/2000 18/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

tH

D1A Q2A

Q2B Q2C

Q2D

GS820E32T/Q-150/138/133/117/100/66

Sleep Mode Timing Diagram

~

CK

ADSP

ADSC

ZZ

tS

tH

tKC

tKH

tKL

tZZS

~

~

~

~

~

~

~

~

~

~

~

Snooze

tZZH

tZZR

Application Tips

Single and Dual Cycle Deselect

SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.

Rev: 1.03 2/2000 19/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS 820E32 Output Driver Characteristics

I Out (mA)

VDDQ

60

Pull Down Drivers

40

20

0

GS820E32T/Q-150/138/133/117/100/66

I Out

VOut

VSS

-20

-40

Pull Up Drivers

-60

-80

-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
V Out (Pull Down)

VDDQ - V Out (Pull Up)

3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD

E

Rev: 1.03 2/2000 20/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

TQFPand QFP Package Drawing

θ

L

L1

e

b

c

GS820E32T/Q-150/138/133/117/100/66

Pin 1

D1

D

A1

A2

Y

E1

E

TQFP QFP

Symbol Description Min. Nom. Max Min. Nom. Max

A1 Standoff 0.05 0.10 0.15 0.25 0.35 0.45
A2 Body Thickness 1.35 1.40 1.45 2.55 2.72 2.90

b Lead Width 0.20 0.30 0.40 0.20 0.30 0.40
c Lead Thickness 0.09 0.20 0.10 0.15 0.20

D Terminal Dimension 21.9 22.0 22.1 22.95 23.2 23.45

D1 Package Body 19.9 20.0 20.1 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1 17.0 17.2 17.4

E1 Package Body 13.9 14.0 14.1 13.9 14.0 14.1

e Lead Pitch 0.65 0.65
L Foot Length 0.45 0.60 0.75 .60 0.80 1.00

L1 Lead Length 1.00 1.60

Y Coplanarity 0.10 0.10
θ Lead Angle 0° 7° 0° 7°

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion

Rev: 1.03 2/2000 21/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

GS820E32T/Q-150/138/133/117/100/66

2

Org

Part Number

1

Type Package

(Mhz/

ns)

64K x 32 GS820E32T-150 Pipeline/Flow Through TQFP 150/9 C
64K x 32 GS820E32T-138 Pipeline/Flow Through TQFP 138/9.7 C
64K x 32 GS820E32T-133 Pipeline/Flow Through TQFP 133/10 C
64K x 32 GS820E32T-4 Pipeline/Flow Through TQFP 117/11 C
64K x 32 GS820E32T-5 Pipeline/Flow Through TQFP 100/12 C
64K x 32 GS820E32T-6 Pipeline/Flow Through TQFP 66/18 C
64K x 32 GS820E32T-150I Pipeline/Flow Through TQFP 150/9 I Not Available
64K x 32 GS820E32T-138I Pipeline/Flow Through TQFP 138/9.7 I
64K x 32 GS820E32T-133I Pipeline/Flow Through TQFP 133/10 I
64K x 32 GS820E32T-4I Pipeline/Flow Through TQFP 117/11 I
64K x 32 GS820E32T-5I Pipeline/Flow Through TQFP 100/12 I
64K x 32 GS820E32T-6I Pipeline/Flow Through TQFP 66/18 I
64K x 32 GS820E32Q-150 Pipeline/Flow Through QFP 150/9 C
64K x 32 GS820E32Q-138 Pipeline/Flow Through QFP 138/9.7 C
64K x 32 GS820E32Q-133 Pipeline/Flow Through QFP 133/10 C
64K x 32 GS820E32Q-4 Pipeline/Flow Through QFP 117/11 C
64K x 32 GS820E32Q-5 Pipeline/Flow Through QFP 100/12 C
64K x 32 GS820E32Q-6 Pipeline/Flow Through QFP 66/18 C
64K x 32 GS820E32Q-150I Pipeline/Flow Through QFP 150/9 I Not Available
64K x 32 GS820E32Q-138I Pipeline/Flow Through QFP 138/9.7 I
64K x 32 GS820E32Q-133I Pipeline/Flow Through QFP 133/10 I
64K x 32 GS820E32Q-4I Pipeline/Flow Through QFP 117/11 I
64K x 32 GS820E32Q-5I Pipeline/Flow Through QFP 100/12 I
64K x 32 GS820E32Q-6I Pipeline/Flow Through QFP 66/18 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820E32T-100IT.

2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.

Speed

T

A

3

Status

Rev: 1.03 2/2000 22/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D

Revision History

GS820E32T/Q-150/138/133/117/100/66

DS/DateRev. Code: Old;

New

GSGS820E3218/36 Rev 1.00 9/

1999A

GSGS820E3218/36 Rev 1.00 9/

1999A; 1.01 11/1999B

GSGS820E3218/36 Rev 1.01

11/1999B; 1.02 1/2000C

GS820E3218/361.02 1/

2000C;820E3218/361.03 2/

2000D

Types of Changes
Format or Content

Format

Content

Content

Format/Content

Revisions

• This was the first release of 2 Meg Burst Datasheets in the new format.
They included information for the Fine Pitch BGA package.

• Took out the Fine Pitch BGA information.

• Ordering information. Changed 128K x 32 to 64K x 32; Typo

• Ordering information. Changed “0” to go before “H” or “E” in part number.

• Ordering information. Changed - 117 to -4, -100 to -5. and -66 to -6.

• New GSI Logo

• Switched TKQ with TCycle in Flow Through part of table on page 1.

Rev: 1.03 2/2000 23/23 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D