Datasheet GS8162Z72C-133I, GS8162Z72C-133, GS8162Z36D-250I, GS8162Z36D-250, GS8162Z36D-225I Datasheet (GSI)

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

119, 165, & 209 BGA

18Mb Pipelined and Flow Through

Commercial Temp Industrial Temp

Synchronous NBT SRAM

Features

• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• On-chip parity encoding and error detection

• LBO

pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165-, or 209-Bump BGA package

/low output drive

250 MHz–133 MHz

2.5 V or 3.3 V V

DD

2.5 V or 3.3 V I/O

read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

) must be tied to a power

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

3.3 V

2.5 V

Flow

Through

2-1-1-1

3.3 V

2.5 V

t

KQ

tCycle

Curr (x18) Curr (x36) Curr (x72)

t

KQ

tCycle

Curr (x18) Curr (x36) Curr (x72)

2.5

4.0

280 330

n/a

275 320

n/a

5.5

175 200

n/a

175 200

n/a

2.7

4.4

255 300

n/a

250 295

n/a

6.0

165 190

n/a

165 190

n/a

3.0

5.0

230 270 350

230 265 335

6.5

160 180 225

3.4

6.0

200 230 300

195 225 290

7.0

150 170 115

3.8

6.7

185 215 270

180 210 260

7.5

145 165 210

4.0

7.5nsns

165

mA

190

mA

245

mA

165

mA

185

mA

235

mA

8.5

8.5nsns

135

mA

150

mA

185

mA

135

mA

150

mA

185

mA

Functional Description

The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package.

Because it is a synchronous device, address, data inputs, and

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

GS8162Z72 Pad Out

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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

209-Bump BGA—Top View (Package C)

A DQG5 DQG1 A13 E2 A14 ADV A15 E

B DQG6 DQG2 B

C DQG7 DQG3 B

D DQG8 DQG4 V

E DQG9 DQC9 V

F DQC4 DQC8 V

G DQC3 DQC7 V

H DQC2 DQC6 V

J DQC1 DQC5 V

K NC NC CK NC V

L DQH1 DQH5 V

M DQH2 DQH6 V

N DQH3 DQH7 V

P DQH4 DQH8 V

CBGNC WA16 BBBF DQB2 DQB6

HBDNCE1NCBEBA DQB3 DQB7

SS

DDQ

SS

DDQ

SS

DDQ

SS

DDQ

SS

NC NC G NC NC V

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

DDQ

V

SS

V

DDQ

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

SS

V

DD

V

SS

V

DD

V

SS

V

DD

ZQ V

MCH V

MCL V

MCH V

MCL V

FT V

MCL V

MCH V

ZZ V

V

DD

SS

DD

SS

DD

SS

DD

SS

DD

SS

V

3 A17 DQB1 DQB5

SS

DDQ

V

SS

DDQ

V

SS

DDQ

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

DQB4 DQB8

DQF9 DQB9

DQF8 DQF4

DQF7 DQF3

DQF6 DQF2

DQF5 DQF1

NC NC NC NC

DDQ

V

SS

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

DQA5 DQA1

DQA6 DQA2

DQA7 DQA3

DQA8 DQA4

R DQD9 DQH9 V

T DQD8 DQD4 V

DDQ

SS

V

DDQ

NC NC LBO PE NC V

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

SS

DQA9 DQE9

DQE4 DQE8

U DQD7 DQD3 NC A12 NC A11 NC A10 NC DQE3 DQE7

VDQD6DQD2A9A8A7A1A6A5A4DQE2DQE6

W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5

Rev 10

11 x 19 Bump BGA—14 x 22 mm

2

Body—1 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

GS8162Z72 BGA Pin Description

Symbol Type Description

1

A0, A

An I Address Inputs

DQ

A1

A9

–DQ

B

B9

C9

D9

E9

F9

G9

H9

G,BH

DQB1–DQ DQC1–DQ DQD1–DQ DQE1–DQ DQF1–DQ DQG1–DQ DQH1–DQ

B

A, BB, BC,BD, BE, BF,

NC — No Connect

CK I Clock Input Signal; active high

W

E

1, E3

E

2

G

ZZ

FT

LBO

MCH

MCL

PE

BW

ZQ

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Address field LSBs and Address Counter Preset Inputs

I/O Data Input and Output pins

I

Byte Write Enable for DQ

DQ

F

, DQG, DQH I/Os; active low

I Write Enable. Writes all enabled bytes; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Sleep Mode control; active high

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

I Must Connect High

Must Connect Low

I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

I Byte Enable; active low

I

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

FLXDrive Output Impedance Control

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

A

, DQB, DQC, DQ

D, DQE

,

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

165 Bump BGA—x18 Commom I/O—Top View (Package D)

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ANC

BNC

CNCNC

DNC

ENC

FNC

GNC

HFT

J

K

L

DQB NC V

A6 E1 BB NC E3

A7 E2 NC BA CK W G A18 A9 NC B

V

DQB V

MCH NC

DDQ

CKE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

ADV A17 A8

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDQ

NC DQA C

NC DQA D

NC DQA E

NC DQA F

NC DQA G

NC ZQ ZZ H

V

DDQ

DQA NC J

DQA NC K

DQA NC L

A19

A

M

N

DQB NC V

DQB DNU V

PNCNC

RLBO

NC A3 A2 TMS A0 TCK A10 A13 A15 A16 R

DDQ

A5 A4 TDI A1 TDO A11 A12 A14 NC P

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

DDQ

DQA NC M

NC NC N

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

165 Bump BGA—x36 Common I/O—Top View (Package D)

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ANC

BNC

C

D

E

F

G

HFT

J

K

L

DQC NC V

DQC DQC V

MCH NC

DQD DQD V

A6 E1 BC BB E3 CKE ADV A17 A8

NC

A7 E2 BD BA CK W G A18 A9 NC B

DDQ

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DD

V

DDQ

NC DQB C

DQB DQB D

DQB DQB E

DQB DQB F

DQB DQB G

NC ZQ ZZ H

V

DDQ

DQA DQA J

DQA DQA K

DQA DQA L

A

M

N

DQD DQD V

DQD DNU V

PNCNC

RLBO

NC A3 A2 TMS A0 TCK A10 A13 A15 A16 R

DDQ

A5 A4 TDI A1 TDO A11 A12 A14 NC P

V

DD

V

SS

V

SS

V

SS

V

SS

NC NC NC V

V

DD

SS

V

DDQ

DQA DQA M

NC DQA N

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z36 Pad Out

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

119 Bump BGA—Top View (Package B)

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A V

DDQ

B NC E

C NC A

D DQ

E DQ

F V

G

H DQ

J

K DQ

L DQ

DQ

V

C4

C3

DDQ

C2

C1

DDQ

A1

A2

DQ

V

DQ

6

A

2

5

C9

C8

C7

C6

C5

DD

A5

A6

7

A

4

A

3

A

V

SS

V

SS

V

SS

C

B

V

SS

NC V

V

SS

D

B

18

A

ADV A

V

DD

ZQ V

1

E

G V

17

A

W V

DD

CK V

NC B

8

A

15

14

A

SS

V

SS

B

SS

NC V

SS

A

DQ

9

A

E

16

DD

V

DDQ

3

NC

B9

B8

B7

B6

B5

A5

A6

DQ

V

DQ

V

DQ

B4

B3

DDQ

B2

B1

DDQ

A1

A2

M V

N DQ

P DQ

R

T

U V

DDQ

A3

A4

NC A

NC NC A

DDQ

DQ

A7

A8

A9

2

V

SS

V

SS

V

SS

LBO V

10

CKE V

1

A

0

A

DD

11

A

SS

V

SS

V

SS

FT A

12

A

A7

DQ

A8

DQ

A9

DQ

13

NC ZZ

TMS TDI TCK TDO NC V

V

DQ

PE

DDQ

A3

A4

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18 Pad Out

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

119 Bump BGA—Top View (Package B)

1234567

A V

B

C

D DQ

DDQ

NC E

NC A

B1

NC V

E NC DQ

F V

G

H

J V

DDQ

NC DQ

DQ

DDQ

B4

NC V

V

K NC DQ

L

DQ

B6

NC NC NC B

6

A

2

5

B2

B3

DD

B5

7

A

4

A

3

A

SS

V

SS

B

SS

NC V

V

SS

18

A

ADV A

V

DD

ZQ V

1

E

G V

17

A

W V

DD

CK V

8

A

15

14

A

SS

V

SS

9

A

3

E

16

A

PA9

DQ

NC DQ

A7

DQ

V

NC NC DQ

A5

DQ

SS

NC V

SS

A

NC DQ

DQ

DD

V

A3

DDQ

NC

A8

DDQ

A6

NC

DDQ

A4

NC

M V

N

DQ

DDQ

B8

P NC DQ

R NC A

T

U

NC A

V

DDQ

B7

DQ

NC V

PB9

2

10

V

SS

V

SS

LBO V

11

A

CKE V

1

A

0

A

DD

NC A

SS

V

SS

V

SS

FT A

12

NC V

A2

DQ

NC DQ

13

19

A

TMS TDI TCK TDO NC V

DDQ

NC

A1

PE

ZZ

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description

Symbol Type Description

1

A0, A

An I Address Inputs

DQ

A1

A9

–DQ

DQB1–DQ DQC1–DQ DQD1–DQ

A

, BB, BC, B

B

B9

C0

D0

D

NC — No Connect

CK I Clock Input Signal; active high

CKE

PE

W

E

1 I Chip Enable; active low

E3

E

2

G

ADV I Burst address counter advance enable; active high

ZZ I Sleep mode control; active high

FT

LBO

ZQ I

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I Address field LSBs and Address Counter Preset Inputs

I/O Data Input and Output pins

I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

I Clock Enable; active low

I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

I Write Enable; active low

I Chip Enable; active low

I Chip Enable; active high

I Output Enable; active low

I Flow Through or Pipeline mode; active low

I Linear Burst Order mode; active low

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

I Scan Test Mode Select

I Scan Test Data In

O Scan Test Data Out

I Scan Test Clock

I Core power supply

I I/O and Core Ground

I Output driver power supply

BPR1999.05.18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load activation is accomplished by asserting all three of the Chip Enable inputs (E inputs will deactivate the device.

pin (ADV) held low, in order to load the new address. Device

, E2, and E3). Deassertion of any one of the Enable

1

Function W

B

A

B

C

D

Read H X X X X

Write Byte “a” L L H H H

Write Byte “b” L H L H H

Write Byte “c” L H H L H

Write Byte “d” L H H H L

Write all Bytes L L L L L

Write Abort/NOP L H H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE chip enables (E

1

, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

is asserted low, all three

presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B

, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write

A

cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.

Flow Through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Synchronous Truth Table

Operation Type Address E1E2E3ZZ ADV W Bx G CKE CK DQ Notes

Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z

Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z

Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z

Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1

Read Cycle, Begin Burst R External L H L L L H X L L L-H Q

Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10

NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2

Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10

Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3

Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10

NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3

Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10

Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4

Sleep Mode None X X X H X X X X X X High-Z

Notes:

1. Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.

2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W is sampled low but no Byte Write pins are active, so no write operation is performed.

3. G

can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write

cycles.

4. If CKE

5. X = Don’t Care; H = Logic High; L = Logic Low; Bx

6. All inputs, except G

7. Wait states can be inserted by setting CKE

8. This device contains circuitry that ensures all outputs are in High Z during power-up.

9. A 2-bit burst counter is incorporated.

10. The address counter is incriminated for all Burst continue cycles.

High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus

will remain in High Z.

= High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals

are Low

and ZZ must meet setup and hold times of rising clock edge.

high.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Pipelined and Flow Through Read Write Control State Diagram

D

B

Deselect

R

D

W

New Read New Write

R

B

R

W

R

Burst Read Burst Write

B

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

Next State (n+1)

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

D

W

B

W

B

DD

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒƒƒ

Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Pipeline Mode Data I/O State Diagram

Intermediate Intermediate

Key

ƒ

Transition

Current State (n) Next State (n+2)

W

B

High Z (Data In)

Input Command Code

R

D

Intermediate

Transition

Intermediate State (N+1)

Intermediate

W

High Z

B

D

Intermediate

R

B

Data Out

W

(Q Valid)

Intermediate

R

D

Notes

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command codes as indicated in the Truth Tables.

n n+1 n+2 n+3

Clock (CK)

Command

Current State

ƒ

ƒƒƒ

Intermediate

Next State

State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Data I/O State Diagram

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

W

B

High Z (Data In)

Key Notes

ƒ

Current State (n)

Input Command Code

Transition

R

D

Next State (n+1)

W

R

High Z

B

D

1. The Hold command (CKE Low) is not shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

R

B

Data Out

W

(Q Valid)

D

n n+1 n+2 n+3

Clock (CK)

Command

Current State Next State

ƒ

ƒƒƒ

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

). When this pin is Low, a linear burst

Mode Name

Burst Order Control LBO

Output Register Control FT

Power Down Control ZZ

Note: There are pull-up devices on the ZQ and FT the chip will operate in the default states as specified in the above tables.

Name

State Function

L Linear Burst

H Interleaved Burst

L Flow Through

H or NC Pipeline

L or NC Active

H

pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and

Standby, I

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

DD

= I

SB

A[1:0] A[1:0] A[1:0] A[1:0]

4th address 11 00 01 10

Note: The burst counter wraps to initial state on the 5th clock.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

4th address 11 10 01 00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

ZZ

2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

SB

~

~ ~

~

~ ~

tZZR

tZZS

Sleep

~

tZZH

2. The duration of

SB

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as V

through parts. GSI NBT SRAMs are fully compatible with these sockets.

DD

or V

on pipelined parts and VSS on flow

DDQ

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Absolute Maximum Ratings

(All voltages reference to V

Symbol Description Value Unit

V

DD

V

DDQ

V

I/O

V

IN

I

IN

I

OUT

P

D

T

STG

T

BIAS

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.

)

SS

Voltage on VDD Pins

Voltage in V

DDQ

Pins

Voltage on I/O Pins

Voltage on Other Input Pins

–0.5 to V

–0.5 to 4.6 V

+0.5 (≤ 4.6 V max.)

DDQ

+0.5 (≤ 4.6 V max.)

DD

Input Current on Any Pin +/–20 mA

Output Current on Any I/O Pin +/–20 mA

Package Power Dissipation 1.5 W

Storage Temperature –55 to 125

Temperature Under Bias –55 to 125

V

o

C

o

C

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Power Supply Voltage Ranges

Parameter Symbol Min. Typ. Max. Unit Notes

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

3.3 V Supply Voltage

2.5 V Supply Voltage

3.3 V V

2.5 V V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

I/O Supply Voltage V

DDQ

I/O Supply Voltage V

DDQ

V

DD3

V

DD2

DDQ3

DDQ2

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

3.0 3.3 3.6 V

2.3 2.5 2.7 V

3.0 3.3 3.6 V

2.3 2.5 2.7 V

V

Range Logic Levels

DDQ3

Parameter Symbol Min. Typ. Max. Unit Notes

V

DDQ

DD

+ 0.3

V1

V1,3

VDD Input High Voltage V

Input Low Voltage V

V

DD

V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL

IHQ

ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

2.0 —

–0.3 — 0.8 V 1

2.0 —

–0.3 — 0.8 V 1,3

V

Range Logic Levels

DDQ2

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage V

Input Low Voltage V

V

DD

V

I/O Input High Voltage V

DDQ

I/O Input Low Voltage V

V

DDQ

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

3. V

(max) is voltage on V

IHQ

pins plus 0.3 V.

DDQ

DDn

IH

IL

IHQ

ILQ

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

0.6*V

DD

–0.3 —

0.6*V

DD

–0.3 —

—

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

0.3*V

V

DDQ

0.3*V

DD

+ 0.3

DD

+ 0.3

DD

V1

V1,3

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Ambient Temperature (Commercial Range Versions)

Ambient Temperature (Industrial Range Versions)

Note:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V

T

A

T

A

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

DDn

02570°C2

–40 25 85 °C2

Undershoot Measurement and Timing Overshoot Measurement and Timing

V

– 2.0 V

SS

V

50%

IH

V

+ 2.0 V

DD

SS

20% tKC

50%

V

DD

V

IL

20% tKC

Capacitance

(TA = 25oC, f = 1 MHZ, V

DD

= 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance

Input/Output Capacitance

Note: These parameters are sample tested.

C

IN

C

I/O

V

OUT

IN

= 0 V

45pF

67pF

Package Thermal Characteristics

Rating Layer Board Symbol Max Unit Notes

Junction to Ambient (at 200 lfm) single

Junction to Ambient (at 200 lfm) four

Junction to Case (TOP) —

Notes:

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

R

ΘJA ΘJA ΘJC

40 °C/W 1,2 24 °C/W 1,2

9 °C/W 3

AC Test Conditions

Parameter Conditions

V

DQ

– 0.2 V

DD

V

DDQ

/2

DD

/2

Output Load 1

Input high level

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level

Output reference level

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Fig. 1

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins)

ZZ and PE

FT

Output Leakage Current

Output High Voltage

Output Low Voltage

Input Current

, ZQ Input Current

* Distributed Test Jig Capacitance

I

IL

I

IN1

I

IN2

I

OL

V

OH2

V

OH3

V

OL

50Ω

V

DDQ/2

V 0 V

V

0 V

Output Disable, V

I

= –8 mA, V

OH

I

= –8 mA, V

OH

V

IN

DD ≥

I

OL

30pF

= 0 to V

V

IN

≤ V

IN

V

IN

≤ V

IN

DDQ

= 8 mA

*

DD

≥

VIH

≤ V

≥

VIL

≤ V

= 0 to V

OUT

= 2.375 V

= 3.135 V

–1 uA 1 uA

–1 uA

IH

–1 uA

–100 uA

IL

DD

–1 uA

–1 uA 1 uA

1 uA

100 uA

1 uA 1 uA

1.7 V —

2.4 V —

— 0.4 V

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

–40

0

–40

0

–40

0

–40

0

–40

85°C

70°C

85°C

70°C

85°C

70°C

85°C

70°C

85°C

mA

215

205

235

225

260

250

300

290

Unit

to

40

45

50

60

mA

175

165

190

180

195

185

205

195

20

30

180

170

200

190

215

205

250

240

275

mA

20

25

30

35

mA

150

140

160

150

165

155

175

165

180

10

15

20

165

155

180

170

195

185

225

215

245

mA

10

15

20

mA

135

125

145

135

150

140

160

150

165

10

215

205

235

225

260

250

300

290

mA

30

35

40

45

mA

175

165

190

180

195

185

205

195

20

30

180

170

200

190

215

205

250

240

275

mA

15

20

25

30

mA

150

140

160

150

165

155

175

165

180

10

15

20

165

155

180

170

195

185

225

215

245

mA

10

15

135

125

145

135

150

140

160

150

165

mA

10

mA

0

to

70°C

to

–40

85°C

-250 -225 -200 -166 -150 -133 0

to

70°C

DD

I

n/an/an/an/a

Pipeline

Operating Currents

Parameter Test Conditions Mode Symbol

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

I

DDQ

DD

I

Flow

(x72)

n/an/an/an/a

DDQ

I

Through

35

265

40

300

40

290

DD

I

DDQ

I

Pipeline

Device Selected;

All other inputs

Current

Operating

170

190

180

DD

I

Flow

(x36)

IL

or ≤ V

IH

≥V

20

DDQ

I

Through

Output open

3.3 V

235

270

260

DD

I

Pipeline

20

I

DDQ

155

175

165

DD

I

Flow

(x18)

10

DD

I

DDQ

I

Through

n/an/an/an/a

DDQ

I

Pipeline

(x72)

DD

I

Flow

n/an/an/an/a

265

300

290

DD

I

DDQ

I

Through

30

I

DDQ

I

Pipeline

(x36)

IL

or ≤ V

IH

≥V

Device Selected;

All other inputs

Current

Operating

20

170

20

190

20

180

DD

I

Flow

Through

Output open

2.5 V

235

270

260

15

155

175

165

10

20 30 20 30 20 30 20 30 20 30 20 30

85 90 80 85 75 80 64 70 60 65 50 55

operation.

DDQ2

60 65 60 65 50 55 50 55 50 55 45 50

, and V

SB

DD

I

DDQ

DD

I

DDQ

I

DDQ

I

SB

DD

I

DD

I

DDQ3

, V

DD2

, V

Pipeline

(x18)

Flow

Pipeline

Through

Flow

—

Pipeline

Through

Flow

—

Through

IL

DD3

– 0.2 V

Device Deselected;

or ≤ V

IH

≥ V

All other inputs

apply to any combination of V

DDQ

DD

ZZ ≥ V

and I

Current

Standby

Deselect

Current

DD

Notes:

1. I

2. All parameters listed are worst case scenario.

AC Electrical Characteristics

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Parameter Symbol

-250 -225 -200 -166 -150 -133

Min Max Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns

Clock to Output Valid tKQ — 2.5 — 2.7 — 3.0 — 3.4 — 3.8 — 4.0 ns

Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Pipeline

Clock to Output in Low-Z

tLZ

1

1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Setup time tS 1.2 — 1.3 — 1.4 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.2 — 0.3 — 0.4 — 0.5 — 0.5 — 0.5 — ns

Clock Cycle Time tKC 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 — ns

Clock to Output Valid tKQ — 5.5 — 6.0 — 6.5 — 7.0 — 7.5 — 8.5 ns

Flow

Through

Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Clock to Output in Low-Z

tLZ

1

3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns

Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns

Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns

Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns

Clock to Output in

High-Z

G

to Output Valid tOE — 2.5 — 2.7 — 3.2 — 3.5 — 3.8 — 4.0 ns

to output in Low-Z

G

to output in High-Z

G

ZZ setup time

ZZ hold time

tHZ

tOLZ

tOHZ

tZZS

tZZH

1

1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns

1

0 — 0 — 0 — 0 — 0 — 0 — ns

1

— 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns

2

5 — 5 — 5 — 5 — 5 — 5 — ns

2

1 — 1 — 1 — 1 — 1 — 1 — ns

ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.

Unit

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

tKQX

tHZ

tKQ

tLZ

tKCtKC

tKHtKH

tKLtKL

tH

E

tS

tKQ

tS

tH

tKQXtKQ

tS

D(A) Q(B) Q(C) D(D) Q(E)

Write A Read B Suspend Read C Write D Suspend1 Write Read E Deselect

tH

tS

CK

tH

tS

CKE

tH

tS

E

ADV

tH

tS

W

Bn

AB CD

tS

A0–An

DQ

Pipeline Mode Timing (NBT)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

tKQXtLZ

tHZ

Write A Read B Suspend Read C Write D1 Suspend1 Write Read E Deselect

tKLtKL

tKCtKC

tKHtKH

CK

tH

tKQXtKQ

tHZ

tH

tS

AB C D E

A0–An

D(A) Q(B) Q(C) D(D) Q(E)

DQ

W

tH

tS

tH

tS

Bn

tH

tS

tH

tS

CKE

tS

tH

tS

E

ADV

Flow Through Mode Timing (NBT)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V

drivers are powered by V

DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V

or VSS. TDO should be left unconnected.

DD

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In

TMS Test Mode Select In

TDI Test Data In In

TDO Test Data Out Out

Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.

. The JTAG output

DD

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

0

Bypass Register

012

Instruction Register

TDI

ID Code Register

31 30 29

····

012

TDO

Boundary Scan Register

n

······

···

012

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ID Register Contents

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Die

Revision

Code

Bit # 31302928272625242322212019181716151413121110987654321 0

x72 XXXX000000000000100100011011001 1

x36 XXXX000000000000100000011011001 1

x32 XXXX000000000000110000011011001 1

x18 XXXX000000000000101000011011001 1

x16 XXXX000000000000111000011011001 1

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Presence Register

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Run Test Idle

0

111

Select DR

1

Capture DR

Shift DR

1

Exit1 DR

Pause DR

Exit2 DR

Update DR

1

Select IR

0

1

0

Capture IR

0

Shift IR

1

0

1

Exit1 IR

0

Pause IR

1

0

0 0

1

Exit2 IR

1

Update IR

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z 010

RFU 011

SAMPLE/

PRELOAD

GSI 101 GSI private instruction. 1

RFU 110

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

100

TDO. Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter Symbol Min. Max. Unit Notes

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V

≤ V

2. V

ILJ

3. 0 V

4. Output Disable, V

5. The TDO output driver is served by the V

6. I

OHJ

7. I

OLJ

8. I

OHJC

9. I

OHJC

IN

≤ V

IN

= –4 mA

= + 4 mA

= –100 uA

= +100 uA

≤ V

DDn

ILJn

OUT

= 0 to V

DDn

DDQ

supply.

JTAG Port AC Test Conditions

+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

V

I

V

IHJ3

ILJ3

IHJ2

ILJ2

INHJ

INLJ

OLJ

OHJ

OLJ

OHJC

OLJC

V

DDQ

0.6 * V

V

2.0

DD3

+0.3

V1

–0.3 0.8 V 1

V

–0.3

DD2

0.3 * V

+0.3

DD2

V1

–300 1 uA 2

–1 100 uA 3

–11uA4

1.7 — V5, 6

— 0.4 V 5, 7

– 100 mV

— V5, 8

— 100 mV V 5, 9

Parameter Conditions

Input high level 2.3 V

DQ

JTAG Port AC Test Load

Input low level 0.2 V

Input slew rate 1 V/ns

50Ω

30pF

*

Input reference level 1.25 V

= 1.25 V

V

T

Notes:

Output reference level 1.25 V

* Distributed Test Jig Capacitance

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

tTKQ

tTKL

tTS tTH

tTKC

tTKH

TCK

TMS

TDI

TDO

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 — ns

TCK Low to TDO Valid tTKQ — 20 ns

TCK High Pulse Width tTKH 20 — ns

TCK Low Pulse Width tTKL 20 — ns

TDI & TMS Set Up Time tTS 10 — ns

TDI & TMS Hold Time tTH 10 — ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

.

209 BGA Package Drawing (Package C)

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

A1

C

A

aaa

e

∅b

D

D1

E1

e

Side View

E

Bottom View

Symbol Min Typ Max Units

A

A1 0.40 0.50 0.60 mm

∅b

c

D

D1 18.0 (BSC) mm

E

E1 10.0 (BSC) mm

e

aaa 0.15 mm

Rev 1.0

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

0.50 0.60 0.70 mm

0.31 0.36 0.38 mm

21.9 22.0 22.1 mm

13.9 14.0 14.1 mm

1.00 (BSC) mm

1.70 mm

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Package Dimensions—165-Bump FPBGA (Package D)

A1 CORNER

1 2 3 4 5 6 7 8 9 10 11

A B C D E F G H I J K L M N P R

C

0.25

0.45±0.05

TOP VIEW

M

Ø0.10

C

M

Ø0.25

C A B

Ø0.40~0.50 (165x)

BOTTOM VIEW

A1 CORNER

11 10 9 8 7 6 5 4 3 2 1

A B C D E

1.01.0

F G H

14.0

15±0.07

I J K L M N P R

A

C

0.15

B

0.20(4x)

1.0 1.0

10.0

13±0.07

C

(0.26)

SEATING PLANE

0.25~0.40

1.20 MAX.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Package Dimensions—119-Pin PBGA (Package B)

Pin 1 Corner

A

A B C D E F G H J K L M N P R T U

B

G

D

S

1234567

A B C D E F G H J K L M N P R T U

R

Top View

Package Dimensions—119-Pin PBGA

Bottom View

F

Symbol Description Min. Nom. Max

A Width 13.9 14.0 14.1

B Length 21.9 22.0 22.1

C Package Height (including ball) 1.73 1.86 1.99

D Ball Size 0.60 0.75 0.90

E Ball Height 0.50 0.60 0.70

F Package Height (excluding balls) 1.16 1.26 1.36

G Width between Balls 1.27

K

E

CT

K Package Height above board 0.65 0.70 0.75

R Width of package between balls 7.62

S Length of package between balls 20.32

T Variance of Ball Height 0.15

Unit: mm

Side View

BPR 1999.05.18

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Ordering Information—GSI NBT Synchronous SRAM

Org

1M x 18 GS8162Z18B-250 NBT Pipeline/Flow Through 119 BGA 250/5.5 C

1M x 18 GS8162Z18B-225 NBT Pipeline/Flow Through 119 BGA 225/6 C

1M x 18 GS8162Z18B-200 NBT Pipeline/Flow Through 119 BGA 200/6.5 C

1M x 18 GS8162Z18B-166 NBT Pipeline/Flow Through 119 BGA 166/7 C

1M x 18 GS8162Z18B-150 NBT Pipeline/Flow Through 119 BGA 150/7.5 C

1M x 18 GS8162Z18B-133 NBT Pipeline/Flow Through 119 BGA 133/8.5 C

512K x 36 GS8162Z36B-250 NBT Pipeline/Flow Through 119 BGA 250/5.5 C

512K x 36 GS8162Z36B-225 NBT Pipeline/Flow Through 119 BGA 225/6 C

512K x 36 GS8162Z36B-200 NBT Pipeline/Flow Through 119 BGA 200/6.5 C

512K x 36 GS8162Z36B-166 NBT Pipeline/Flow Through 119 BGA 166/7 C

512K x 36 GS8162Z36B-150 NBT Pipeline/Flow Through 119 BGA 150/7.5 C

512K x 36 GS8162Z36B-133 NBT Pipeline/Flow Through 119 BGA 133/8.5 C

1M x 18 GS8162Z18D-250 NBT Pipeline/Flow Through 165 BGA 250/5.5 C

1M x 18 GS8162Z18D-225 NBT Pipeline/Flow Through 165 BGA 225/6 C

1M x 18 GS8162Z18D-200 NBT Pipeline/Flow Through 165 BGA 200/6.5 C

1M x 18 GS8162Z18D-166 NBT Pipeline/Flow Through 165 BGA 166/7 C

1M x 18 GS8162Z18D-150 NBT Pipeline/Flow Through 165 BGA 150/7.5 C

1M x 18 GS8162Z18D-133 NBT Pipeline/Flow Through 165 BGA 133/8.5 C

512K x 36 GS8162Z36D-250 NBT Pipeline/Flow Through 165 BGA 250/5.5 C

512K x 36 GS8162Z36D-225 NBT Pipeline/Flow Through 165 BGA 225/6 C

512K x 36 GS8162Z36D-200 NBT Pipeline/Flow Through 165 BGA 200/6.5 C

512K x 36 GS8162Z36D-166 NBT Pipeline/Flow Through 165 BGA 166/7 C

512K x 36 GS8162Z36D-150 NBT Pipeline/Flow Through 165 BGA 150/7.5 C

512K x 36 GS8162Z36D-133 NBT Pipeline/Flow Through 165 BGA 133/8.5 C

256K x 72 GS8162Z72C-200 NBT Pipeline/Flow Through 209 BGA 200/6.5 C

256K x 72 GS8162Z72C-166 NBT Pipeline/Flow Through 209 BGA 166/7 C

256K x 72 GS8162Z72C-150 NBT Pipeline/Flow Through 209 BGA 150/7.5 C

256K x 72 GS8162Z72C-133 NBT Pipeline/Flow Through 209 BGA 133/8.5 C

1M x 18 GS8162Z18B-250I NBT Pipeline/Flow Through 119 BGA 250/5.5 I

1M x 18 GS8162Z18B-225I NBT Pipeline/Flow Through 119 BGA 225/6 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings

Speed

(MHz/ns)

2

3

T

A

Status

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Org

1M x 18 GS8162Z18B-200I NBT Pipeline/Flow Through 119 BGA 200/6.5 I

1M x 18 GS8162Z18B-166I NBT Pipeline/Flow Through 119 BGA 166/7 I

1M x 18 GS8162Z18B-150I NBT Pipeline/Flow Through 119 BGA 150/7.5 I

1M x 18 GS8162Z18B-133I NBT Pipeline/Flow Through 119 BGA 133/8.5 I

512K x 36 GS8162Z36B-250I NBT Pipeline/Flow Through 119 BGA 250/5.5 I

512K x 36 GS8162Z36B-225I NBT Pipeline/Flow Through 119 BGA 225/6 I

512K x 36 GS8162Z36B-200I NBT Pipeline/Flow Through 119 BGA 200/6.5 I

512K x 36 GS8162Z36B-166I NBT Pipeline/Flow Through 119 BGA 166/7 I

512K x 36 GS8162Z36B-150I NBT Pipeline/Flow Through 119 BGA 150/7.5 I

512K x 36 GS8162Z36B-133I NBT Pipeline/Flow Through 119 BGA 133/8.5 I

1M x 18 GS8162Z18D-250I NBT Pipeline/Flow Through 165 BGA 250/5.5 I

1M x 18 GS8162Z18D-225I NBT Pipeline/Flow Through 165 BGA 225/6 I

1M x 18 GS8162Z18D-200I NBT Pipeline/Flow Through 165 BGA 200/6.5 I

1M x 18 GS8162Z18D-166I NBT Pipeline/Flow Through 165 BGA 166/7 I

1M x 18 GS8162Z18D-150I NBT Pipeline/Flow Through 165 BGA 150/7.5 I

1M x 18 GS8162Z18D-133I NBT Pipeline/Flow Through 165 BGA 133/8.5 I

512K x 36 GS8162Z36D-250I NBT Pipeline/Flow Through 165 BGA 250/5.5 I

512K x 36 GS8162Z36D-225I NBT Pipeline/Flow Through 165 BGA 225/6 I

512K x 36 GS8162Z36D-200I NBT Pipeline/Flow Through 165 BGA 200/6.5 I

512K x 36 GS8162Z36D-166I NBT Pipeline/Flow Through 165 BGA 166/7 I

512K x 36 GS8162Z36D-150I NBT Pipeline/Flow Through 165 BGA 150/7.5 I

512K x 36 GS8162Z36D-133I NBT Pipeline/Flow Through 165 BGA 133/8.5 I

256K x 72 GS8162Z72C-200I NBT Pipeline/Flow Through 209 BGA 200/6.5 I

256K x 72 GS8162Z72C-166I NBT Pipeline/Flow Through 209 BGA 166/7 I

256K x 72 GS8162Z72C-150I NBT Pipeline/Flow Through 209 BGA 150/7.5 I

256K x 72 GS8162Z72C-133I NBT Pipeline/Flow Through 209 BGA 133/8.5 I

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user.

3. T

= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

A

4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com

Part Number

1

Type Package

) for a complete listing of current offerings

Speed

(MHz/ns)

2

3

T

A

Status

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

18Mb Sync SRAM Datasheet Revision History

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

DS/DateRev. Code: Old;

New

GS8162Z18/36/72B 1.00 9/

1999A;GS8162Z18/36/

72B2.0012/1999B

GS8162Z18/36/72B2.00 12/

1999BGS8162Z18/36/

72B2.01 1/2000C

GS8162Z18/36/72B2.01 1/

2000C;GS8162Z18/36/

72B2.02 1/2000D

GS8162Z18/36/72B2.02 1/

2000DGS8162Z18/36/

72B2.03 2/2000E

GS8162Z18/36/72B2.03 2/

2000E; 8162Z18_r2_04

Types of Changes Format or Content

Content

Format

Content

Page;Revisions;Reason

• Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B

• Added x72 Pinout.

• Added new GSI Logo

• Added 209 Pin BGA Package diagram

• Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Completeness

• Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness.

• Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness

• Electrical Characteristics - Added second Output High Voltage line to table; completeness.

• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.

• Pin 6N changed to MCH.

8162Z18_r2_04;

8162Z18_r2_05

8162Z18_r2_05;

8162Z18_42_06

8162Z18_r2_06;

8162Z18_r2_07

8162Z18_r2_07;

8162Z18_r2_08

8162Z18_r2_08;

8162Z18_r2_09

8162Z18_r2_09;

8162Z18_r2_10

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Content

Content/Format

Content

• Updated BGA pin description tables to meet JEDEC standards

• Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 22 from 20 ns to 100 ns

• Added 225 MHz speed bin

• Updated numbers in page 1 table, AC Characteristics table, and Operating Currents table

• Updated format to comply with Technical Publications standards

• Changed V

• Changed K4 and K8 in 209-bump BGA to NC

• Updated numbers for Clock to Output Valid (PL) and Clock to Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical Characteristics table

• Updated Features list on page 1

• Completely reworked table on page 1

• Updated Mode Pin Functions table on page 14

references to V

SSQ

SS

18Mb Sync SRAM Datasheet Revision History

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

DS/DateRev. Code: Old;

New

8162Z18_r2_10;

8162Z18_r2_11

8162Z18_r2_11;

8162Z18_r2_11

8162Z18_r2_12;

8162Z18_r2_13

8162Z18_r2_13;

8162Z18_r2_14

8162Z18_r2_14;

8162Z18_r2_15

Types of Changes Format or Content

Content

Page;Revisions;Reason

• Added 3.3 V references to entire document

• Updated Operating Conditions table

• Updated JTAG section

• Updated Operating Currents table and added note

• Updated Boundary Scan Chain table

• Updated table on page 1; added power numbers

• Updated DQ on page 24

• Updated DQ on page 26 (Q(A3))

• Updated ID Register Contents table

• Updated Operating Currents table

• Updated power numbers in table on page 1

• Updated Recommended Operating Conditions table (added V

references)

DDQ

• Updated table on page 1

• Added 119-Bump BGA Pin Description table

• Created recommended operating conditions tables on pages 19 and 20

• Updated AC Electrical Characteristics table

• Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns)

• Updated BSR table (2 and 3 changed to X (value undefined))

• Added 250 MHz speed bin

• Deleted 180 MHz speed bin

• Added parity bit references to x18 pad out and pin description table

• Updated x36 pinout (DQA pins listed twice)

• Updated pin description tables to match pinouts

• Updated Flow Through power numbers in table on page 1 and Operating Currents table

• Updated Pipeline and Flow Through numbers in AC Charac-

8162Z18_r2_15;

8162Z18_r2_16

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Content

teristics table

• Added 165-bump BGA package, pinout, and pinout description

• Removed ByteSafe pins and references

• Updated AC Test Conditions table and removed Output Load 2 diagram

18Mb Sync SRAM Datasheet Revision History

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

DS/DateRev. Code: Old;

New

8162Z18_r2_16;

8162Z18_r2_17

8162Z18_r2_17;

8162Z18_r2_18

Types of Changes Format or Content

Content

Page;Revisions;Reason

• Removed parity I/O bit designation from 165 BGA pinout

• Updated both 209 BGA and 119 BGA pin description tables

• Removed pin locations from pin description tables

• Removed Preliminary banner

• Removed BSR table

• Removed 250 MHz and 225 MHz specs from x72

• Updated AC Characteristics table (tHZ, tOE, tOHZ equal to tKQ (PL) for 250 MHz and 225 MHz)

• Added new timing diagrams

• Added specific address locations to 165 BGA

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.