Datasheet GS816018BT-250, GS816018BT-200, GS816018BT-150, GS816032BT-250, GS816032BT-200 Datasheet (GSI TECHNOLOGY)
...Page 1
GS816018/32/36BT-250/200/150
100-Pin TQFP
1M x 18, 512K x 32, 512K x 36
Commercial Temp
Industrial Temp
18Mb Sync Burst SRAMs
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (
(
Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (
and power down control (ZZ) are asynchronous inputs. Burst
ADSP, ADSC, ADV), and write control inputs
G)
250 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
cycles can be initiated with either
Burst mode, subsequent burst addresses are generated
internally and are controlled by
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the
FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(
BW) input combined with one or more individual byte write
signals (
writing all bytes at one time, regardless of the Byte Write
Bx). In addition, Global Write (GW) is available for
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816018/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
) pins are used to decouple output noise
DDQ
from the internal circuits and are 3.3 V and 2.5 V compatible.
ADSP or ADSC inputs. In
ADV. The burst address
LBO) input. The
DD
FT
Parameter Synopsis
-250 -200 -150 Unit
t
KQ
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
Rev: 1.03 9/2005 1/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2.5
4.0
295
345
5.5
5.5
225
255
3.0
5.0
245
285
6.5
6.5
200
220
3.8
6.7
200
225
7.5
7.5
185
205
ns
ns
mA
mA
ns
ns
mA
mA
Page 2
GS816018B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQB
DQB
V
SS
V
DDQ
DQB
DQB
FT
V
DD
NC
V
SS
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQPB
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
B
B
BA
Top View
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DD
E3
SS
V
V
1M x 18
CK
GW
BW
ADSC
ADV
ADSP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
A
DQ
DQA
V
DDQ
V
SS
DQA
DQA
NC
NC
V
SS
V
DDQ
NC
NC
NC
G
A
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
A
V
V
A A A A A
A
A
Rev: 1.03 9/2005 2/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 3
GS816032B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
V
V
V
V
NC
DQC
DQ
DDQ
V
SS
DQC
DQ
DQC
DQC
V
SS
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
DDQ
DQD
DQD
NC
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
C
C
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
512K x 32
Top View
DD
E3
SS
V
V
CK
GW
BW
G
ADSC
ADV
ADSP
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQ
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
NC
B
A
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
A
V
V
A
A A A A A
A
A
Rev: 1.03 9/2005 3/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 4
GS816036B 100-Pin TQFP Pinout
GS816018/32/36BT-250/200/150
DQPC
DQC
DQC
V
DDQ
V
SS
DQC
DQC
DQC
DQC
V
SS
V
DDQ
DQC
DQC
FT
V
DD
NC
V
SS
DQD
DQD
V
DDQ
V
SS
DQD
DQD
DQD
DQD
V
SS
V
DDQ
DQD
DQD
DQPD
1
A
E
A
E2
10099989796959493929190898887868584838281
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BB
BA
BC
BD
512K x 36
Top View
DD
E3
SS
V
V
CK
GW
BW
G
ADSC
ADV
ADSP
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
V
DDQ
V
SS
DQB
DQB
DQB
DQB
V
SS
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
A
DQ
DQA
V
DDQ
V
SS
DQA
DQA
DQA
DQA
V
SS
V
DDQ
DQA
DQA
DQPA
SS
LBO
A
A
A
A
A1A0
NC
NC
DD
V
V
A
A A A A A
A
A
A
Rev: 1.03 9/2005 4/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 5
GS816018/32/36BT-250/200/150
TQFP Pin Description
Symbol Type Description
A0, A1 I Address field LSBs and Address Counter preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
NC No Connect
BW I Byte Write—Writes all enabled bytes; active low
BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable—Writes all bytes; active low
E1, E3 I Chip Enable; active low
E2 I Chip Enable; active high
G I Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
V
DD
V
SS
V
DDQ
I/O Data Input and Output pins
I Core power supply
I I/O and Core Ground
I Output driver power supply
Rev: 1.03 9/2005 5/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 6
GS816018/32/36B Block Diagram
GS816018/32/36BT-250/200/150
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0
D1
Counter
Load
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Q0
Q1
A0
A1
A
Memory
Array
QD
36
4
DQ
Register
36
Register
DQ
E1
E2
E3
FT
G
ZZ
Note: Only x36 version shown for simplicity.
Power Down
Control
Register
DQ
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.03 9/2005 6/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 7
Mode Pin Functions
GS816018/32/36BT-250/200/150
Mode Name
Burst Order Control LBO
Output Register Control FT
Power Down Control ZZ
Single/Dual Cycle Deselect Control SCD
FLXDrive Output Impedance Control ZQ
Note:
There is a are pull-up devices on the ZQ and SCD FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Pin
Name
State Function
L Linear Burst
H Interleaved Burst
L Flow Through
H or NC Pipeline
L or NC Active
H
L Dual Cycle Deselect
H or NC Single Cycle Deselect
L High Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Standby, IDD = I
SB
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 9/2005 7/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 8
GS816018/32/36BT-250/200/150
Byte Write Truth Table
Function GW BW BA BB BC BD Notes
Read H H X X X X 1
Read H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.03 9/2005 8/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 9
Synchronous Truth Table
GS816018/32/36BT-250/200/150
Operation
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Address
Used
Diagram
5
Key
E1
E
2
ADSP ADSC ADV
W
3
DQ
4
State
Rev: 1.03 9/2005 9/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 10
Simplified State Diagram
X
Deselect
WR
GS816018/32/36BT-250/200/150
Simple Synchronous OperationSimple Burst Synchronous Operation
W
X
First Write
WR
Burst Write
CW CR
R
CR
R
CR
R
First Read
Burst Read
X
CRCW
XX
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G
2. The upper portion of the diagram assumes active use of only the Enable (E1
control inputs, and that ADSP
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC
assumes ADSP
Rev: 1.03 9/2005 10/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
is tied high and ADV is tied low.
is tied high and ADSC is tied low.
, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
is tied low.
control inputs, and
Page 11
Simplified State Diagram with G
X
Deselect
WR
GS816018/32/36BT-250/200/150
W
X
First Write
W
X
Burst Write
CW CR
R
CR
R
CR
W
CW
W
CW
R
First Read
R
Burst Read
X
CRCW
X
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G
2. Use of “Dummy Reads” (Read Cycles with G
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G
Data Input Set Up Time.
Rev: 1.03 9/2005 11/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
High) may be used to make the transition from Read cycles to Write cycles without passing
has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
.
Page 12
GS816018/32/36BT-250/200/150
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
V
DD
V
DDQ
V
I/O
V
IN
I
IN
I
OUT
P
D
T
STG
T
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Voltage on VDD Pins
Voltage in V
DDQ
Pins
Voltage on I/O Pins
Voltage on Other Input Pins
–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to V
–0.5 to V
DDQ
DD
+0.5
+0.5
V
V
Input Current on Any Pin +/–20 mA
Output Current on Any I/O Pin +/–20 mA
Package Power Dissipation 1.5 W
Storage Temperature –55 to 125
Temperature Under Bias –55 to 125
o
o
C
C
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage
2.5 V Supply Voltage
3.3 V V
2.5 V V
I/O Supply Voltage V
DDQ
I/O Supply Voltage V
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
V
DD3
V
DD2
DDQ3
DDQ2
+1.5 V maximum, with a pulse width not to exceed 50% tKC.
DDn
3.0 3.3 3.6 V
2.3 2.5 2.7 V
3.0 3.3 3.6 V
2.3 2.5 2.7 V
Rev: 1.03 9/2005 12/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 13
V
Range Logic Levels
DDQ3
GS816018/32/36BT-250/200/150
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
V
Input Low Voltage V
DD
V
I/O Input High Voltage V
DDQ
V
I/O Input Low Voltage V
DDQ
IH
IL
IHQ
ILQ
2.0 —
–0.3 — 0.8 V 1
2.0 —
–0.3 — 0.8 V 1,3
VDD + 0.3
V
+ 0.3
DDQ
V 1
V 1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
V
(max) is voltage on V
IHQ
Range Logic Levels
DDQ2
pins plus 0.3 V.
DDQ
+1.5 V maximum, with a pulse width not to exceed 50% tKC.
DDn
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage V
V
Input Low Voltage V
DD
V
I/O Input High Voltage V
DDQ
V
I/O Input Low Voltage V
DDQ
IH
IL
IHQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
3. V
(max) is voltage on V
IHQ
pins plus 0.3 V.
DDQ
+1.5 V maximum, with a pulse width not to exceed 50% tKC.
DDn
0.6*V
DD
–0.3 —
0.6*V
DD
–0.3 —
—
—
VDD + 0.3
0.3*V
V
+ 0.3
DDQ
0.3*V
DD
DD
V 1
V 1
V 1,3
V 1,3
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < V
Rev: 1.03 9/2005 13/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
T
A
T
A
+1.5 V maximum, with a pulse width not to exceed 50% tKC.
DDn
0 25 70 °C 2
–40 25 85 °C 2
Page 14
GS816018/32/36BT-250/200/150
Undershoot Measurement and Timing Overshoot Measurement and Timing
V
IH
V
+1.5 V
DD
V
SS
50%
50% tKC
50%
V
– 2.0 V
SS
50% tKC
Capacitance
o
(TA = 25 = 2.5 V)
C, f = 1 MHZ, V
DD
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance
Input/Output Capacitance
Note:
These parameters are sample tested.
C
IN
C
I/O
AC Test Conditions
Parameter Conditions
Input high level
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level
Output reference level
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
VDD – 0.2 V
VDD/2
V
/2
DDQ
V
V
OUT
IN
= 0 V
= 0 V
V
DD
V
IL
4 5 pF
6 7 pF
Output Load 1
DQ
50Ω
V
DDQ/2
* Distributed Test Jig Capacitance
30pF
*
Rev: 1.03 9/2005 14/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 15
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins)
ZZ Input Current
FT Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
V
V
I
I
V
I
IL
IN1
IN2
I
OL
OH2
OH3
OL
V
= 0 to V
IN
V
DD ≥ VIN ≥ VIH
0 V ≤ V
V
DD ≥ VIN ≥ VIL
0 V ≤ V
Output Disable, V
I
= –8 mA, V
OH
I
= –8 mA, V
OH
I
= 8 mA
OL
GS816018/32/36BT-250/200/150
–1 uA 1 uA
–1 uA
–1 uA
–100 uA
–1 uA
–1 uA 1 uA
1.7 V —
2.4 V —
— 0.4 V
IN
IN
OUT
DDQ
DDQ
≤ V
≤ V
DD
IH
IL
= 0 to V
= 2.375 V
= 3.135 V
DD
1 uA
100 uA
1 uA
1 uA
Rev: 1.03 9/2005 15/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 16
Operating Currents
Parameter Test Conditions Mode Symbol
Flow Through
Flow Through
Flow Through
Flow Through
, V
DD3
Pipeline
Pipeline
Pipeline
Pipeline
, V
DD2
DDQ3
, and V
(x32/
x36)
(x18)
—
—
Operating
Current
Standby
Current
Deselect
Current
Device Selected;
All other inputs
≥VIH or ≤ V
Output open
ZZ ≥ V
Device Deselected;
All other inputs
≥ VIH or ≤ V
DD
IL
– 0.2 V
IL
Notes:
1. IDD and I
apply to any combination of V
DDQ
2. All parameters listed are worst case scenario.
I
I
I
I
I
DD
DDQ
I
DD
DDQ
I
DD
DDQ
I
DD
DDQ
I
SB
I
SB
I
DD
I
DD
DDQ2
GS816018/32/36BT-250/200/150
-250 -200 -150
0
to
70°C
305
40
235
20
275
20
215
10
40 50 40 50 40 50 mA
40 50 40 50 40 50 mA
85 90 75 80 60 65 mA
60 65 50 55 50 55 mA
operation.
–40
to
85°C
315
40
245
20
285
20
225
10
0
to
70°C
255
30
205
15
230
15
190
10
–40
to
85°C
265
30
215
15
240
15
200
10
0
to
70°C
205
20
190
15
185
15
175
10
–40
to
85°C
215
20
200
15
195
15
185
10
Unit
mA
mA
mA
mA
Rev: 1.03 9/2005 16/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 17
AC Electrical Characteristics
GS816018/32/36BT-250/200/150
Pipeline
Flow Through
Parameter Symbol
Clock Cycle Time tKC 4.0 — 5.0 — 6.7 — ns
Clock to Output Valid tKQ — 2.5 — 3.0 — 3.8 ns
Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — ns
Clock to Output in Low-Z
Setup time tS 1.2 — 1.4 — 1.5 — ns
Hold time tH 0.2 — 0.4 — 0.5 — ns
Clock Cycle Time tKC 5.5 — 6.5 — 7.5 — ns
Clock to Output Valid tKQ — 5.5 — 6.5 — 7.5 ns
Clock to Output Invalid tKQX 2.0 — 2.0 — 2.0 — ns
Clock to Output in Low-Z
Setup time tS 1.5 — 1.5 — 1.5 — ns
Hold time tH 0.5 — 0.5 — 0.5 — ns
Clock HIGH Time tKH 1.3 — 1.3 — 1.5 — ns
Clock LOW Time tKL 1.5 — 1.5 — 1.7 — ns
Clock to Output in
High-Z
G to Output Valid tOE — 2.5 — 3.0 — 3.8 ns
G to output in Low-Z
G to output in High-Z
ZZ setup time
ZZ hold time
ZZ recovery tZZR 20 — 20 — 20 — ns
tLZ
tLZ
tHZ
tOLZ
tOHZ
tZZS
tZZH
1
1
1
1
1
2
2
-250 -200 -150
Min Max Min Max Min Max
1.5 — 1.5 — 1.5 — ns
2.0 — 2.0 — 2.0 — ns
1.5 2.5 1.5 3.0 1.5 3.0 ns
0 — 0 — 0 — ns
— 2.5 — 3.0 — 3.8 ns
5 — 5 — 5 — ns
1 — 1 — 1 — ns
Unit
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times
as specified above.
Rev: 1.03 9/2005 17/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 18
CK
ADSP
ADSC
ADV
A0–An
GW
GS816018/32/36BT-250/200/150
Pipeline Mode Timing
Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
Burst ReadBurst ReadSingle Write
tKH
tKH
Single WriteSingle Read
tKLtKL
tKCtKC
ADSC initiated read
Single Read
tS
tH
tHtS
tS
tH
ABC
tS
BW
Ba–Bd
E1
E2
E3
DQa–DQd
tHtS
tH
tS
tS
tS
tH
tS
tH
G
tH
E2 and E3 only sampled with ADSP and ADSC
tS
tOHZtOE
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
E1 masks ADSP
tLZtH
Deselected with E1
tKQXtKQ
tHZ
Rev: 1.03 9/2005 18/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 19
GS816018/32/36BT-250/200/150
Flow Through Mode Timing
Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect
tKLtKL
tKHtKH
CK
tKCtKC
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
Fixed High
tS
tH
tS
tH
tS
tH
ABC
tS
tH
tS
tH
tS
tH
ADSC initiated read
tS
tH
tS
tH
Deselected with E1
tS
tH
E2
tS
tH
E3
G
DQa–DQd
E2 and E3 only sampled with ADSC
tH
tS
tOHZtOE
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQ
tLZ
tHZ
tKQX
Rev: 1.03 9/2005 19/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 20
GS816018/32/36BT-250/200/150
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
tKHtKH
tKCtKC
CK
Setup
Hold
ADSP
tKLtKL
ADSC
tZZR
tZZHtZZS
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
Rev: 1.03 9/2005 20/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 21
GS816018/32/36BT-250/200/150
TQFP Package Drawing (Package T)
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 — 0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch — 0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length — 1.00 —
Y Coplanarity 0.10
θ Lead Angle 0° — 7°
L1
A1
θ
L
c
Pin 1
D1
D
e
b
A2
Y
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 1.03 9/2005 21/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 22
Ordering Information for GSI Synchronous Burst RAMs
GS816018/32/36BT-250/200/150
Org
1M x 18 GS816018BT-250 Pipeline/Flow Through TQFP 250/5.5 C MP
1M x 18 GS816018BT-200 Pipeline/Flow Through TQFP 200/6.5 C MP
1M x 18 GS816018BT-150 Pipeline/Flow Through TQFP 150/7.5 C MP
512K x 32 GS816032BT-250 Pipeline/Flow Through TQFP 250/5.5 C MP
512K x 32 GS816032BT-200 Pipeline/Flow Through TQFP 200/6.5 C MP
512K x 32 GS816032BT-150 Pipeline/Flow Through TQFP 150/7.5 C MP
512K x 36 GS816036BT-250 Pipeline/Flow Through TQFP 250/5.5 C MP
512K x 36 GS816036BT-200 Pipeline/Flow Through TQFP 200/6.5 C MP
512K x 36 GS816036BT-150 Pipeline/Flow Through TQFP 150/7.5 C MP
1M x 18 GS816018BT-250I Pipeline/Flow Through TQFP 250/5.5 I MP
1M x 18 GS816018BT-200I Pipeline/Flow Through TQFP 200/6.5 I MP
1M x 18 GS816018BT-150I Pipeline/Flow Through TQFP 150/7.5 I MP
512K x 32 GS816032BT-250I Pipeline/Flow Through TQFP 250/5.5 I MP
512K x 32 GS816032BT-200I Pipeline/Flow Through TQFP 200/6.5 I MP
512K x 32 GS816032BT-150I Pipeline/Flow Through TQFP 150/7.5 I MP
512K x 36 GS816036BT-250I Pipeline/Flow Through TQFP 250/5.5 I MP
512K x 36 GS816036BT-200I Pipeline/Flow Through TQFP 200/6.5 I MP
512K x 36 GS816036BT-150I Pipeline/Flow Through TQFP 150/7.5 I MP
1M x 18 GS816018BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C PQ
1M x 18 GS816018BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C PQ
1M x 18 GS816018BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C PQ
512K x 32 GS816032BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C PQ
512K x 32 GS816032BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C PQ
512K x 32 GS816032BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C PQ
512K x 36 GS816036BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C PQ
512K x 36 GS816036BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C PQ
512K x 36 GS816036BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C PQ
1M x 18 GS816018BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I PQ
1M x 18 GS816018BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I PQ
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (
Part Number
1
Type Package
www.gsitechnology.com) for a complete listing of current offerings.
Speed
(MHz/ns)
2
3
T
Status
A
Rev: 1.03 9/2005 22/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 23
Ordering Information for GSI Synchronous Burst RAMs (Continued)
GS816018/32/36BT-250/200/150
Org
1M x 18 GS816018BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I PQ
512K x 32 GS816032BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I PQ
512K x 32 GS816032BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I PQ
512K x 32 GS816032BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I PQ
512K x 36 GS816036BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I PQ
512K x 36 GS816036BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I PQ
512K x 36 GS816036BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I PQ
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. T
= C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
A
4. MP = Mass Production. PQ = Pre-Qualification.
5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com
Part Number
1
Type Package
) for a complete listing of current offerings.
Speed
(MHz/ns)
2
3
T
Status
A
Rev: 1.03 9/2005 23/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 24
18Mb Sync SRAM Datasheet Revision History
GS816018/32/36BT-250/200/150
DS/DateRev. Code: Old;
New
8160xxB_r1
8160xxB_r1; 8160xxB_r1_01 Content
8160xxB_r1_01;
8160xxB_r1_02
8160xxB_r1_02;
8160xxB_r1_03
Types of Changes
Format or Content
Content
Content
Page;Revisions;Reason
• Creation of new datasheet
• Updated overshoot/undershoot information
• Added 300 MHz speed bin
• Removed 300 MHz speed bin
• Added Status column to Ordering Information table
• Changed Pb-free to RoHS-compliant
Rev: 1.03 9/2005 24/24 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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