Datasheet GS78116B-15I, GS78116B-12I, GS78116B-12, GS78116B-10I, GS78116B-10 Datasheet (GSI)

GS78116B

BGA

512K x 16

Commercial Temp
Industrial Temp

8Mb Asynchronous SRAM

Features

• Fast access time: 10, 12, 15 ns

• CMOS low power operation: 300/250/220/180 mA at
minimum cycle time

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• 14 mm x 22 mm, 119-Bump, 1.27 mm Pitch Ball Grid Array
package

Description

The GS78116 is a high speed CMOS static RAM organized as
524,288-words by 16-bits. Static design eliminates the need for
external clocks or timing strobes. The GS78116 operates on a
single 3.3 V power supply and all inputs and outputs are TTL­compatible. The GS78116 is available in 14 mm x 22 mm
BGA package.

Pin Descriptions

Symbol Description

A0 to A18 Address input

DQ1 to DQ16 Data input/output

CE Chip enable input
WE Write enable input
OE Output enable input

V

DD

V

SS

NC No connect

10, 12, 15 ns

3.3 V V

+3.3 V power supply

Ground

DD

Block Diagram

A0

A18

CE

WE

OE

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column

Decoder

I/O Buffer

DQ1

DQ16

Rev: 1.02 9/2001 1/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

512K x 16 Async SRAM in 119-Bump, 14 mm x 22 mm

Top View

1 2 3 4 5 6 7

A NC A15 A14 A16 A13 A12 NC

GS78116B

B

NC,

VSS

A11 A10 CE A9 A8 NC

C NC NC

D NC

V

DD

E DQ1 NC

F DQ2

V

DD

G DQ3 NC

H DQ4

J VDD

K DQ5

V

DD

V

SS

V

DD

L DQ6 NC

VDD,

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

A17

V

V

V

V

V

V

V

V

SS

SS

SS

SS

SS

SS

SS

SS

VSS,

NC

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

NC NC

V

DD

NC

NC DQ16

V

DD

DQ15

NC DQ14

V

V

V

DD

SS

DD

DQ13

VDD

DQ12

NC DQ11

M DQ7

V

N DQ8 NC

P NC

V

DD

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

SS

V

DD

DQ10

NC DQ9

V

DD

NC

R NC NC NC A18 NC NC NC

T NC A7 A6 WE A5 A4

NC,

VSS

U NC A3 A2 OE A1 A0 NC

Note: Bumps 1B, 7T, 3C, and 5C are actually NC’s but should be wired 3C = VDD and 1B, 7T and 5C = VSS to assure compatibility

with future versions.

Rev: 1.02 9/2001 2/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Truth Table

CE OE WE DQ1 to DQ8 VDD Current

H X X Not Selected ISB1, ISB2

L L H Read
L X L Write IDD
L H H High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD –0.5 to +4.6 V

GS78116B

Input Voltage

Output Voltage

V

V

OUT

IN

(≤ 4.6 V max.)

–0.5 to VDD+0.5

(≤ 4.6 V max.)

–0.5 to V

DD

+0.5

V

V

Allowable power dissipation PD 1.5 W

Storage temperature

T

STG

–55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply Voltage for -10/12/15

Input High Voltage

Input Low Voltage

Ambient Temperature,

Commercial Range

V

DD

V

IH

V

IL

T

Ac

3.0 3.3 3.6 V

2.0 —

VDD +0.3

–0.3 — 0.8 V

0 — 70

V

o

C

Ambient Temperature,

Industrial Range

T

Ai

–40 — 85

o

C

Notes:

1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Rev: 1.02 9/2001 3/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Capacitance

GS78116B

Parameter Symbol

Input Capacitance

Output Capacitance

C

IN

C

OUT

Test

Condition

V

= 0 V

IN

V

= 0 V

OUT

Max Unit

10 pF

7 pF

Notes:

1. Tested at TA = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage

Current

Output Leakage

Current

Output High Voltage

Output Low Voltage

I

IL

I

OL

V

OH

V

OL

V

= 0 to VDD

IN

Output High Z,

V

= 0 to VDD

OUT

I

= –4 mA

OH

I

= +4 mA

OL

–2 uA 2 uA

–1 uA 1 uA

2.4

0.4 V

Power Supply Currents

Parameter Symbol Test Conditions

E ≤ V

Operating

Supply

Current

Standby

Current

Standby

Current

I

I

I

DD

SB1

SB2

All other inputs

≥ VIH or ≤ V

Min. cycle time

I

OUT

E ≥ VIH

All other inputs

≥ VIH or ≤V

Min. cycle time

E ≥ VDD – 0.2V

All other inputs

≥ VDD – 0.2 V or ≤ 0.2 V

IL

= 0 mA

0 to 70°C –40 to 85°C

10 ns 12 ns 15 ns 10 ns 12 ns 15 ns

IL

IL

225 mA 220 mA 180 mA 270 mA 240 mA 200 mA

130 mA 120 mA 110 mA 150 mA 140 mA 130 mA

60 mA 80 mA

Rev: 1.02 9/2001 4/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

AC Test Conditions

Parameter Conditions

Input high level

Input low level
Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

V

V

= 2.4 V

IH

= 0.4 V

IL

DQ

Output Load 1

50Ω

VT = 1.4 V

GS78116B

1

30pF

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted

3. Output load 2 for tLZ, tHZ, t

OLZ

and t

OHZ

.

AC Characteristics

Read Cycle

Parameter Symbol

Min Max Min Max Min Max

Read cycle time

Address access time

t

RC

t

AA

Output Load 2

3.3 V

DQ

1

5pF

-10 -12 -15
Unit

10 — 12 — 15 — ns

— 10 — 12 — 15 ns

589Ω

434Ω

t

t

OHZ

t

AC

t

OE

t

OH

t

LZ

OLZ

t

HZ

— 10 — 12 — 15 ns

— 4 — 5 — 6 ns

3 — 3 — 3 — ns

*

*

*

*

3 — 3 — 3 — ns

0 — 0 — 0 — ns

— 5 — 6 — 7 ns

— 4 — 5 — 6 ns

Chip enable access time (CE)

Output enable to output valid (OE)

Output hold from address change

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

Rev: 1.02 9/2001 5/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Read Cycle 1:CE = OE = VIL

Address

Data Out Previous Data Data valid

Read Cycle 2: WE = VIH

Address

CE

OE

Data Out

t

OH

High impedance

GS78116B

t

RC

t

AA

t

RC

t

AA

t

AC

t

LZ

t

OE

t

OLZ

Data valid

t

t

OHZ

HZ

Rev: 1.02 9/2001 6/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Write Cycle

Address valid to end of write tAW 7 — 8 — 10 — ns

-10 -12 -15

Parameter Symbol

Unit

Min Max Min Max Min Max

Write cycle time tWC 10 — 12 — 15 — ns

Chip enable to end of write tCW 7 — 8 — 10 — ns

Data set up time tDW 5 — 6 — 7 — ns

Data hold time tDH 0 — 0 — 0 — ns

Write pulse width tWP 7 — 8 — 10 — ns

Address set up time tAS 0 — 0 — 0 — ns
Write recovery time (WE) tWR 0 — 0 — 0 — ns
Write recovery time (CE) tWR1 0 — 0 — 0 — ns

GS78116B

Output Low Z from end of write

Write to output in High Z

tWLZ

tWHZ

* These parameters are sampled and are not 100% tested.

Write Cycle 1: WE Controlled

Address

OE

CE

WE

Data In

Data Out

*

3 — 3 — 3 — ns

*

— 4 — 5 — 6 ns

t

WC

t

AW

t

CW

t

AS

t

WHZ

t

WP

High impedance

t

DW

Data valid

t

WLZ

t

WR

t

DH

Rev: 1.02 9/2001 7/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Write Cycle 2: CE Controlled

Address

t

GS78116B

WC

OE

CE

WE

Data In

Data Out

t

AW

t

AS

t

WP

t

CW

High impedance

t

DW

Data valid

t

WR1

t

DH

Rev: 1.02 9/2001 8/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Package Dimensions - 119-Pin PBGA

GS78116B

Pin 1
Corner

A

1234567

A

G

P

B

N

Top View

D

S

R

Bottom View

B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U

Package Dimensions - 119 Pin PBGA

Symbol Description Min. Nom. Max

A Width 13.8 14.0 14.2
B Length 21.8 22.0 22.2
C Package Height (including ball) — — 2.40
D Ball Size 0.60 0.75 0.90
E Ball Height 0.50 0.60 0.70
F Package Height (excluding balls) — 1.46 1.70
G Width between Balls — 1.27 —
K Package Height above board 0.80 0.90 1.00
N Cut-out Package Width — 12.00 —

K

E

F

P Foot Length — 19.50 —
R Width of package between balls — 7.62 —
S Length of package between balls — 20.32 —
T Variance of Ball Height — 0.15 —

Unit: mm

C T

Side View

BPR 1999.05.18

Rev: 1.02 9/2001 9/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Ordering Information

GS78116B

Part Number

GS78116B-10 BGA 10 ns Commercial
GS78116B-12 BGA 12 ns Commercial

GS78116B-15 BGA 15 ns Commercial
GS78116B-10I BGA 10 ns Industrial
GS78116B-12I BGA 12 ns Industrial
GS78116B-15I BGA 15 ns Industrial

* Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS78116B-12T

*

Package Access Time Temp. Range Status

Rev: 1.02 9/2001 10/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.

Asynchronous SRAM Datasheet Revision History

GS78116B

Rev. Code: Old;

New

GS78116Rev0.01a 5/1999;

1.00 X/1999

GS78116Rev 1.0010/1999A;Rev

1.01 2/2000FormatB

Rev 1.01 2/2000FormatB;

78116_r1_02

Types of Changes
Format or Content

Format/Typos

Content

Format/Content

Page #/Revisions/Reason

• p.2/Changed E to CE/consistency.

• p.2/Changed Pin T1 from BA to BD/Correction

• Added GSI Logo

• Updated format to comply with Technical Publication standards

• Finalized document and removed preliminary references

Rev: 1.02 9/2001 11/11 © 1999, Giga Semiconductor, Inc.

For latest documentation see http://www.gsitechnology.com.