Datasheet GS74116AX-8I, GS74116AX-8, GS74116AX-7I, GS74116AX-7, GS74116AJ-8I Datasheet (GSI)

GS74116ATP/J/X

SOJ, TSOP, FP-BGA

256K x 16

Commercial Temp
Industrial Temp

4Mb Asynchronous SRAM

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 150/130/105/95 mA at
minimum cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package

Description

The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL­compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II
packages.

7, 8, 10, 12 ns

3.3 V V

Center VDD and V

SOJ 256K x 16-Pin Configuration (Package J)

A
A
A
A
A

CE
DQ
DQ
DQ
DQ

V

DD

V

SS

DQ
DQ6
DQ7
DQ

WE
A
A
A

A

12

A

4

3

2

1

0

1

2

3

4

5

8

15

14

13

16

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44-pin

SOJ

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

27

26
25

24
23

A
A
A
OE
UB
LB
DQ
DQ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
A

DD

SS

5

6

7

16

15

14

13

SS

DD

12

11

10

9

8

9

10

11

17

Pin Descriptions

Symbol Description

FP-BGA 256K x 16 Bump Configuration (Package X)

123456

A0–A17 Address input

–DQ

CE

LB

UB

WE

OE

V

V

DD

SS

16

Data input/output

ALBOE A

0

1

A

A2NC

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

Ground

16

BDQ

UB A

CDQ14DQ15A

DVSSDQ13A

EVDDDQ12NC A16DQ5V

FDQ11DQ10A

GDQ9NC A

HNCA12A

3

A4CE DQ

5

A6DQ2DQ

17

A7DQ4V

8

A9DQ7DQ

10A11

13A14A15

WE DQ

1

3

DD

SS

6

8

NC

DQ1

NC No connect

6 x 10 mm Bump Pitch

Rev: 1.03 10/2002 1/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TSOP-II 256K x 16 Pin Configuration (Package TP)

GS74116ATP/J/X

Top View

DQ
DQ
DQ
DQ

V

V

DQ
DQ
DQ
DQ

WE
A

A14

A

A

A

CE

A

4

A

3

A

2

A

1

A

0

1

2

3

4

DD

SS

5

6

7

8

15

13

12

16

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44 pin

TSOP II

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

A

5

A

6

A

7

OE
UB
LB
DQ

16

DQ

15

DQ

14

DQ

13

V

SS

V

DD

DQ

12

DQ

11

DQ

10

DQ

9

NC

27

A

26

25

24

23

8

A

9

A

10

A

11

A

17

Block Diagram

A

A

CE

WE

OE

UB
LB

0

17

_____

_____

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ

1

DQ

16

Rev: 1.03 10/2002 2/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

GS74116ATP/J/X

CE OE WE LB UB DQ1 to DQ

8

DQ9 to DQ

16

H X X X X Not Selected Not Selected ISB1, ISB

L L Read Read

LLH

L H Read High Z

H L High Z Read

LL Write Write

LXL

L H Write Not Write, High Z

H L Not Write, High Z Write

L H H X X High Z High Z

L X X H H High Z High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage V

DD

–0.5 to +4.6 V

VDD Current

2

DD

I

Input Voltage V

Output Voltage V

IN

OUT

–0.5 to V

(≤ 4.6 V max.)

–0.5 to V

(≤ 4.6 V max.)

DD

DD

+0.5

+0.5

V

V

Allowable power dissipation PD 0.7 W

Storage temperature T

STG –55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Rev: 1.03 10/2002 3/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

GS74116ATP/J/X

Supply Voltage for -7/-8/-10/-12

Input High Voltage V

Input Low Voltage V

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

V

DD

IH

IL

T

Ac

I

T

A

3.0 3.3 3.6 V

2.0 —

–0.3 — 0.8 V

0—70

–40 — 85

Note:

1. Input overshoot voltage should be less than V

+2 V and not exceed 20 ns.

DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN = 0 V 5 pF

Output Capacitance C

Notes:

1. Tested at T

A = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

OUT

OUT

V

= 0 V 7 pF

V

DD

+0.3

V

o

C

o

C

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage

Current

Output Leakage

Current

Output High Voltage V

Output Low Voltage V

IIL

I

LO

OH IOH = –4 mA 2.4 —

OL ILO = +4 mA — 0.4 V

Rev: 1.03 10/2002 4/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VIN = 0 to V

Output High Z

V

OUT = 0 to V

DD

DD

– 1 uA 1 uA

–1 uA 1 uA

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ VIL

Operating

Supply

Current

Standby

Current

Standby

Current

I

I

I

SB1

SB2

DD

All other inputs

≥ V

IH or ≤ VIL

Min. cycle time

I

OUT = 0 mA

CE ≥ V

All other inputs

≥ V

IH

Min. cycle time

CE ≥ V

All other inputs

≥ V

DD

– 0.2 V or ≤ 0.2 V

or ≤ V

DD

– 0.2V

GS74116ATP/J/X

0 to 70°C –40 to 85°C

7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns

150 130 105 90 160 140 115 100 mA

IH

IL

40 30 25 25 50 40 35 35 mA

10 20 mA

Unit

AC Test Conditions

Parameter Conditions

Input high level VIH = 2.4 V

Input low level V

Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output load 2 for t

LZ

, tHZ, t

OLZ

and t

OHZ

IL = 0.4 V

DQ

Output Load 1

VT = 1.4 V

Output Load 2

DQ

5pF

1

50Ω

3.3 V

589Ω

434Ω

30pF

1

Rev: 1.03 10/2002 5/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Characteristics

Read Cycle

GS74116ATP/J/X

Parameter Symbol

Read cycle time t

Address access time t

Chip enable access time (CE

Byte enable access time (UB

Output enable to output valid (OE

)t

, LB)tAB—3—3.5—4—5ns

)tOE —3—3.5—4—5ns

Output hold from address change t

Chip enable to output in low Z (CE

Output enable to output in low Z (OE

Byte enable to output in low Z (UB

Chip disable to output in High Z (CE

Output disable to output in High Z (OE

Byte disable to output in High Z (UB

)

)

, LB)

)

)

, LB)

-7 -8 -10 -12

Min Max Min Max Min Max Min Max

RC

AA — 7 — 8 — 10 — 12 ns

AC

OH

*

t

LZ

OLZ

t

t

BLZ

*

t

HZ

t

OHZ

t

BHZ

7 — 8 — 10 — 12 — ns

— 7 — 8 — 10 — 12 ns

3—3—3—3—ns

3—3—3—3—ns

*

0—0—0—0—ns

*

0—0—0—0—ns

—3.5—4—5—6ns

*

—3—3.5—4—5ns

*

—3—3.5—4—5ns

Unit

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = V

IL

RC

t

Address

tAA

OH

t

Data Out Previous Data Data valid

Rev: 1.03 10/2002 6/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS74116ATP/J/X

Read Cycle 2: WE = V

Write Cycle

IH

Address

CE

UB, LB

OE

Data Out

High impedance

tLZ

tBLZ

tOLZ

tAA

tAC

tRC

tAB

tOE

tHZ

tBHZ

tOHZ

Data valid

Parameter Symbol

Write cycle time tWC 7 — 8 — 10 — 12 — ns

Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns

Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns

Byte enable to end of write tBW 5 — 5.5 — 7 — 8 — ns

Data set up time tDW 3.5 — 4 — 4.5 — 6 — ns

Data hold time tDH 0 — 0 — 0 — 0 — ns

Write pulse width tWP 5 — 5.5 — 7 — 8 — ns

Address set up time tAS 0 — 0 — 0 — 0 — ns

Write recovery time (WE

Write recovery time (CE

Output Low Z from end of write

Write to output in High Z

* These parameters are sampled and are not 100% tested.

) tWR 0—0—0—0—ns

) tWR10—0—0—0—ns

*

tWLZ

*

tWHZ

-7 -8 -10 -12

Min Max Min Max Min Max Min Max

3—3—3—3—ns

—3—3.5—4—5ns

Unit

Rev: 1.03 10/2002 7/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle 1: WE control

GS74116ATP/J/X

tWC

Address

Write Cycle 2: CE control

Address

OE

CE

UB, LB

WE

Data In

Data Out

tAW

tCW

tBW

tAS tWP

tWC

tWR

tDW tDH

Data valid

tWLZtWHZ

High impedance

tAW

OE

tAS tCW

CE

tBW

UB, LB

tWP

WE

tDW tDH

Data In

Data Out

Rev: 1.03 10/2002 8/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Data valid

High impedance

tWR1

Write Cycle 3: UB, LB control

Address

GS74116ATP/J/X

tWC

OE

CE

UB, LB

WE

Data In

Data Out

tAW

tAS tCW

tBW

tWP

tWR1

tDW tDH

Data valid

High impedance

Rev: 1.03 10/2002 9/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44-Pin, 400 mil SOJ

GS74116ATP/J/X

D

2344

E

122

e

c

E

H

A

A2

A

A1

y

B

B1

Detail A

L

Symbol

min nom max min nom max

A — — 0.148 — — 3.759

A1 0.025 — — 0.635 — —

E

G

Q

A2 0.105 0.110 0.115 2.667 2.794 2.921

B — 0.018 — — 0.457 —

B1 0.026 0.028 0.032 0.660 0.711 0.813

c — 0.008 — — 0.203 —

D 1.120 1.125 1.130 28.44 28.58 28.70

E 0.395 0.400 0.405 10.033 10.160 10.287

e — 0.05 — — 1.27 —

H

E 0.435 0.440 0.445 11.049 11.176 11.303

GE

0.360 0.370 0.380 9.144 9.398 9.652

L 0.082 0.087 0.106 2.083 2.210 2.70

y — — 0.004 — — 0.102

Q

o

0

—

o

7

o

0

Notes:

1. Dimension D& E do not include interlead flash

2. Dimension B1 does not include dambar protrusion / intrusion

3. Controlling dimension: inches

—

o

7

Dimension in inch Dimension in mm

Rev: 1.03 10/2002 10/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44-Pin, 400 mil TSOP-II

122

A2

A

A1

e

y

GS74116ATP/J/X

Dimension in inch Dimension in mm

D

2344

E

E

H

c

B

L1

Q

Detail A

Symbol

min nom max min nom max

A — — 0.047 — — 1.20

A1 0.002 — — 0.05 — —

A

A2 0.037 0.039 0.041 0.95 1.00 1.05

B 0.01 0.014 0.018 0.25 0.35 0.45

c — 0.006 — — 0.15 —

D 0.721 0.725 0.729 18.31 18.41 18.51

E 0.396 0.400 0.404 10.06 10.16 10.26

e — 0.031 — — 0.80 —

H

E

0.455 0.463 0.471 11.56 11.76 11.96

L 0.016 0.020 0.024 0.40 0.50 0.60

L

L1 — 0.031 — — 0.80 —

y — — 0.004 — — 0.10

Q

o

0

—

o

5

o

0

—

Notes:

1. Dimension D& E do not include interlead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Controlling dimension: mm

o

5

Rev: 1.03 10/2002 11/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

6 mm x 10 mm FP-BGA

GS74116ATP/J/X

Pin A1
Index

A

A1

D

Top View

Side View

aaa

Symbol Unit: mm

A 1.10±0.10

A1 0.20~0.30

f

b

E

c 0.36(TYP)

D 10.0±0.05

D1 5.25

E 6.0±0.05

E1 3.75

e 0.75(TYP)

aaa 0.10

f

0.30~0.40

c

Pin A1
Index

A B C D E F G H

fb

Solder Ball

1
2
3
4

e

E1

5
6

e

D1

Bottom View

Rev: 1.03 10/2002 12/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information

GS74116ATP/J/X

Part Number

GS74116ATP-7 400 mil TSOP-II 7 ns Commercial

GS74116ATP-8 400 mil TSOP-II 8 ns Commercial

GS74116ATP-10 400 mil TSOP-II 10 ns Commercial

GS74116ATP-12 400 mil TSOP-II 12 ns Commercial

GS74116ATP-7I 400 mil TSOP-II 7 ns Industrial

GS74116ATP-8I 400 mil TSOP-II 8 ns Industrial

GS74116ATP-10I 400 mil TSOP-II 10 ns Industrial

GS74116ATP-12I 400 mil TSOP-II 12 ns Industrial

GS74116AJ-7 400 mil SOJ 7 ns Commercial

GS74116AJ-8 400 mil SOJ 8 ns Commercial

GS74116AJ-10 400 mil SOJ 10 ns Commercial

GS74116AJ-12 400 mil SOJ 12 ns Commercial

GS74116AJ-7I 400 mil SOJ 7 ns Industrial

GS74116AJ-8I 400 mil SOJ 8 ns Industrial

*

Package Access Time Temp. Range Status

GS74116AJ-10I 400 mil SOJ 10 ns Industrial

GS74116AJ-12I 400 mil SOJ 12 ns Industrial

GS74116AX-7 Fine Pitch BGA 7 ns Commercial

GS74116AX-8 Fine Pitch BGA 8 ns Commercial

GS74116AX-10 Fine Pitch BGA 10 ns Commercial

GS74116AX-12 Fine Pitch BGA 12 ns Commercial

GS74116AX-7I Fine Pitch BGA 7 ns Industrial

GS74116AX-8I Fine Pitch BGA 8 ns Industrial

GS74116AX-10I Fine Pitch BGA 10 ns Industrial

GS74116AX-12I Fine Pitch BGA 12 ns Industrial

*

Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:

GS74116ATP-8T

Rev: 1.03 10/2002 13/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

4Mb Asynchronous Datasheet Revision History

GS74116ATP/J/X

Rev. Code: Old;

New

74116A_r1 Format/Content

74116A_r1; 74116A_r1_01 Content

74116A_r1_01; 74116A_r1_02 Content

74116A_r1_02; 74116A_r1_03 Content

Types of Changes
Format or Content

Page #/Revisions/Reason

• Created new datasheet

• Added 6 ns and 7 ns speed bins

• Updated power numbers

• Changed FPBGA package size from 7.2 x 11.65 mm to 6 x 10 mm

• Changed package designator from “U” to “X” for FPBGA

• Changed D3 on FPBGA pinout to A17 and E3 to NC

• Updated Recommended Operating Conditions on page 4

• Updated Read Cycle and Write Cycle AC Characteristics tables

• Removed 6 ns speed bin from entire document

Rev: 1.03 10/2002 14/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.