Datasheet GS74104TP-8I, GS74104TP-8, GS74104TP-15I, GS74104TP-15, GS74104TP-12I Datasheet (GSI)

GS74104TP/J

SOJ, TSOP

1M x 4

Commercial Temp
Industrial Temp

4Mb Asynchronous SRAM

Features

• Fast access time: 8, 10, 12, 15 ns

• CMOS low power operation: 150/125/110/90 mA at
minimum cycle time.

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 32-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package

Description

The GS74104 is a high speed CMOS Static RAM organized as
1,048,576 words by 4 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single

3.3 V power supply and all inputs and outputs are TTL-com-

patible. The GS74104 is available in 400 mil SOJ and 400 mil
TSOP Type-II packages.

Center VDD and V

SOJ 1M x 4-Pin Configuraton

A4
A3
A2
A1
A0
CE
DQ1
V

DD

V

SS

DQ2
WE
A19
A18
A17
A16
A15

TSOP-II 1M x 4-Pin Configuration

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-pin

400 mil SOJ

8, 10, 12, 15 ns

3.3 V V

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A5
A6
A7
A8
A9
OE
DQ4
V
V
DQ3
A10
A11
A12
A13
A14
NC

DD

SS

SS
DD

Pin Descriptions

Symbol Description

A0–A19 Address input

DQ1–DQ4 Data input/output

CE Chip enable input
WE Write enable input
OE Output enable input

V

DD

V

SS

NC No connect

+3.3 V power supply

Ground

NC
NC
NC
A4
A3
A2
A1
A0
CE
DQ1
V

DD

V

SS

DQ2
WE
A19
A18
A17
A16

A15
NC

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21
22

44-pin

400 mil TSOP II

44
43

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

24
23

NC
NC
NC
A5
A6
A7
A8
A9
OE
DQ4
V

SS

V

DD

DQ3
A10
A11
A12
A13
A14
NC
NC

NC
NC

Rev: 1.07 1/2001 1/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Block Diagram

GS74104TP/J

A0

A19

CE

WE

OE

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ1

DQ4

Truth Table

CE OE WE DQ1 to DQ8

H X X Not Selected ISB1, ISB2

L L H Read

VDD Current

IDDL X L Write

L H H High Z

Note: X: “H” or “L”

Rev: 1.07 1/2001 2/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD –0.5 to +4.6 V

GS74104TP/J

Input Voltage VIN

Output Voltage VOUT

–0.5 to V

(≤ 4.6 V max.)

–0.5 to V

(≤ 4.6 V max.)

DD

DD

+0.5

+0.5

V

V

Allowable power dissipation PD 0.7 W

Storage temperature TSTG –55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply Voltage for -10/12/15

Supply Voltage for -8

Input High Voltage VIH 2.0 —

Input Low Voltage VIL –0.3 — 0.8 V

V

DD

V

DD

3.0 3.3 3.6 V

3.135 3.3 3.6 V
VDD +0.3

V

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

TAc 0 — 70

TAI –40 — 85

o

C

o

C

Note:

1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Rev: 1.07 1/2001 3/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN = 0 V 5 pF

Output Capacitance COUT VOUT = 0 V 7 pF

Notes:

1. Tested at TA = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

GS74104TP/J

Input Leakage

Current

Output Leakage

Current

Output High Voltage VOH IOH = –4mA 2.4 —

Output Low Voltage VOL ILO = +4mA — 0.4 V

IIL

ILO

VIN = 0 to V

Output High Z

VOUT = 0 to V

DD

DD

– 1 uA 1 uA

–1 uA 1 uA

Rev: 1.07 1/2001 4/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ VIL

Operating

Supply

Current

Standby

Current

IDD (max)

ISB1 (max)

All other inputs

≥ VIH or ≤ VIL

Min. cycle time

IOUT = 0 mA

CE ≥ VIH

All other inputs

≥ VIH or ≤VIL

Min. cycle time

GS74104TP/J

0 to 70°C –40 to 85°C

8 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns

150 mA 125 mA 110 mA 90 mA 135 mA 120 mA 100 mA

70 mA 65 mA 60 mA 55 mA 75 mA 70 mA 65 mA

Standby

Current

ISB2 (max)

CE ≥ VDD - 0.2V

All other inputs

≥ VDD - 0.2V or ≤ 0.2V

AC Test Conditions

Parameter Conditions

Input high level VIH = 2.4 V

Input low level VIL = 0.4 V
Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ

30 mA 40 mA

Output Load 1

DQ

50Ω

VT = 1.4 V

Output Load 2

3.3 V

DQ

5pF

589Ω

1

434Ω

30pF

1

Rev: 1.07 1/2001 5/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Characteristics

Read Cycle

Parameter Symbol

Read cycle time tRC 8 — 10 — 12 — 15 — ns

Address access time tAA — 8 — 10 — 12 — 15 ns

Chip enable access time (CE) tAC — 8 — 10 — 12 — 15 ns

Output enable to output valid (OE) tOE — 3.5 — 4 — 5 — 6 ns

Output hold from address change tOH 3 — 3 — 3 — 3 — ns

GS74104TP/J

-8 -10 -12 -15
Unit

Min Max Min Max Min Max Min Max

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = V

Address

Data Out Previous Data Data valid

IH

tLZ

tOLZ

tHZ

tOHZ

*

*

*

*

tOH

3 — 3 — 3 — 3 — ns

0 — 0 — 0 — 0 --- ns

— 4 — 5 — 6 — 7 ns

— 3.5 — 4 — 5 — 6 ns

tRC

tAA

Rev: 1.07 1/2001 6/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS74104TP/J

Read Cycle 2: WE = V

Write Cycle

Parameter Symbol

IH

Address

CE

OE

Data Out

High impedance

tRC

tAA

tAC

tLZ

tOLZ

tOE

DATA VALID

tHZ

tOHZ

-8 -10 -12 -15

Min Max Min Max Min Max Min Max

Unit

Write cycle time tWC 8 — 10 — 12 — 15 — ns

Address valid to end of write tAW 5.5 — 7 — 8 — 10 — ns

Chip enable to end of write tCW 5.5 — 7 — 8 — 10 — ns

Data set up time tDW 4 — 5 — 6 — 7 — ns

Data hold time tDH 0 — 0 — 0 — 0 — ns

Write pulse width tWP 5.5 — 7 — 8 — 10 — ns

Address set up time tAS 0 — 0 — 0 — 0 — ns
Write recovery time (WE) tWR 0 — 0 — 0 — 0 — ns
Write recovery time (CE) tWR1 0 — 0 — 0 — 0 — ns

Output Low Z from end of write

Write to output in High Z

* These parameters are sampled and are not 100% tested.

tWLZ

tWHZ

*

3 — 3 — 3 — 3 — ns

*

— 3.5 — 4 — 5 — 6 ns

Rev: 1.07 1/2001 7/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle 1: WE control

Address

GS74104TP/J

tWC

CE

WE

Data In

Data Out

Write Cycle 2: CE control

Address

OE

CE

OE

tAW

tCW

tAS tWP

tWC

tAW

tAS tCW

tWR

tDW tDH

DATA VALID

tWLZtWHZ

HIGH IMPED ANCE

tWR1

tWP

WE

tDW tDH

Data In

Data Out

DATA VALID

HIGH IMPED ANCE

Rev: 1.07 1/2001 8/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

32-Pin SOJ, 400 mil

1

e

A2

A

A1

GS74104TP/J

Dimension in inch Dimension in mm

Symbol

L

D

c

A — — 0.146 — — 3.70
A1 0.026 — — 0.66 — —
A2 0.105 0.110 0.115 2.67 2.80 2.92

E

HE

GE

B 0.013 0.017 0.021 0.33 0.43 0.53
B1 0.024 0.028 0.032 0.61 0.71 0.81

A

c 0.006 0.008 0.012 0.15 0.20 0.30

D 0.820 0.824 0.829 20.83 20.93 21.06

E 0.395 0.400 0.405 10.04 10.16 10.28

e — 0.05 — — 1.27 —

y

B

B1

Detail A

HE 0.430 0.435 0.440 10.93 11.05 11.17

Q

GE 0.354 0.366 0.378 9.00 9.30 9.60

L 0.082 — — 2.08 — —

y — — 0.004 — — 0.10

Q

Note:

1. Dimension D& E do not include interlead flash.

2. Dimension B1 does not include dambar protrusion/intrusion.

3. Controlling dimension: inches

min nom max min nom max

o

0

—

10

o

o

0

—

10

o

Rev: 1.07 1/2001 9/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44-Pin, 400 mil TSOP-II

1 22

A

A1 A2

e

y

GS74104TP/J

Dimension in inch Dimension in mm

D

2344

c

Symbol

A — — 0.047 — — 1.20
A1 0.002 — — 0.05 — —
A2 0.037 0.039 0.041 0.95 1.00 1.05

E

HE

A

B 0.01 0.014 0.018 0.25 0.35 0.45

c — 0.006 — — 0.15 —

D 0.721 0.725 0.729 18.31 18.41 18.51

B

E 0.396 0.400 0.404 10.06 10.16 10.26

e — 0.031 — — 0.80 —
HE 0.455 0.463 0.471 11.56 11.76 11.96

L 0.016 0.020 0.024 0.40 0.50 0.60
L1 — 0.031 — — 0.80 —

L1

Detail A

L

Q

y — — 0.004 — — 0.10

Q

Note:

1. Dimension D& E do not include interlead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Controlling dimension: mm

min nom max min nom max

o

0

—

o

5

o

0

—

o

5

Rev: 1.07 1/2001 10/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information

GS74104TP/J

Part Number

GS74104TP-8 400 mil TSOP-II 8 ns Commercial
GS74104TP-10 400 mil TSOP-II 10 ns Commercial
GS74104TP-12 400 mil TSOP-II 12 ns Commercial
GS74104TP-15 400 mil TSOP-II 15 ns Commercial

GS74104TP-8I 400 mil TSOP-II 8 ns Industrial
GS74104TP-10I 400 mil TSOP-II 10 ns Industrial
GS74104TP-12I 400 mil TSOP-II 12 ns Industrial
GS74104TP-15I 400 mil TSOP-II 15 ns Industrial

GS74104J-8 400 mil SOJ 8 ns Commercial
GS74104J-10 400 mil SOJ 10 ns Commercial
GS74104J-12 400 mil SOJ 12 ns Commercial
GS74104J-15 400 mil SOJ 15 ns Commercial
GS74104J-8I 400 mil SOJ 8 ns Industrial

GS74104J-10I 400 mil SOJ 10 ns Industrial

*

Package Access Time Temp. Range Status

GS74104J-12I 400 mil SOJ 12 ns Industrial
GS74104J-15I 400 mil SOJ 15 ns Industrial

*

Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:

GS74104TP-8T

Rev: 1.07 1/2001 11/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision History

GS74104TP/J

Rev. Code: Old;

New

GS74104Rev1.05 1/2000K;Rev 6
2/2000L

74104_r1_06; 74104_r1_07 Format

Types of Changes

Format or Content

Format/Content

Page #/Revisions/Reason

• GSI Logo

• Updated format to comply with Technical Publications standard

• Specifically noted that numbers in Power Supply Currents table are worst
case scenario

• Corrected package reference on page 9 (replaced 300 mil diagram with 400
mil diagram)

Rev: 1.07 1/2001 12/12 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.