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GS72108J-8I
Datasheet (GSI)
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Datasheet GS72108TP-8I, GS72108TP-8, GS72108TP-15I, GS72108TP-15, GS72108TP-12I Datasheet (GSI)

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Page 1
GS72108TP/J
SOJ, TSOP
256K x 8
Commercial Temp Industrial Temp
2Mb Asynchronous SRAM

Features

• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 150/125/110/90 mA at minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 36-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package

Description

The GS72108 is a high speed CMOS Static RAM organized as 262,144 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-com-
patible. The GS72108 is available in 400 mil SOJ and 400 mil TSOP Type-II packages.

SOJ 256K x 8-Pin Configuration

A
A
A
A
A
CE
DQ
DQ
V
V
DQ
DQ
WE
A
A
A
A
A
4
3
2
1
0
1
2
DD
SS
3
4
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36-pin
400 mil SOJ
8, 10, 12, 15 ns
3.3 V V
Center VDD and V
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
A
A
A
OE
DQ
DQ
V
V
DQ
DQ
A
A
A
A
NC
NC
5
6
7
8
SS
DD
9
10
11
12
DD
SS
8
7
6
5

Pin Descriptions

Symbol Description
17
A0–A
DQ
1–DQ8 Data input/output
CE
WE
OE
V
DD
V
SS
NC No connect
Address input
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
Rev: 1.08 7/2002 1/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 2

TSOP-II 256K x 8-Pin Configuration

GS72108TP/J
NC NC
A A A A A CE DQ DQ
V V DQ DQ WE
A
A
A A
A
NC NC
1
2
4
3
2
1
0
1
2
DD
SS
3
4
17
16
15
14
13
3 4
5 6 7 8
9 10 11 12 13
14 15 16 17
18
19 20
21
22
44-pin
400 mil TSOP II
44
43 42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC NC
NC A A A A OE DQ DQ
V V DQ DQ
A A A NC
NC
NC NC
5
6
7
8
8
7
SS
DD
6
5
A
9
10
11
12
Block Diagram
A
A
CE
WE
OE
0
Row
Memory Array
Decoder
Address
Input
Buffer
Column
17
Control
Decoder
I/O Buffer
1
DQ
DQ
8
Rev: 1.08 7/2002 2/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 3

Truth Table

GS72108TP/J
CE OE WE DQ1 to DQ
8
H X X Not Selected ISB1, ISB
L L H Read
LX L Write
LH H High Z
Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
Input Voltage V
Output Voltage V
IN
OUT
–0.5 to V
(≤ 4.6 V max.)
–0.5 to V
(≤ 4.6 V max.)
DD
DD
+0.5
+0.5
V
V
VDD Current
2
I
DD
Allowable power dissipation PD 0.7 W
Storage temperature T
STG
–55 to 150
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.08 7/2002 3/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 4

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit
GS72108TP/J
Supply Voltage for -10/12/15
Supply Voltage for -8
Input High Voltage V
Input Low Voltage V
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
V
DD
V
DD
IH
IL
T
Ac 0 — 70
T
AI
3.0 3.3 3.6 V
3.135 3.3 3.6 V
2.0 —
–0.3 — 0.8 V
–40 — 85
Note:
1. Input overshoot voltage should be less than V
+2 V and not exceed 20 ns.
DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Max Unit
V
DD
+0.3
V
o
C
o
C
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance C
OUT VOUT = 0 V 7 pF
Notes:
1. Tested at T
A = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max
Input Leakage
Current
Output Leakage
Current
Output High Voltage V
Output Low Voltage V
IIL
I
LO
OH
OL
Rev: 1.08 7/2002 4/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
VIN = 0 to V
DD
Output High Z
V
OUT = 0 to V
OH
I
LO
I
DD
= –4mA 2.4 —
= +4mA — 0.4 V
– 1 uA 1 uA
–1 uA 1 uA
Page 5
Power Supply Currents
Parameter Symbol Test Conditions
≤ V
CE
Operating
Supply
Current
Standby Current
Standby Current
I
DD
(max)
SB1 (max)
I
ISB2 (max)
All other inputs
≥ V
IH
or ≤ V
Min. cycle time
I
OUT
= 0 mA
≥ VIH
CE
All other inputs
≥ V
IH or ≤VIL
Min. cycle time
CE
≥ V
- 0.2 V
DD
All other inputs
– 0.2 V or
≥ V
DD
≤ 0.2 V
GS72108TP/J
0 to 70°C –40 to 85°C
8 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns
IL
IL
150 mA 125 mA 110 mA 90 mA 135 mA 120 mA 100 mA
55 mA 50 mA 45 mA 40 mA 60 mA 55 mA 50 mA
15 mA 25 mA

AC Test Conditions

Parameter Conditions
Input high level VIH = 2.4 V
Input low level V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load
Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in unless otherwise noted.
3. Output load 2 for t
LZ, tHZ, tOLZ and tOHZ
IL = 0.4 V
Fig. 1& 2
Fig. 1
Output Load 1
DQ
1
50Ω
30pF
VT = 1.4 V
Output Load 2
3.3 V
DQ
5pF
589Ω
1
434Ω
Rev: 1.08 7/2002 5/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 6

AC Characteristics

Read Cycle

Parameter Symbol
GS72108TP/J
-8 -10 -12 -15 Unit
Min Max Min Max Min Max Min Max
t
t
RC
AA
OE
OH
t
LZ
OLZ
t
HZ
OHZ
*
*
*
*
Read cycle time t
Address access time t
Chip enable access time (CE
Output enable to output valid (OE
)tAC — 8 — 10 — 12 — 15 ns
)t
Output hold from address change t
Chip enable to output in low Z (CE
Output enable to output in low Z (OE
Chip disable to output in High Z (CE
Output disable to output in High Z (OE
)
)
)
)
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = V
IH
Address
8 — 10 — 12 — 15 — ns
— 8 — 10 — 12 — 15 ns
— 3.5 — 4 — 5 — 6ns
3 — 3 — 3 — 3 — ns
3 — 3 — 3 — 3 — ns
0 — 0 — 0 — 0 — ns
— 4 — 5 — 6 — 7ns
— 3.5 — 4 — 5 — 6ns
RC
t
AA
t
tOH
Data Out Previous Data Data valid
Rev: 1.08 7/2002 6/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 7
GS72108TP/J
Read Cycle 2: WE = V

Write Cycle

Parameter Symbol
IH
Address
CE
OE
Data Out
High impedance
tRC
AA
t
AC
t
HZ
ATA VALID
t
t
OHZ
LZ
t
OE
t
tOLZ
D
-8 -10 -12 -15
Min Max Min Max Min Max Min Max
Unit
Write cycle time tWC 8 — 10 — 12 — 15 — ns
Address valid to end of write tAW 5.5 — 7 — 8 — 10 — ns
Chip enable to end of write tCW 5.5 — 7 — 8 — 10 — ns
Data set up time tDW 4 — 5 — 6 — 7 — ns
Data hold time tDH 0 — 0 — 0 — 0 — ns
Write pulse width tWP 5.5 — 7 — 8 — 10 — ns
Address set up time tAS 0 — 0 — 0 — 0 — ns
Write recovery time (WE
Write recovery time (CE
Output Low Z from end of write
Write to output in High Z
)tWR0— 0 — 0 — 0 — ns
)tWR10— 0 — 0 — 0 — ns
tWLZ
tWHZ
* These parameters are sampled and are not 100% tested.
*
3 — 3 — 3 — 3 — ns
*
— 3.5 — 4 — 5 — 6ns
Rev: 1.08 7/2002 7/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 8

Write Cycle 1: WE control

Address
GS72108TP/J
WC
t
CE
WE
Data In
Data Out

Write Cycle 2: CE control

Address
OE
CE
OE
tAW
tCW
AS
t
tWC
AW
t
tAS tCW
WP
t
DW
t
D
IGH IMPEDANCE
H
ATA VALID
tWR
DH
t
tWLZtWHZ
WR1
t
tWP
WE
Data In
Data Out
DW
t
D
IGH IMPEDANCE
H
ATA VALID
DH
t
Rev: 1.08 7/2002 8/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 9

36-Pin SOJ, 400 mil

1
A2
A
A1
GS72108TP/J
Dimension in inch Dimension in mm
Symbol
L
D
c
A ——0.146 ——3.70
A1 0.026 ——0.66 ——
A2 0.105 0.110 0.115 2.67 2.80 2.92
E
E
H
E
G
B 0.013 0.017 0.021 0.33 0.43 0.53
B1 0.024 0.028 0.032 0.61 0.71 0.81
c 0.006 0.008 0.012 0.15 0.20 0.30
e
A
D 0.920 0.924 0.929 23.37 23.47 23.60
E 0.395 0.400 0.405 10.04 10.16 10.28
e — 0.05 ——1.27 —
H
y
B
B1
Detail A
Q
E
G
L 0.082 ——2.08 ——
y ——0.004 ——0.10
Q
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
min nom max min nom max
0.430 0.435 0.440 10.93 11.05 11.17
E 0.354 0.366 0.378 9.00 9.30 9.60
o
0
—
10
o
o
0
—
10
o
Rev: 1.08 7/2002 9/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 10

44-Pin, 400 mil TSOP-II

122
A2
A
A1
e
y
GS72108TP/J
Dimension in inch Dimension in mm
D
2344
c
Symbol
A ——0.047 ——1.20
A1 0.002 ——0.05 ——
A2 0.037 0.039 0.041 0.95 1.00 1.05
E
E
H
A
B 0.01 0.014 0.018 0.25 0.35 0.45
c — 0.006 ——0.15 —
D 0.721 0.725 0.729 18.31 18.41 18.51
B
E 0.396 0.400 0.404 10.06 10.16 10.26
e — 0.031 ——0.80 —
H
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 — 0.031 ——0.80 —
L1
Detail A
L
Q
y ——0.004 ——0.10
Q
Note:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
min nom max min nom max
E
0.455 0.463 0.471 11.56 11.76 11.96
o
0
—
o
5
o
0
—
o
5
Rev: 1.08 7/2002 10/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 11

Ordering Information

GS72108TP/J
Part Number
GS72108TP-8 400 mil TSOP-II 8 ns Commercial
GS72108TP-10 400 mil TSOP-II 10 ns Commercial
GS72108TP-12 400 mil TSOP-II 12 ns Commercial
GS72108TP-15 400 mil TSOP-II 15 ns Commercial
GS72108TP-8I 400 mil TSOP-II 8 ns Industrial
GS72108TP-10I 400 mil TSOP-II 10 ns Industrial
GS72108TP-12I 400 mil TSOP-II 12 ns Industrial
GS72108TP-15I 400 mil TSOP-II 15 ns Industrial
GS72108J-8 400 mil SOJ 8 ns Commercial
GS72108J-10 400 mil SOJ 10 ns Commercial
GS72108J-12 400 mil SOJ 12 ns Commercial
GS72108J-15 400 mil SOJ 15 ns Commercial
GS72108J-8I 400 mil SOJ 8 ns Industrial
GS72108J-10I 400 mil SOJ 10 ns Industrial
*
Package Access Time Temp. Range Status
GS72108J-12I 400 mil SOJ 12 ns Industrial
GS72108J-15I 400 mil SOJ 15 ns Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS72108TP-8T
Rev: 1.08 7/2002 11/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Page 12

Revision History

GS72108TP/J
Rev. Code: Old;
New
72108 1.04d 5/1999/721081.05 1/ 2000 Content
GS72108Rev1.05 10/19991/ 2000K;Rev 5 2/2000L
721081.05 1/2000 Content
72108_r1_07; 72108_r1_08 Content
Types of Changes Format or Content
Format/Content
Format
Page #/Revisions/Reason
• Page 2/Pins 16–20 and 26–30 on 44-pin TSOP II Pin Configuration/ Correction
• GSI Logo
• Corrected TSOP-II pin configuration diagram (A17–A13 in lower left quadrant; A9–A12, A18 in lower right quadrant)
• Updated format to comply with Technical Publications standard
• Specifically noted that numbers in Power Supply Currents table are worst case scenario
• Removed all references to “U” package
Rev: 1.08 7/2002 12/12 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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