Datasheet GS71116AU-8I, GS71116AU-8, GS71116ATP-12I, GS71116ATP-12, GS71116ATP-10I Datasheet (GSI)

GS71116ATP/J/U

SOJ, TSOP, FP-BGA

64K x 16

Commercial Temp
Industrial Temp

1Mb Asynchronous SRAM

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

Description

The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single

3.3 V power supply and all inputs and outputs are TTL-

compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.

Pin Descriptions

Symbol Description

0–A15

A

DQ

1–DQ16 Data input/output

CE

LB

UB

WE

OE

V

DD

V

SS

NC No connect

Address input

Chip enable input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Write enable input

Output enable input

+3.3 V power supply

Ground

7, 8, 10, 12 ns

3.3 V V

Center VDD and V

SOJ 64K x 16-Pin Configuration

A
A
A
A
A

CE
DQ
DQ
DQ
DQ

V

DD

V

SS

DQ
DQ6
DQ7
DQ

WE
A
A
A

A

12

4

3

2

1

0

1

2

3

4

5

8

15

14

13

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44-pin

SOJ

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

27

26
25

24
23

Package J

Fine Pitch BGA 64K x 16-Bump Configuration

123456

0

ALB

OE A

BDQ16UB A

CDQ14DQ15A

V

D

E

DQ13NC A7DQ

SS

V

DQ12NC NC DQ

DD

FDQ11DQ10A

GDQ9NC A

HNCA12A

1

A

3

A4CE DQ

5

A6DQ2DQ

8

A9DQ7DQ

10A11

13A14A15

WE DQ

A2NC

V

4

V

5

NC

A
A
A
OE
UB
LB
DQ
DQ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
NCNC

DD

SS

DD

SS

5

6

7

16

15

14

13

SS

DD

12

11

10

9

8

9

10

11

1

3

6

8

6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)

Rev: 1.04a 10/2002 1/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TSOP-II 64K x 16-Pin Configuration

GS71116ATP/J/U

Top View

DQ
DQ
DQ
DQ

V

V

DQ
DQ
DQ
DQ

WE
A

A14

A

A

CE

A

4

A

3

A

2

A

1

A

0

1

2

3

4

DD

SS

5

6

7

8

15

13

12

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15

16
17
18

19
20
21
22

Top view

44-pin

TSOP II

44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29
28

27

26

25

24

23

A
A
A
OE
UB
LB
DQ
DQ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
NCNC

5

6

7

16

15

14

13

SS

DD

12

11

10

9

8

9

10

11

Package TP

Block Diagram

A

A

CE

WE

OE

UB
LB

0

15

_____

_____

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ

1

DQ

16

Rev: 1.04a 10/2002 2/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

GS71116ATP/J/U

CE OE WE LB UB DQ1 to DQ

8

DQ9 to DQ

16

H X X X X Not Selected Not Selected ISB1, ISB

L L Read Read

LLH

L H Read High Z

H L High Z Read

LL Write Write

LXL

L H Write Not Write, High Z

H L Not Write, High Z Write

L H H X X High Z High Z

L X X H H High Z High Z

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage V

DD

–0.5 to +4.6 V

VDD Current

2

I

DD

Input Voltage V

Output Voltage V

IN

OUT

–0.5 to V

(≤ 4.6 V max.)

–0.5 to V

(≤ 4.6 V max.)

DD

DD

+0.5

+0.5

V

V

Allowable power dissipation PD 0.7 W

Storage temperature T

STG –55 to 150

o

C

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Rev: 1.04a 10/2002 3/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

GS71116ATP/J/U

Supply Voltage for -7/-8/-10/-12

Input High Voltage V

Input Low Voltage V

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

V

DD

IH

IL

T

Ac

I

T

A

3.0 3.3 3.6 V

2.0 —

–0.3 — 0.8 V

0 — 70

–40 — 85

Notes:

1. Input overshoot voltage should be less than V

+2 V and not exceed 20 ns.

DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance C

Output Capacitance C

IN

OUT

Notes:

1. Tested at T

A

= 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

IN

V

= 0 V 5 pF

OUT

V

= 0 V 7 pF

V

DD

+0.3

V

o

C

o

C

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current I

Output Leakage

Current

Output High Voltage V

Output Low Voltage V

IL

LO

I

OH

OL ILO = +4 mA 0.4V

Rev: 1.04a 10/2002 4/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VIN = 0 to V

DD

Output High Z

V

OUT = 0 to V

OH

I

DD

= –4 mA 2.4

–1 uA 1uA

–1 uA 1uA

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ V

Operating

Supply

Current

Standby

Current

IDD

I

SB1

All other inputs

≥ VIH

or ≤ V

Min. cycle time

IOUT

= 0 mA

CE ≥ V

All other inputs

≥ V

IH

or ≤V

Min. cycle time

GS71116ATP/J/U

0 to 70°C –40 to 85°C

7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns

IL

IL

IH

IL

145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA

25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA

Standby

Current

I

SB2

CE ≥ VDD – 0.2 V

All other inputs

≥ V

DD – 0.2 V or ≤ 0.2 V

2 mA 5 mA

Rev: 1.04a 10/2002 5/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Test Conditions

Parameter Conditions

Input high level VIH = 2.4 V

Input low level V

I L

= 0.4 V

DQ

GS71116ATP/J/U

Output Load 1

50Ω

30pF

1

Input rise time tr = 1V/ns

Input fall time tf = 1 V/ns

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output load 2 for t

LZ, tHZ, tOLZ and tOHZ

VT = 1.4 V

Output Load 2

DQ

5pF

1

3.3 V

589Ω

434Ω

Rev: 1.04a 10/2002 6/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Characteristics

Read Cycle

GS71116ATP/J/U

Parameter Symbol

Read cycle time t

Address access time t

Chip enable access time (CE

Byte enable access time (UB

Output enable to output valid (OE

)tAC—7—8—10—12ns

, LB)tAB—3—3.5— 4 — 5 ns

)tOE —3—3.5— 4 — 5 ns

Output hold from address change t

Chip enable to output in low Z (CE

Output enable to output in low Z (OE

Byte enable to output in low Z (UB

Chip disable to output in High Z (CE

Output disable to output in High Z (OE

Byte disable to output in High Z (UB

)

)

, LB)

)

)

, LB)

-7 -8 -10 -12
Unit

Min Max Min Max Min Max Min Max

RC

AA —7—8—10—12ns

OH

*

t

LZ

*

OLZ

t

*

t

BLZ

*

t

HZ

*

t

OHZ

*

t

BHZ

7—8—10— 12 — ns

3—3—3 — 3 —ns

3—3—3 — 3 —ns

0—0—0 — 0 —ns

0—0—0 — 0 —ns

—3.5— 4 — 5 — 6 ns

—3—3.5— 4 — 5 ns

—3—3.5— 4 — 5 —

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = V

IL

RC

t

Address

tAA

OH

t

Data Out Previous Data Data valid

Rev: 1.04a 10/2002 7/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71116ATP/J/U

Read Cycle 2: WE = V

Write Cycle

IH

Address

CE

UB, LB

OE

Data Out

High impedance

tLZ

tBLZ

tOLZ

tAA

tAC

tRC

tAB

tOE

tHZ

tBHZ

tOHZ

Data valid

-7 -8 -10 -12

Parameter Symbol

MinMaxMinMaxMinMaxMinMax

Write cycle time tWC 7 — 8 — 10 — 12 — ns

Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns

Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns

Byte enable to end of write tBW 5 — 5.5 — 7 — 8 — ns

Data set up time tDW 3.5 — 4 — 5 — 6 — ns

Data hold time tDH 0 — 0 — 0 — 0 — ns

Write pulse width tWP 5 — 5.5 — 7 — 8 — ns

Address set up time tAS 0 — 0 — 0 — 0 — ns

Write recovery time (WE

Write recovery time (CE

Output Low Z from end of write

Write to output in High Z

* These parameters are sampled and are not 100% tested.

) tWR 0—0—0—0—ns

) tWR10—0—0—0—ns

tWLZ

tWHZ

*

*

3—3—3—3—ns

—3—3.5—4—5ns

Unit

Rev: 1.04a 10/2002 8/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle 1: WE control

GS71116ATP/J/U

tWC

Address

Write Cycle 2: CE control

Address

OE

CE

UB, LB

WE

Data In

Data Out

tAW

tCW

tBW

tAS tWP

tWC

tWR

tDW tDH

Data valid

tWLZtWHZ

High impedance

tAW

OE

tAS tCW

CE

tBW

UB, LB

tWP

WE

tDW tDH

Data In

Data Out

Rev: 1.04a 10/2002 9/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Data valid

High impedance

tWR1

Write Cycle 3: UB, LB control

Address

GS71116ATP/J/U

tWC

OE

CE

UB, LB

WE

Data In

Data Out

tAW

tAS tCW

tBW

tWP

tWR1

tDW tDH

Data valid

High impedance

Rev: 1.04a 10/2002 10/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44-Pin, 400 mil SOJ

GS71116ATP/J/U

D

2344

E

122

e

c

E

H

A

A2

A

A1

y

B

B1

Detail A

L

Symbol

Dimension in inch Dimension in mm

min nom max min nom max

A — — 0.148 — — 3.759

A1 0.025 — — 0.635 — —

A2 0.105 0.110 0.115 2.667 2.794 2.921

E

G

B — 0.018 — — 0.457 —

B1 0.026 0.028 0.032 0.660 0.711 0.813

c — 0.008 — — 0.203 —

D 1.120 1.125 1.130 28.44 28.58 28.70

E 0.395 0.400 0.405 10.033 10.160 10.287

e — 0.05 — — 1.27 —

H

E

0.435 0.440 0.445 11.049 11.176 11.303

G

E 0.360 0.370 0.380 9.144 9.398 9.652

Q

L 0.082 0.087 0.106 2.083 2.210 2.70

y — — 0.004 — — 0.102

Q

o

0

—

o

7

o

0

—

o

7

Notes:

1. Dimension D& E do not include interlead flash.

2. Dimension B1 does not include dambar protrusion/intrusion.

3. Controlling dimension: inches

Rev: 1.04a 10/2002 11/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

44 Pin, 400 mil TSOP-II

GS71116ATP/J/U

D

2344

E

E

H

122

e

B

A2

A

A1

y

L1

Detail A

Symbol

c

Dimension in inch Dimension in mm

min nom max min nom max

A — — 0.047 — — 1.20

A1 0.002 — — 0.05 — —

A2 0.037 0.039 0.041 0.95 1.00 1.05

A

B 0.01 0.014 0.018 0.25 0.35 0.45

c — 0.006 — — 0.15 —

D 0.721 0.725 0.729 18.31 18.41 18.51

E 0.396 0.400 0.404 10.06 10.16 10.26

e — 0.031 — — 0.80 —

H

E

0.455 0.463 0.471 11.56 11.76 11.96

L 0.016 0.020 0.024 0.40 0.50 0.60

L1 — 0.031 — — 0.80 —

L

Q

y — — 0.004 — — 0.10

Q

o

0

—

o

5

o

0

—

5

o

Notes:

1. Dimension D& E do not include interlead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Controlling dimension: mm

Rev: 1.04a 10/2002 12/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

6 mm x 8 mm Fine Pitch BGA

pin A1 index

GS71116ATP/J/U

8.00 ± 0.10

6.00 ± 0.10

units: mm

1.20(max)

A

B

0.22 ± 0.05

pin A1 index

Bottom View Top View

654321

D

0.10

F

C

E

D

H

G

0.36(typ)

3.75

0.75(typ).

5.25

Ball Dia. 0.35

Pitch 0.75

Rev: 1.04a 10/2002 13/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information

GS71116ATP/J/U

Part Number

GS71116ATP-7 400 mil TSOP-II 7 ns Commercial

GS71116ATP-8 400 mil TSOP-II 8 ns Commercial

GS71116ATP-10 400 mil TSOP-II 10 ns Commercial

GS71116ATP-12 400 mil TSOP-II 12 ns Commercial

GS71116ATP-7I 400 mil TSOP-II 7 ns Industrial

GS71116ATP-8I 400 mil TSOP-II 8 ns Industrial

GS71116ATP-10I 400 mil TSOP-II 10 ns Industrial

GS71116ATP-12I 400 mil TSOP-II 12 ns Industrial

GS71116AJ-7 400 mil SOJ 7 ns Commercial

GS71116AJ-8 400 mil SOJ 8 ns Commercial

GS71116AJ-10 400 mil SOJ 10 ns Commercial

GS71116AJ-12 400 mil SOJ 12 ns Commercial

GS71116AJ-7I 400 mil SOJ 7 ns Industrial

GS71116AJ-8I 400 mil SOJ 8 ns Industrial

*

Package Access Time Temp. Range Status

GS71116AJ-10I 400 mil SOJ 10 ns Industrial

GS71116AJ-12I 400 mil SOJ 12 ns Industrial

GS71116AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial

GS71116AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial

GS71116AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial

GS71116AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial

GS71116AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial

GS71116AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial

GS71116AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial

GS71116AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial

*

Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:

GS71116ATP-10T

Rev: 1.04a 10/2002 14/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1Mb Asynchronous Datasheet Revision History

GS71116ATP/J/U

Rev. Code: Old;

New

71116A_r1

71116A_r1; 71116_r1_01 Content

71116A_r1_01; 71116A
_r1_02

71116A_r1_02; 71116A
_r1_03

71116A_r1_03; 71116A
_r1_04

Types of Changes
Format or Content

Content

Content

Content

Page #/Revisions/Reason

• Creation of new datasheet

• Added 6 ns speed bin to entire document

• Updated all power numbers

• Changed 6 mm x 10 mm FPBGA package designator from U to X

• Updated Recommended Operating Conditions table on page 4

• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)

• Updated Read Cycle AC Characteristics table

• Removed 6 ns speed bin from entire document

• Added 7 ns speed bin to entire document

Rev: 1.04a 10/2002 15/15 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.