Datasheet GS71024U-8I, GS71024U-8, GS71024U-15I, GS71024U-15, GS71024U-12I Datasheet (GSI)

GS71024T/U

TQFP, FPBGA

64K x 24

Commercial Temp
Industrial Temp

1.5Mb Asynchronous SRAM

Features

• Fast access time: 8, 10, 12, 15 ns

• CMOS low power operation: 190/160/130/110 mA at
minimum cycle time.

• Single 3.3 V ± 0.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40 to 85°C

• Package

T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array

Description

The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL­compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.

Fine Pitch BGA Bump Configuration

1 2 3 4 5 6

A

DQ A3 A2 A1 A0 DQ

B

DQ DQ CE2 WE DQ DQ

C

DQ DQ CE1 OE DQ DQ

V

D

E

F

G

H

6 mm x 8 mm, 0.75 mm Bump Pitch

DQ A5 A4 DQ

SS

V

DQ A7 A6 DQ

DD

DQ DQ A9 A8 DQ DQ

DQ DQ A11 A10 DQ DQ

DQ A15 A14 A13 A12 DQ

Top View

8, 10, 12, 15 ns

3.3 V V

V

DD

V

SS

DD

Pin Descriptions

Symbol Description Symbol Description

A0 to A15 Address input DQ1 to DQ24 Data input/output

X/Y Vector Input V/S Address Multiplexer Control

WE Write enable input OE Output enable input

CE1, CE2 Chip enable input — —

V

DD

Block Diagram

A14

A15

X/Y
V/S

CE1
CE2

WE

OE

+3.3 V power supply

A0

Address

Input

0

Q

1

Control

Row

Decoder

V

SS

Memory Array

1024 x 1536

Column
Decoder

I/O Buffer

DQ1 DQ24

Ground

Rev: 1.03 11/2000 1/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

100-Pin TQFP Pinout

GS71024T/U

DD

A14

CE2

CE1

A15

NC

NC

V/S

NC

X/Y

SS

V

V

NC

WE

OE

NC

NC

A0

A1

NC

NC

NC
NC
NC

NC

NC
DQ13
DQ14
DQ15
DQ16

V

SS

V

DD

DQ17
DQ18

NC

V

DD

NC

V

SS

DQ19
DQ20

V

DD

V

SS

DQ21
DQ22
DQ23
DQ24

NC

NC

NC

NC

NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

2
3

4
5
6

7
8

9
10
11

12
13

14
15
16

17
18
19

20
21

22
23
24

25
26

27
28
29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Top View

80
79
78

77
76
75

74
73
72

71
70
69
68

67
66
65

64
63
62

61
60
59

58
57
56

55
54
53
52

51

NC
NC
NC
NC
NC
DQ12
DQ11
DQ10
DQ9
V

SS

V

DD

DQ8
DQ7
V

SS

NC
V

DD

NC
DQ6
DQ5
V

DD

V

SS

DQ4
DQ3
DQ2
DQ1
NC
NC
NC
NC
NC

SS

A9

NC

A11

A13

A12

A8

A10

NC

DD

NC

V

V

A7

A6

A5

A4

A3

NC

NC

NC

A2

Rev: 1.03 11/2000 2/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Truth Table

GS71024T/U

CE1 CE2 OE WE V/S Mode DQ0 to DQ23

H X X X X Not selected High Z

X L X X X Not selected High Z

L H L H H Read using X/Y Data Out

L H L H L Read using A15 Data Out

L H X L H Write using X/Y Data In

L H X L L Write using A15 Data In

L H H H X Output disable High Z

X: “H” or “L”

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD –0.5 to +4.6 V

Input Voltage VIN

–0.5 to V

(≤ 4.6 V max.)

DD

+ 0.5

VDD Current

ISB1, ISB2

I

V

DD

Output Voltage VOUT

Allowable TQFP power dissipation PD 1 W

Allowable FPBGA power dissipation PD 1 W

Storage temperature

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

T

STG

–0.5 to V

(≤ 4.6 V max.)

–55 to 150

DD

+ 0.5

V

o

C

Rev: 1.03 11/2000 3/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Operating Conditions

Parameter Symbol Minimum Typical Maximum Unit

GS71024T/U

Supply Voltage for -10/12/15

Supply Voltage for -8

Input High Voltage

Input Low Voltage

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

V

DD

V

DD

V

IH

V

IL

T

Ac

T

Ai

3.0 3.3 3.6 V

3.135 3.3 3.6 V

2.0 —

–0.3 — 0.8 V

0 — 70

–40 — 85

Notes:

1. Input overshoot voltage should be less than V

+ 2 V and not exceed 20 ns.

DD

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter Symbol Test Condition Maximum Unit

C

C

OUT

IN

Input Capacitance

I/O Capacitance

V

V

IN

OUT

= 0 V

= 0 V

V

+ 0.3

DD

5 pF

7 pF

V

o

C

o

C

Notes:

1. Tested at TA = 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Minimum Maximum

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

I

IL

I

OL

V

OH

V

OL

Rev: 1.03 11/2000 4/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

V

= 0 to V

IN

Output High Z, V

to V

DD

I

= –4mA

OH

I

= +4mA

OL

DD

OUT

= 0

–1uA 1uA

–1uA 1uA

2.4 —

— 0.4 V

AC Test Conditions

Parameter Conditions

Input high level

Input low level

Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

V

V

= 2.4 V

IH

= 0.4 V

IL

DQ

Output Load 1

50Ω

VT = 1.4 V

GS71024T/U

1

30pF

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted

3. Output load 2 for tLZ, tHZ, t

OLZ

and t

OHZ

.

Power Supply Currents

Parameter Symbol Test Conditions

8 ns 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns

CE ≤ V

IL

Operating

Supply

Current

I

DD

All other inputs

≥ VIH or ≤ V

IL

Min. cycle time

I

= 0 mA

OUT

190 mA 160 mA 130 mA 110 mA 165 mA 135 mA 115 mA

Output Load 2

3.3 V

DQ

5pF

589Ω

1

434Ω

0 to 70°C -40 to 85°C

Standby

Current

I

SB1

CE ≥ V

All other inputs

≥ VIH or ≤V

IH

45 mA 40 mA 35 mA 30 mA 45 mA 40 mA 35 mA

IL

Min. cycle time

Standby

Current

I

SB2

CE ≥ V

All other inputs

≥ VDD – 0.2 V or ≤ 0.2 V

– 0.2 V

DD

10 mA 15 mA

Rev: 1.03 11/2000 5/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

AC Characteristics

Read Cycle

Parameter Symbol

GS71024T/U

-8 -10 -12 -15
Unit

Min Max Min Max Min Max Min Max

Read cycle time

Address access time

Chip enable access time (CE1, CE2)

MUX control to output valid (V/S)

Output enable to output valid (OE)

Output hold from address change

Output hold from MUX controls change

Chip enable to output in low Z (CE1, CE2)

Output enable to output in low Z (OE)

Chip disable to output in High Z (CE1, CE2)

Output disable to output in High Z (OE)

t

t

t

t

t

t

t

OH1

t

t

OLZ

t

t

OHZ

HZ

* These parameters are sampled and are not 100% tested

RC

AA

AC

AV

OE

OH

LZ

8 — 10 — 12 — 15 — ns

— 8 — 10 — 12 — 15 ns

— 8 — 10 — 12 — 15 ns

— 8 — 10 — 12 — 15 ns

— 4 — 5 — 6 — 7 ns

3 — 3 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

*

*

3 — 3 — 3 — 3 — ns

*

0 — 0 — 0 — 0 — ns

— 4 — 5 — 6 — 7 ns

*

— 4 — 5 — 6 — 7 ns

Rev: 1.03 11/2000 6/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71024T/U

Read Cycle 1: CE = OE = VIL, WE = V

Address

V/S

Data Out

Read Cycle 2: WE = V

IH

Address

(*1)

CE1

V/S

IH

t

RC

t

AA

t

OH

Previous Data Data valid

t

OH1

t

AV

t

RC

t

AA

t

AC

t

LZ

t

AV

t

HZ

OE

Data Out

t

OE

t

OLZ

High impedance

Data valid

*1 CE1 represents both CE1 low and CE2 high.

t

OHZ

Rev: 1.03 11/2000 7/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle

Parameter Symbol

GS71024T/U

-8 -10 -12 -15
Unit

Min Max Min Max Min Max Min Max

Write cycle time

Address valid to end of write

Chip enable to end of write (CE1, CE2)

MUX control to end of write (V/S)

Data set up time

Data hold time

Write pulse width

Address set up time

MUX control set up time

Write recovery time (WE)

Write recovery time (V/S, CE1, CE2 )

Output Low Z from end of write

Write to output in High Z

t

t

t

t

t

t

t

t

t

t

t

WR1

t

WLZ

t

WHZ

WC

AW

CW

VW

DW

DH

WP

AS

VS

WR

8 — 10 — 12 — 15 — ns

5.5 — 7 — 8 — 10 — ns

5.5 — 7 — 8 — 10 — ns

5.5 — 7 — 8 — 10 — ns

4 — 5 — 6 — 7 — ns

0 — 0 — 0 — 0 — ns

5.5 — 7 — 8 — 10 — ns

0 — 0 — 0 — 0 — ns

0 — 0 — 0 — 0 — ns

0 — 0 — 0 — 0 — ns

0 — 0 — 0 — 0 — ns

*

2 — 3 — 3 — 3 — ns

*

— 4 — 5 — 6 — 7 ns

* These parameters are sampled and are not 100% tested

Rev: 1.03 11/2000 8/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Write Cycle 1: WE control

Address

t

GS71024T/U

WC

Write Cycle 2: CE control

t

AW

t

WR

OE

t

t

CW

VW

t

WP

(*2)

CE1

V/S

(*1)

t

VS

t

AS

WE

Data In

t

WHZ

t

DW

Data valid

t

t

WLZ

DH

Data Out

(*3) (*3)

High impedance

*1 CE1 represents both CE1 low and CE2 high.
*2 Write is executed when both CE1 and WE are at low simultaneously.
*3 Do not apply the data input voltage to the output while DQ pin is in output condition.

t

WC

Address

t

AW

t

WR1

OE

CE1

(*1)

t

AS

t

t

CW

VW

V/S

t

WP

WE

Data In

t

DW

Data valid

t

DH

Data Out

High impedance

*1 CE1 represents both CE1 low and CE2 high.

Rev: 1.03 11/2000 9/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

6 mm x 8 mm Fine Pitch BGA

B

pin A1 index

GS71024T/U

8.00 ± 0.10

6.00 ± 0.10

units: mm

1.20(max)

Bottom View Top View

D

0.10

A

B

C

D

0.22 ± 0.05

E

F

G

H

0.36(typ)

pin A1 index

3.75

0.75(typ).

6 5 4 3 2 1

5.25
all Dia. 0.35Pitch 0.75

Rev: 1.03 11/2000 10/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Package Drawing

D

GS71024T/U

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15

A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch 0.65

L Foot Length 0.45 0.60 0.75

L1 Lead Length 1.00

Y Coplanarity 0.10

θ Lead Angle 0° 7°

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion

L1

A1

θ

L

c

Pin 1

e

D1

b

A2

Y

E1

E

BPR 1999.05.18

Rev: 1.03 11/2000 11/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information

Part Number Package Access Time Temp. Range Status

GS71024T-8 100-Pin TQFP 8 ns Commercial

GS71024T-10 100-Pin TQFP 10 ns Commercial

GS71024T-12 100-Pin TQFP 12 ns Commercial

GS71024T-15 100-Pin TQFP 15 ns Commercial

GS71024T-8I 100-Pin TQFP 8 ns Industrial Not Available

GS71024T-10I 100-Pin TQFP 10 ns Industrial

GS71024T-12I 100-Pin TQFP 12 ns Industrial

GS71024T-15I 100-Pin TQFP 15 ns Industrial

GS71024U-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial

GS71024U-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial

GS71024U-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial

GS71024T/U

GS71024U-15 6 mm x 8 mm Fine Pitch BGA 15 ns Commercial

GS71024U-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial Not Available

GS71024U-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial

GS71024U-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial

GS71024U-15I 6 mm x 8 mm Fine Pitch BGA 15 ns Industrial

* Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS71024T/U-12T.

Rev: 1.03 11/2000 12/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Revision History

GS71024T/U

Rev. Code: Old;

New

GS71024Rev 2:17pm, 4/8/

1999;

1.00a5/1999

GS710241.00a5/1999;

1.01 8/1999B

GS710241.01 8/1999C;

1.02 9/1999C

GS71024Rev1.01 8/

1999C;Rev1.02 2/2000D

Rev1.02 2/2000D;

71024_r1_03

Types of Changes

Format or Content

Format/Typos

Content

Content

Content

Format

Format and Content

Page/Revisions/Reason

• Document Changed subscripts to small caps.

• 1/Features: Changed TP to T.

• Document/Replaced “micro” with “fine pitch”.

• Ordering Information/Added Tape and Reel Note/
Enhancement

• Pin Description/Changed A0 - A14 to A0 - A15/Correction

• Page 1/Took out “Byte Control” from Features/Correction

• 3/Changed pin 97 from NC to CE2/Correction

•

1. Pin out/Changed Pin 89 from CK to NC/Correction

2. Pin out/Changed Pin 92 from NC to V/S/Correction

3. Pin out/Changed Pin 93 from V/S to X/Y/Correction

4. Pin out/Changed Pin 94 from X/Y to NC/Correction

• Package Diagram/Changed Dimension “D Max” from 20.1 to

22.1/Correction

• GSI Logo

• Updated format to comply with Technical Publications
standards

• Changed all V
page 2

• Updated Revision History (revision notes for 8/1999 incorrect)

to VSS and all V

SSQ

to VDD in pinout on

DDQ

Rev: 1.03 11/2000 13/13 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.