FEATURES
• fully integrated 270Mb/s SDI receiver or transmitter
• fully compliant with SMPTE 259M-C
• lock and carrier detect output indication
• performance from 0 - 85°C
™
PRO-LINX
GS7000
Serial Digital Video Transceiver
PRELIMINARY DATA SHEET
DESCRIPTION
The GS7000 is a dual function IC capable of operating as
either a 270Mb/s Serial Digital Video receiver or a 270Mb/s
Serial Digital Video transmitter. The GS7000 is designed so
that it can be programmed to operate in either receive or
transmit mode via a mode select pin.
GS7000
RECEIVER FUNCTION
• accepts SMPTE 259M-C 270Mb/s serial digital video
and outputs SMPTE 125M compliant 27Mb/s parallel
digital video and clock
• integrated cable equalization (beyond 100m Belden
8281)
• ease of design use and adjustment free operation
• H timing signal output
TRANSMITTER FUNCTION
• accepts SMPTE 125M (27Mb/s) parallel video data and
clock, outputs SMPTE 259M-C 270Mb/s serial digital
video
• integrated cable driver provides one differential output
(or two single-ended outputs)
APPLICATIONS
Space limited, low power 270Mb/s serial to parallel or
parallel to serial interfaces; Alternate, broadcast quality
uncompressed video interface for industrial and
professional video equipment using the IEEE P1394
interface.
When operating as a receiver, the serial data input accepts
SMPTE 259M-C compliant signals. Line terminations are on
the device. An on-chip by-passable fixed gain equalizer
provides cable equalization beyond 100m of high quality
co-axial cable. The clock recovery is performed on chip
with minimal external components. Incoming Serial Digital
Video data is decoded using a NRZI decoder and SMPTE
descrambler to provide clocked SMPTE 125M compliant
parallel output. The SMPTE descrambler and NRZI
decoding functions can be disabled.
When operating as a transmitter, the GS7000 accepts
parallel SMPTE 125M compliant ten bit video. An on-chip
scrambler and NRZI encoder converts the parallel data into
a bit serial SMPTE 259M-C compliant NRZI output signal
suitable for driving co-axial cable. Through the SMPTE
select pin, the SMPTE scrambler and NRZI coding functions
can be disabled.
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE
GS7000-CQT 52 pin MQFP 0°C to 85°C
GS7000-CTT 52 pin MQFP Tape 0°C to 85°C
D
PCLK
D
OUT(0,9)
IN (0,9)
OUT
H
SMPTE
SCRAMBLER
10
10
P to S
S to P
f/10 PLL
TRS
DETECTOR
DESCRAMBLER
SMPTE
NRZI
ENCODER
NRZI
DECODER
C1C
MUX
2
SLICER EQUALIZER
SIGNAL
LOCK
DETECT
SDO
SDO
LOCK
CD
PCLK
IN
SDI
SDI
EQRx/Tx
BLOCK DIAGRAM
Revision Date: August 1999 Document No. 522 - 06 - 02
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE
Supply Voltage 5.5V
Input Voltage Range (any input) V
DC Input Current (any one input) 10mA
Power Dissipation (V
= 5.25 V) 830mW
CC
Maximum Die Temperature 125°C
GS7000
Operating Temperature Range 0°C ≤ T
Storage Temperature Range -65°C ≤ T
Lead Temperature (soldering 10s) 260°C
AC ELECTRICAL CHARACTERISTICS (Receiver Mode)
VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified.
Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, f
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES
Parallel Data Output - Rise/Fall Time C
PCLK rising edge to D
PCLK rise/fall time C
Input Return Loss 75Ω match
center t
OUT(n)
5MHz -> 270MHz
< VIN < V
EE
PCLK
= 20pF t
L
= 20pF t
L
≤ 85°C
A
≤ 150°C
S
= 27MHz
CC
R/F_PDO
D
R/F_PCLKo
LOSS
IN
TEST
LEVEL
1.0 - 6.0 ns 1 1
--± 5ns2, 3 1
0.5 - 3.0 ns 1 1
-17 - dB 6
Asynchronous Lock Time t
Synchronous Lock Time t
LOCK_ASYNC
LOCK_SYNC
Input Jitter Tolerance pathological Input t
Output PCLK Jitter pathological Input t
J_SI
J_PCLKo
- - 250 ms 4 1
- - 10 µs 5 1
-0.4 - U.I. 6 4
- 1000 - ps p-p 6 1
Max Error Free Cable Length pathological Input 75 100 - m 6, 7 1, 4
NOTES
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value,
or to fall from 80% to 20% of the specified value.
2. Refer also to Figure 21.
3. This is the time difference between the rising edge of PCLK
and the center of the bit period.
OUT
4. This is the time delay between a valid serial TRS signal on the input, to the moment valid data
appears on the parallel outputs.
5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking
interval in accordance with SMPTE RP168-1993. The two streams may be 180° out of phase with
respect to one another, but pixel aligned.
6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3.
TEST LEVELS
1. 100% tested at 25 °C
2. Guaranteed by design
3. Inferred or correlated
value
4. Evaluated using test
setup Figure 1a.
5. Evaluated using test
setup Figure 1b.
6. Evaluated using test
setup Figure 1c.
7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable
and 75Ω connections. The MIN value is fully tested and the TYP value is based on using the
EB7000 Evaluation Board.
522 - 06 - 02
2
AC ELECTRICAL CHARACTERISTICS (Transmitter Mode)
VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified in ‘conditions’
Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, f
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES
Parallel Data Inputs - rise/fall time t
PCLK
= 27MHz
R/F_DPI
0.5
TEST
LEVEL
10
ns 1 2
Parallel Data Inputs - setup t
Parallel Data Inputs - hold t
Parallel Data Inputs - high V
Parallel Data Inputs - low V
Parallel Clock Input - rise/fall time t
Serial Data Output - signal swing V
= 5.25V V
CC
= 4.75V V
CC
= 4.75 - 5.25V V
CC
R/F_PCLK
Serial Data Output - high V
Serial Data Output - low V
Serial Data Output - rise/fall time t
Serial Data Output - jitter V
= 4.75V t
CC
Lock Time t
SETUP
HOLD
DPI
DPI
DSO
OH
OL
R/F
J_DSO
LOCK
4- -ns8 1
4- -ns8 1
2.0 - V
V
EE
-0.8V 1
CC
V1
0.5 - 4 ns 2
720 800 880 mV p-p 9, 10 1
-VCC - 0.8 - V 11 2
-VCC - 1.6 - V 11 2
400 600 1500 ps 1 1
--675ps p-p121
--250ms131
Output Return Loss 270MHz 15 - - dB 6
NOTES
8. Refer to Figure 26.
9. The outputs are capable of driving a 75Ω single-ended load, terminated to ground.
10.This value is measured after the resistor network at the SDI outputs shown in Figure 2.
11.Typical PECL values
12.6σ additive intrinsic jitter contribution based on pathological input signal
13.This is the lapsed time between valid parallel TRS input to valid serial output
TEST LEVELS
1. 100% tested at 25°C
2. Guaranteed by design
3. Inferred or correlated value
4. Evaluated using test setup Figure 1a.
5. Evaluated using test setup Figure 1b.
6. Evaluated using test setup Figure 1c.
GS7000
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0°C to 85°C, unless otherwise specified.
Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, f
PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS TEST LEVEL
Positive Supply Voltage V
Supply Current - Receive Mode V
Supply Current - Transmit Mode V
Power Consumption - Receive Mode V
Power Consumption - Transmit Mode V
Logic Inputs - Low V
Logic Inputs - High V
Logic Outputs - Low V
Logic Outputs - High V
CC
CC
CC
CC
CC
CC
CC
CC
= 27MHz
PCLK
= 5.25V I
= 5.25V I
= 5.25V P
= 5.25V P
= 5.25V V
= 4.75V V
= 5.25V V
= 4.75V V
CC
CC
CC
OL
OH
+ 4.75 + 5.00 + 5.25 V
- 150 - mA 1
- 130 - mA 1
D
D
IL
IH
- 750 - mW 3
- 650 - mW 3
V
EE
-0.8V 2
2.0 - V
V
EE
-0.5V 2
2.4 - V
3
CC
CC
V2
V2
522 - 06 - 02
BELDEN 8281
CABLE
EB7000
BOARD
TEKTRONIX
TDS 820
SCOPE
TEKTRONIX
GigaBERT
1400
DATA
DATA
GS9028
CABLE
DRIVER
TRANSMITTER
CLOCK
TRIGGER
Fig. 1a Test Setup for Jitter Measurements
GS7000
TEKTRONIX
VIDEO SlGNAL
GENERATOR
VIDEO STREAM
WITH EDH
Fig. 1b Test Setup for Error-Free Cable Length
BELDEN 8281
CABLE
EB7000
BOARD
EB9021
EDH ERROR
COUNTER
SERIAL DIGITAL
OUT
SERIAL DIGITAL
OUT
HP 4195A
NETWORK
ANALYSER
10u
10u
PARALLEL
DATA
INPUTS
825
BELDEN 8281
CABLE
EB7000
BOARD
Fig. 1c Test Setup for Return Loss Measurements
V
CC
825
7.5
7.5
10
11
12
13
220
1
NC
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
H
NC
CD
V
10k
V
CC
CC
MODE
100n
52 51 50 49 48 47 46 45 44 43 42 41 40
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
NC
NC
EE3
V
EE1
V
SDO
C1C2V
SDO
CD
CC3
V
GS7000
CC1
SDI
NC
SMPTE
CC2
SDI
V
NC
PCLKINV
14 15 16 17 18 19 20 21 22 23 24 25 26
V
CC
OUT
V
PCLK
EE2
EQ
DD
BELDEN 8281
CABLE
33
PARALLEL CLOCK OUT
100n
SS
NC
V
Rx/Tx
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
D
OUT8
D
OUT9
LOCK
NC
NC
NC
39
38
37
36
35
34
33
32
31
30
29
28
27
HP 4195A
NETWORK
ANALYSER
10p
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
PARALLEL
DATA
OUTPUTS
10k
V
CC
220
LOCK
V
CC
100n
V
CC
10u
522 - 06 - 02
PARALLEL CLOCK IN
SERIAL DIGITAL IN
100n
100n
100n
33
10p
10u10u
V
CC
Fig. 2 Test Circuit (Half Duplex Operation)
4
V
CC
Rx/Tx
EQ
PIN CONNECTIONS
OUT
EE3
SDO
C1C
CC3
SDO
V
GS7000
TOP VIEW
2
CC1
V
CD
SMPTENCNC
SDI
SDI
CC2
V
IN
PCLK
PCLK
VDDVSSNC
EQ
EE2
V
NC
Rx/Tx
NC
39
D
38
OUT0
D
37
OUT1
D
36
OUT2
D
35
OUT3
D
34
OUT4
D
33
OUT5
D
32
OUT6
D
31
OUT7
D
30
OUT8
D
29
OUT9
LOCK
28
NC
27
NC
V
51 50 49 48 47 46 45 44 43 42 41 40
NC
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
NC
52
1
2
3
4
5
6
7
8
9
10
11
H
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
EE1
V
PIN DESCRIPTIONS
NUMBER SYMBOL TYPE MODE DESCRIPTION
GS7000
1, 13, 14, 26, 27,
NC - - No Connect - Connected to Ground.
39, 40, 44, 45, 52
2-11 D
12 H
IN(0,9)
I Tx 27Mb/s Parallel Data Input
O Rx Indicates the presence of active video. Low after SAV ID and high after
EAV ID
15 V
16, 17 C
18 V
1
EE1
, C
CC1
19, 20 SDI, SDI
21 V
22 PCLK
23 V
CC2
IN
EE2
24 EQ
25 Rx/Tx
2
- - Most negative supply for analog circuits
- - External 100nF Loop Filter Capacitor Connection
- - Most positive supply for analog circuits
I Rx Differential Serial Data Input
- - Most positive supply for PECL circuits
I Tx 27MHz External Clock Input
- - Most negative supply for PECL circuits
I Rx Equalizer control. LOW = EQ on, HIGH = EQ bypassed.
I - Receiver/Transmitter Mode Control Input
28 LOCK O Rx/Tx Signal Lock Indication Output. Goes HIGH approximately 38 µs after
valid parallel data occurs.
29 - 38 D
OUT
(9,0)
O Rx 27Mb/s Parallel Data Output
5
522 - 06 - 02
PIN DESCRIPTIONS
NUMBER SYMBOL TYPE MODE DESCRIPTION
41 V
42 V
43 PCLK
46 SMPTE I Rx/Tx NRZI de/encoding and SMPTE de/scrambling control. LOW = NRZI and
GS7000
47 CD
48 V
49, 50 SDO, SDO
51 V
INPUT / OUTPUT CIRCUITS
ESD
IN
SS
DD
CC3
EE3
OUT
V
DD
- - Most negative supply for CMOS circuits
- - Most positive supply for CMOS circuits
O Rx 27MHz Clock Output
SMPTE mode on, HIGH = NRZI and SMPTE mode disabled.
O Rx/Tx Indicates loss of carrier. Low when carrier is present and high when
carrier is lost.
- - Most positive supply for Analog and PECL Circuits
O Tx Differential Serial Data Output
- - Most negative supply for Analog and PECL Circuits
V
DD
TO INTERNAL
STRUCTURES
TO INTERNAL
STRUCTURES
ESD
OUT
TTL-IN
ESD
Fig. 5 D
V
EE
Fig. 3 SDI,
, PCLKIN, EQ, Rx/Tx, SMPTE
IN(0,9)
SDI
V
V
DD
TO INTERNAL
STRUCTURES
SS
TO INTERNAL
STRUCTURES
Fig. 6 D
V
Fig. 4 SDO,
V
DD
V
EE
, H, LOCK, CD
OUT(0,9)
EE
SDO
ESD
OUT
522 - 06 - 02
6
V
DD
ESD
TYPICAL PERFORMANCE CURVES
DATA
TO
FOLLOW
TO INTERNAL
STRUCTURES
V
EE
Fig. 7 PCLK
(V
= 5 V, TA = 25 °C unless otherwise shown)
CC
OUT
OUT
GS7000
DATA
TO
FOLLOW
Fig. 8 Output PCLK Jitter vs. Cable Length
815
810
805
800
795
SERIAL DATA OUTPUT LEVEL (mV)
790
0 10 20 30 40 50 60 70 80 90
TEMPERATURE (˚C)
Fig. 10 Serial Data Output Level vs. Temperature
Fig. 9
0
-10
-20
-30
RETURN LOSS (dB)
-40
-50
270MHz
135MHz
0.05 GHz 1 GHz
FREQUENCY (GHz)
Fig. 11 Input Return Loss
7
522 - 06 - 02
0
-10
-20
-30
270MHz
135MHz
RETURN LOSS (dB)
GS7000
-40
-50
0.05 1
FREQUENCY (GHz)
Fig. 12 Output Return Loss
0
600kHz
-3
AMPLITUDE (dB)
-6
1k 10k 100k 1M 10M
FREQUENCY (Hz)
Fig. 13 Loop Bandwidth
J1
J2
J0.5
54MHz
1.97GHz
270MHz
540MHz
Impedances
normalized
to 50
W
Fig. 14 Serial Data Output
J1
J0.5
1.97GHz
54MHz
-J0.5
-J1
Fig. 16 Output Impedance
270MHz
540MHz
-J2
Impedances
normalized
to 50
W
-J0.5
-J2
-J1
Fig. 15 Input Impedance
J2
800
700
600
500
400
300
POWER (mW)
200
100
0
Rx
Tx
0 10 20 30 40 50 60 70 80 90
TEMPERATURE (˚C)
Fig. 17 Power vs. Temperature
522 - 06 - 02
8
RECEIVER OPERATION
EQ Rx/Tx SMPTE GS7000 OPERATING MODE
0 1 0 SMPTE 259M Receiver (Equalizer on, SMPTE / NRZI on)
1 1 0 SMPTE 259M Receiver with equalizer bypassed
0 1 1 Receiver function with NRZI and SMPTE Descrambler disabled, equalizer enabled.
1 1 1 Receiver function with NRZI and SMPTE Descrambler disabled, equalizer bypassed.
The diagram below depicts the active portions of the chip when operating in Receiver mode (Rx/Tx set to logic high level)
with the equalizer, descrambling and NRZI functions all active. In this mode of operation the output of the LOCK pin is logic
high whenever the receiver has successfully locked to the input serial bit stream. The output H
is set low after the SAV ID
and is set high after the EAV ID when these sequences are identified in the incoming bit stream.
GS7000
Note the function available called "Equalizer Control" (EQ
). Setting EQ to a logic HIGH level shuts off the equalization
function of the device for implementations where the length of cable to be equalized is very short (less than 10 m).
It is possible to turn off the NRZI and SMPTE Descrambler function by setting SMPTE
the output of H
D
PCLK
D
OUT(0,9)
, will be either "1" or "0" (indeterminate).
SCRAMBLER
IN (0,9)
10
OUT
H
10
P to S
S to P
DETECTOR
DESCRAMBLER
SMPTE
NRZI
ENCODER
f/10 PLL
TRS
NRZI
DECODER
SMPTE
C1C
MUX
2
SLICER EQUALIZER
HIGH. When operating in this mode,
SIGNAL
LOCK
DETECT
EQRx/Tx
SDO
SDO
LOCK
CD
PCLK
SDI
SDI
IN
Fig. 18 Functional Block Diagram (Receiver Mode)
TRANSMITTER OPERATION
EQ Rx/Tx SMPTE GS7000 OPERATING MODE
X 0 0 SMPTE 259M Transmitter
X 0 1 Transmitter function with NRZI and SMPTE Scrambler disabled
The diagram below depicts the active portions of the chip when operating in Transmitter mode (Rx/Tx set to logic low level),
with the NRZI and scrambling functions active.
Note that similar to receive mode above, it is possible to turn off the NRZI and SMPTE Scrambler by setting SMPTE
high.
9
522 - 06 - 02
SMPTE
C1C
2
SCRAMBLER
D
IN (0,9)
10
PCLK
D
OUT(0,9)
OUT
H
10
GS7000
P to S
S to P
f/10 PLL
TRS
DETECTOR
DESCRAMBLER
SMPTE
NRZI
ENCODER
NRZI
DECODER
MUX
SIGNAL
LOCK
DETECT
SLICER EQUALIZER
EQRx/Tx
Fig. 19 Functional Block Diagram (Transmitter Mode)
DIAGRAMS
The figure below describes the timing relationship between the outputs of the GS7000 when operating in receiver mode.
...
PCLK
SDO
SDO
LOCK
CD
PCLK
SDI
SDI
OUT
IN
XXX XXX 3FF 000 000 XXX
SAV ID
Fig. 20 Timing Diagram For Parallel Outputs, PCLK
XXX XXX XXX XXX XXX XXX 3FF 000 000 XXX
...
...
H
and
OUT
EAV ID
XXX XXX
D
OUT(n)
H
The figure below describes the relationship between the output parallel clock and the output parallel data. The output
parallel clock rising edge is centered on the output data within ±5 ns.
WORD CENTER
5 ns
5 ns
D
OUT(n)
PCLK
OUT
522 - 06 - 02
Fig. 21 Receiver Parallel Clock Alignment
10
The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel
data must be stable for 4ns prior to the rising edge of the PCLK
(setup time), and for 4 ns following the rising edge of the
IN
PCLKIN (hold time).
t
= 4ns
t
SETUP
= 4ns
HOLD
D
IN(n)
PCLK
IN
Fig. 22 Transmitter Setup and Hold Time
TYPICAL APPLICATION CIRCUITS
GS7000
V
100n 10u
V
CC
75
10n
75
10n
75
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
37.5
V
CC
CC1
10n
10n
GND
AGC
GND
V
CC
D
IN
D
IN
GND
V
CC
100p
TRISTATE
GS9024
75
1u
V
CC
SSI-CD
13 12 11 10 9 8 7 6 5 4 3 2 1
H
IN9DIN8DIN7DIN6DIN5DIN4DIN3DIN2DIN1
NC
EE1
1
2
CC1
CC2
EE2
10k
D
IN
OUT9DOUT8DOUT7DOUT6DOUT5DOUT4DOUT3DOUT2DOUT1DOUT0
NC
LOCK
D
D
D
CD-ADJ
V
CC
10n
AGC
CD
OUT
OUT
OEM
10n
10n
V
CC
7575
V
V
CC
100n
475
2k
V
CC
475
LOCK
100n
CC
V
220
100n
CC
14
NC
15
V
16
C
17
C
18
V
19
SDI
20
SDI
21
V
22
PCLK
23
V
24
EQ
25
Rx/Tx
26
NC
27 28 29 30 31 32 33 34 35 36 37 38 39
Typical Receiver Application Circuit with External Equalizer
GS7000
PARALLEL DATA OUTPUTS
IN0
D
SMPTE
PCLK
NC
V
SDO
SDO
V
OUT
V
V
NC
NC
EE3
CC3
CD
NC
NC
DD
SS
NC
V
CC
100n
220
CD
V
CC
52
51
50
49
48
47
46
45
10k
V
CC
MODE
44
43
42
41
33
PCLK OUT
40
CC
10p
V
100n
11
522 - 06 - 02
PARALLEL DATA IN
V
13 12 11 10 9 8 7 6 5 4 3 2 1
H
IN9DIN8DIN7DIN6DIN5DIN4DIN3DIN2DIN1DIN0
NC
EE1
1
2
CC1
CC2
EE2
D
GS7000
IN
OUT9DOUT8DOUT7DOUT6DOUT5DOUT4DOUT3DOUT2DOUT1DOUT0
NC
LOCK
D
14
NC
15
10k
V
16
C
17
C
18
V
19
SDI
20
SDI
21
V
22
PCLK
23
V
24
EQ
25
Rx/Tx
26
NC
100n
V
CC
100n
V
CC
GS7000
100n
10k
V
CC
10p
PARALLEL
CLOCK IN
33
V
CC
27 28 29 30 31 32 33 34 35 36 37 38 39
V
CC
10k
220
LOCK
100n
SMPTE
PCLK
V
CC
NC
V
V
NC
10u
NC
EE3
SDO
SDO
CC3
CD
NC
NC
OUT
V
DD
V
SS
NC
100n
52
51
50
49
48
47
10u
10u
V
CC
100n
46
45
44
43
42
41
40
V
CC
100n
V
CC
CC
10u
V
IN
IN
VEER
7575
V
CC
10k
MODE
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
CC
NC/GND
GS9028
100n
OUT
OUT
SET
75
CD
V
CC
59
220
OUT
75
75
1u
8.2n
8.2n
1u
75
OUT
V
CC
Typical Transmitter Application Circuit with Cable Driver
825
825
10µ
10µ
75
SDO
7.5
GS7000
SDO
All resistors in ohms, all capacitors in farads, unless otherwise shown.
7.5
Typical Transmitter Application Circuit - Single Ended Output Operation (as above with changes shown)
522 - 06 - 02
12
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
1
2
3
4
5
6
7
8
9
10
11
12
13
SERIAL DIGITAL
INPUT
10k
V
CC
MODE
V
CC
100n
52 51 50 49 48 47 46 45 44 43 42 41 40
NC
D
D
D
D
D
D
D
D
D
D
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
NC
V
EE3
SDO
SDO
CD
CC3
V
GS7000
NC
SMPTE
NC
H
NC
EE1
NC
V
14 15 16 17 18 19 20 21 22 23 24 25 26
C1C2V
CC1
SDI
SDI
CC2
V
PCLKINV
100n
100n
100n
V
CC
10u10u
V
CC
OUT
V
PCLK
EE2
EQ
DD
CD
33
100n
SS
V
D
D
D
D
D
D
D
D
D
D
Rx/Tx
V
V
CC
220
NC
NC
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
LOCK
NC
NC
CC
V
CC
V
CC
V
CC
100n
10u
10p
GS7000
39
38
37
36
35
34
32
33
31
30
29
28
27
10k
PARALLEL
CLOCK OUT
PARALLEL
DATA OUT
V
CC
220
LOCK
EQ
Typical Receiver Application Circuit - Unbalanced Input Operation
13
522 - 06 - 02
PACKAGE DIMENSIONS
17.20 BSC
14.00 BSC
14 ±2˚
17.20
BSC
14.00
BSC
14 ±2˚
0.13 MIN.
RADIUS
GS7000
1.60
REF
0.40 MIN
0˚ MIN
0.88
±0.15
0.13 MIN
RADIUS
7˚ MAX
0˚ MIN
52 pin MQFP
1.00 BSC
0.50 MAX
0.35 MIN
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change without notice.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
522 - 06 - 02
REVISION NOTES:
Removed figure 8.
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ
Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
© Copyright April 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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