Datasheet GMS90L320Q, GMS90L320PL, GMS90L320, GMS90C320Q50, GMS90C320Q40 Datasheet (HYNIX)

HYNIX SEMICONDUCTOR INC.

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS90C320

User’s Manual (Ver. 1.2)

REVISION HISTORY

VERSION 1.2 (Oct. 2000) This book

Correct the pin number of 44-MQFP package type on page 6.

VERSION 1.1 (Oct. 1999) Before version

Version 1.2
Published by

MCU Application Team
Copy right 2001 Hynix semiconductor, All right reserved.

Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre­sentatives listed at address directory.

Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

GMS90C320

Device Naming Structure

H(G)MS90X320

MCU Series

Hynix semiconductor MCU

XXXX

Frequency

Blank: 24MHz
40: 40MHz
50: 50MHz

Package Type

Blank:
PL:
Q:

Enhanced ROM-less version

Operating Voltage

C:L:Normal voltage

40PDIP
44PLCC
44MQFP

Low voltage

OCT. 2000 Ver 1.2

GMS90C320

GMS90C320 ordering information

Operating

Voltage (V)

4.25~5.5

2.7~5.5

Device Name

GMS90C320 40
GMS90C320 PL40
GMS90C320 Q40

GMS90C320 50
GMS90C320 PL50
GMS90C320 Q50

GMS90L320
GMS90L320 PL
GMS90L320 Q

ROM size

(bytes)

ROM-less 256 40

ROM-less 256 50

ROM-less 256 24

RAM size

(bytes)

Operating max.

Frequency (MHz)

Package Type

40PDIP
44PLCC
44MQFP

40PDIP
44PLCC
44MQFP

40PDIP
44PLCC
44MQFP

OCT. 2000 Ver 1.2

GMS90C320/L320

CMOS SINGLE-CHIP 8-BIT MICROCONT ROLLER

ROM-less Version for 90C52

GMS90C320

Operating Voltage (V) Device Name ROM RAM

4.25~5.5 GMS90C320 ROM-less 256 ×××× 8bit 40/50

2.7~5.5 GMS90L320 ROM-less 256 ×××× 8bit 24

Features

• Fully compatible to standard MCS-51 microcontroller

• Versions for 40/50 MHz operating frequency

• Low voltage version for 24MHz operating frequency

• 256 bytes of on-chip data RAM

• 64K external program memory space

• 64K external data memory space

• Four 8-bit ports

• Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)

•USART

• Six interrupt sources, two priority levels

• Power saving Idle and power down mode

Operating

Frequency (MHz)

• 2.7Volt low voltage version available

• P-DIP-40, P-LCC-44, P-MQFP-44 package

RAM

256 x 8

T0

T2

T1

The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard
80C32 applications.

CPU

ROM-less

8-BIT

USART

PORT0

PORT1

PORT2

PORT3

I/O

I/O

I/O

I/O

OCT. 2000 Ver 1.2 1

GMS90C320

44-PLCC Pin Configuration

(top view)

RESET

RxD/P3.0

TxD/P3.1

INT0

/P3.2

INT1

/P3.3
T0/P3.4
T1/P3.5

P1.5
P1.6
P1.7

N.C.

(P-LCC-44)

P1.4

P1.2

P1.1/T2EX

P1.0/T2

N.C.

2

1

VCCP0.0/AD0

4443424140

P1.3

6

543
7
8
9

10
11
12
13
14
15
16
17

1819202122232425262728

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

39

P0.5/AD5

38

P0.6/AD6

37

P0.7/AD7

36

EA

35

N.C.

34

ALE

33

PSEN

32

P2.7/A15

31

P2.6/A14

30

P2.5/A13

29

/P3.6RD/P3.7
WR

SS

N.C.

V

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

2 OCT. 2000 Ver 1.2

40-PDIP Pin Configuration

(top view)

GMS90C320

(P-DIP-40)

T2/P1.0

T2EX/P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RESET

RxD/P3.0

TxD/P3.1

INT0

/P3.2

INT1

/P3.3
T0/P3.4
T1/P3.5

/P3.6

WR

RD

/P3.7

XTAL2
XTAL1

V

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

SS

V

40

CC

P0.0/AD0

39

P0.1/AD1

38

P0.2/AD2

37

P0.3/AD3

36
35

P0.4/AD4

34

P0.5/AD5

33

P0.6/AD6

32

P0.7/AD7

31

EA

30

ALE

29

PSEN
P2.7/A15

28

P2.6/A14

27

P2.5/A13

26

P2.4/A12

25

P2.3/A11

24

P2.2/A10

23

P2.1/A9

22

P2.0/A8

21

OCT. 2000 Ver 1.2 3

GMS90C320

44-PLCC Pin Configuration

(top view)

(P-MQFP-44)

P1.4

P1.2

P1.1/T2EX

P1.0/T2

N.C.

VCCP0.0/AD0

P0.1/AD1

P0.2/AD2

P1.3

P0.3/AD3

P1.5
P1.6
P1.7

RESET

RxD/P3.0

N.C.

TxD/P3.1

INT0

/P3.2

INT1

/P3.3
T0/P3.4
T1/P3.5

4443424140

1
2
3
4
5
6
7
8

9
10
11

1213141516171819202122

/P3.6RD/P3.7

XTAL2

WR

XTAL1

3837363534

39

SS

N.C.

V

P2.0/A8

P2.1/A9

P2.2/A10

33
32
31
30
29
28
27
26
25
24
23

P2.3/A11

P2.4/A12

P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
N.C.
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

4 OCT. 2000 Ver 1.2

GMS90C320

V

V

CC

SS

Logic Symbol

XTAL1
XTAL2

RESET

EA

ALE

PSEN

Port 0
8-bit Digital I/O

Port 1
8-bit Digital I/O

Port 2
8-bit Digital I/O

Port 3
8-bit Digital I/O

OCT. 2000 Ver 1.2 5

GMS90C320

Pin Definitions and functions

Pin Number

Symbol

P-LCC-44 P-DIP-40

P1.0-P1.7 2-9 1-8 40-44,

2
3

P3.0-P3.7 11,13-1910-17 5,7-

11 10 5 P3.0/RxD receiver data input (asynchronous) or data input

13 11 7 P3.1 / TxD transmitter data output (asynchronous) or clock

14 12 8 P3.2 / INT0 interrupt 0 input /timer0gatecontrol
15 13 9 P3.3 / INT1 interrupt 1 input /timer1gatecontrol
16 14 10 P3.4 / T0 counter 0 input
17 15 11 P3.5 / T1 counter 1 input
18 16 12 P3.6 / WR the write control signal latches the data byte from

19 17 13 P3.7 / RD the read control signal enables the external data

XTAL2 20 18 14 O XTAL2

XTAL1 21 19 15 I XTAL1

P-MQFP-

44

1-3

1
2

40
41

13

Input/

Output

I/O Port1

is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(IIL, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.

P1.0/T2: Timer/counter 2 external count input
P1.1/T2EX: Timer/counter 2 trigger input

I/O Port 3

is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (IIL,in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.

Output of the inverting oscillator amplifier

Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no require­ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divide­by-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.

Function

output (synchronous) of the serial interface 0

output (synchronous) of the serial interface 0

port 0 into the external data memory

memory to port 0

6 OCT. 2000 Ver 1.2

GMS90C320

Symbol

Pin Number

P-LCC-44 P-DIP-40

P-MQFP-

44

Input/

Output

P2.0-P2.7 24-31 21-28 18-25 I/O Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal
pull-up resistors and can be used as inputs. As inputs, port 2 pins
that are externally pulled low will source current because of the
pulls-ups (IIL, in the DC characteristics). Port 2 emits the high­order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @Ri), port 2 emits
the contents of the P2 special function register.

PSEN 32 29 26 O The Program Store Enable

The read strobe to external program memory when the device is
executing code from the external program memory. PSEN is acti­vated twice each machine cycle, except that two PSEN activation
are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.

RESET 10 9 4 I RESET

A high level on this pin for two machine cycles while the oscillator
is running resets the device. An internal diffused resistor to V
permits power-on reset using only an external capacitor to VCC.

ALE 33 30 27 O The Address Latch Enable

Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted
at a constant rate of 1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.

EA 35 31 29 I External Access Enable

EA must be external held low to enable the device to fetch code
from external program memory locations 0000Hto FFFFH.IfEAis
held high, the device executes from internal program memory
unless the program counter contains an address greater than its
internal memory size.

P0.0-P0.7 43-36 39-32 37-30 I/O Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during program verification in
the GMS97C5x. External pull-up resistors are required during
program verification.

V

SS

V

CC

N.C. 1,12,

22 20 16 - Circuit ground potential
44 40 38 - Supply terminal for all operating modes

23,34

-

6,17,

28,39

- No connection

Function

SS

OCT. 2000 Ver 1.2 7

GMS90C320

Function Description

The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard

80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.
Figure 1 shows a block diagram of the GMS90C320

XTAL1
XTAL2

RESET

ALE

PSEN

EA

OSC & Timing

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

Serial Channel

RAM

256 x 8

Port 0

Port 1

Port 2

Port 3

Port 0
8-bit Digital I/O

Port 1
8-bit Digital I/O

Port 2
8-bit Digital I/O

Port 3
8-bit Digital I/O

Figure 1 Block Diagram of the GMS90C320

8 OCT. 2000 Ver 1.2

GMS90C320

CPU

The GMS90C320is efficientbothasa controller and as an arithmetic processor.IthasextensivefacilitiesforbinaryandBCD
arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con­sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% o f the instructions are
executed in 1.0µs.

Special Function R egister PSW

MSB LSB

BitNo.76543210

Addr. D0

CY AC F0 RS1 RS2 OV F1 P PSW

H

Bit Function
CY Carry Flag
AC Auxiliary Carry Flag (for BCD operation)
F0 General Purpose Flag
RS1

0
0
1
1

RS0

0
1
0
1

Register Bank select control bits

Bank 0 selected, data address 00H-07
Bank 1 selected, data address 08H-0F
Bank 2 selected, data address 10H-17
Bank 3 selected, data address 18H-1F

OV Overflow Flag
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware each instruction cycle to indicate an odd/
even number of “one” bits in the accumulator, i.e. even parity.

Reset value of PSW is 00

H.

H

H

H

H

OCT. 2000 Ver 1.2 9

GMS90C320

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register
area.

The 27 special function registers (SFR) include pointers and registers that provide an interface between theCPUand the other
on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in Table 1, Table 2,andTable 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the

functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.

Table 1
Special Function Registers in Numeric Order of their Addresses

Address Register

80

H

81

H

82

H

83

H

84

H

85

H

86

H

87

H

88

H

89

H

8A

H

8B

H

8C

H

8D

H

8E

H

8F

H

90

H

91

H

92

H

93

H

94

H

95

H

96

H

97

H

98

H

99

H

9A

H

9B

H

9C

H

9D

H

9E

H

9F

H

1)

: Bit-addressable Special Function Register

2)

: X means that the value is indeterminate and the location is reserved

1)

P0

SP

DPL

DPH
reserved
reserved
reserved

PCON

TCON

TMOD

TL0
TL1
TH0

TH1
reserved
reserved

1)

P1

reserved
reserved
reserved
reserved
reserved
reserved
reserved

SCON

SBUF
reserved
reserved
reserved
reserved
reserved
reserved

1)

1)

Contents after

Reset

FF

H

07

H

00

H

00

H

2)

XX

H

2)

XX

H

2)

XX

H

00

00
00
00
00
00

FF

00

00

2)

B

H

H
H
H
H
H

2)

H

2)

H

H

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

0XXX0000

XX
XX

XX
XX
XX
XX
XX
XX

XX
XX

XX
XX
XX
XX
XX

Address Register

A0

A1
A2
A3
A4
A5
A6
A7

A8

A9
AA
AB
AC
AD
AE
AF

B0

B1
B2
B3
B4
B5
B6
B7

B8

B9
BA
BB
BC
BD
BE
BF

H

H
H
H
H
H
H
H

H

H
H
H

H

H
H
H

H

H
H
H
H
H
H
H

H

H
H
H

H

H
H
H

1)

P2

reserved
reserved
reserved
reserved
reserved
reserved
reserved

1)

IE

reserved
reserved
reserved
reserved
reserved
reserved
reserved

1)

P3

reserved
reserved
reserved
reserved
reserved
reserved
reserved

1)

IP

reserved
reserved
reserved
reserved
reserved
reserved
reserved

Contents after

Reset

FF

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

FF

2)

B

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

B

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

0X000000

XX
XX

XX
XX
XX
XX
XX

XX
XX

XX
XX
XX
XX
XX

XX000000

XX
XX

XX
XX
XX
XX
XX

10 OCT. 2000 Ver 1.2

Table 1
Special Function Registers in numeric order of their addresses (cont’d)

GMS90C320

Address Register

C0

H

C1

H

C2

H

C3

H

C4

H

C5

H

C6

H

C7

H

C8

H

C9

H

CA

H

CB

H

CC

H

CD

H

CE

H

CF

H

D0

H

D1

H

D2

H

D3

H

D4

H

D5

H

D6

H

D7

H

D8

H

D9

H

DA

H

DB

H

DC

H

DD

H

DE

H

DF

H

1)

: Bit-addressable Special Function Register

2)

: X means that the value is indeterminate and the location is reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

T2CON

T2MOD

RC2L

RC2H

TL2

TH2
reserved
reserved

PSW

reserved
reserved
reserved
reserved
reserved
reserved
reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

1)

1)

Contents after

Reset

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

00

H

XXXXXXX0

00
00
00

00
XX
XX

00

XX
XX
XX
XX
XX
XX
XX

XX
XX
XX
XX
XX
XX
XX
XX

B
H
H
H
H

2)

H

2)

H

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

2)

H

Address Register

E0

H

E1

H

E2

H

E3

H

E4

H

E5

H

E6

H

E7

H

E8

2)

E9
EA
EB
EC
ED
EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB
FC
FD

FE

FF

H

H
H
H

H

H
H
H

H

H
H
H
H
H
H
H

H

H

H
H
H
H
H
H

1)

ACC

reserved
reserved
reserved
reserved
reserved
reserved
reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

1)

B

reserved
reserved
reserved
reserved
reserved
reserved
reserved

reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved

Contents after

Reset

00

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

00

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

2)

XX

H

OCT. 2000 Ver 1.2 11

GMS90C320

Table 2
Special Function Registers - Functional Blocks

Block Symbol Name Address

CPU ACC

B
DPH
DPL
PSW
SP

Interrupt System IE

IP

Ports P0

P1
P2
P3

Serial Channels PCON

SBUF
SCON

Timer 0 / Timer 1 TCON

TH0
TH1
TL0
TL1
TMOD

Timer 2 T2CON

T2MOD
RC2H
RC2L
TH2
TL2

Power Saving

PCON Power Control Register 87

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer

Interrupt Enable Register
Interrupt Priority Register

Port 0
Port 1
Port 2
Port 3

Power Control Register
Serial Channel Buffer Register
Serial Channel 0 Control Register

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte

E0
F0

83
82

D0

81

A8
B8

80
90
A0
B0

87
99

98
88

8C
8D
8A
8B
89

C8

C9
CB
CA
CD
CC

1)

H

1)

H

H
H

1)

H

H

1)

H

1)

H

1)

H

1)

H

1)

H

1)

H

H
H

1)

H

1)

H

H

H
H
H
H

1)

H

H

H
H
H
H

H

Modes

1)

Bit-addressable Special Function Registers

2)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks

3)

X means that the value is indeterminate and the locationis reserved

Content

after Reset

00

H

00

H

00

H

00

H

00

H

07

H

0X000000
XX000000

FF

H

FF

H

FF

H

FF

H

0XXX0000

3)

XX

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

XXXXXXX0

00

H

00

H

00

H

00

H

0XXX0000

2)

B

2)

B

2)

B

2)

B

2)

B

12 OCT. 2000 Ver 1.2

Table 3
Contents of SFRs, SFRs in Numeric Order

GMS90C320

Address Register

80
81
82
83
87
88

89
8A
8B
8C
8D

90

98

H

H

H

H

H

H

H

H

H

H

H

H

H

P0
SP

DPL

DPH
PCON SMOD - - - GF1 GF0 PDE IDLE
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD GATE C/T M1 M0 GATE C/T M1 M0

TL0
TL1
TH0
TH1

P1

SCON SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

99
A0
A8
B0
B8
C8
C9

H

H

H

H

H

H

H

SBUF

P2

IE EA - ET2 ES ET1 EX1 ET0 EX0

P3

IP - - PT2 PS PT1 PX1 PT0 PX0
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2MOD -------DCEN

SFR bit and byte addressable

SFR not bit addressable

-

This bit location is reserved.

OCT. 2000 Ver 1.2 13

GMS90C320

Table 3
Contents of SFRs, SFRs in Numeric Order (cont’d)

Address Register

CA
CB
CC
CD
D0
E0

F0

H

H

H

H

H

H

H

RC2L

RC2H

TL2
TH2

PSW CY AC F0 RS1 RS0 OV F1 P

ACC

B

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR bit and byte addressable

SFR not bit addressable

-

This bit location is reserved.

14 OCT. 2000 Ver 1.2

Timer/Counter0and1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

Table 4
Timer/Counter 0 and 1 Operating Modes

TMOD Input Clock

Mode Description

GATE C/T M1 M0 Internal

GMS90C320

External

(Max.)

0 8-bit timer/counter with a

divide-by-32 prescaler

1 16-bit timer/counter

2 8-bit timer/counter with 8-bit

autoreload

XX00

XX01

XX10

ƒ

OSC

------------------ -

12 32×

ƒ

OSC

--------------- -

12

ƒ

OSC

--------------- -

12

ƒ

OSC

------------------ -

24 32×

ƒ

OSC

--------------- -

24

ƒ

OSC

--------------- -

24

3 Timer/counter 0 used as one

8-bit timer/counter and one 8­bit timer

XX11

ƒ

OSC

--------------- -

12

ƒ

OSC

--------------- -

24

Timer 1 stops

In the “timer” function (C/T

= “0”) the register is incremented every machine cycle. Therefore the count rate is .

ƒ

OSC

12⁄

In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin
(P3.4/T0,P3.5/T1).Sinceittakestwo machinecyclestodetectafallingedge the max. count rate is . External inputs
INT0

and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.

ƒ

OSC

24⁄

Figure 2 illustrates the input clock logic.

P3.4/T0
P3.5/T1
max. f

OSC

/24

f

OSC

TR 0/1
TCON

÷12

C/T

TMOD

0

1

Control

ƒ

OSC

Timer 0/1
Input Clock

12⁄

GATE
TMOD

P3.2/INT0
P3.3/INT1

Figure 2 Timer/Counter 0 and 1 Input Clock Logic

OCT. 2000 Ver 1.2 15

GMS90C320

Timer 2

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which
is selected by bit C/T2

Table 5
Timer/Counter 2 Operating Modes

(T2CON.1). It has three operating modes as shown in Table 5.

Mode

16-bit Auto­reload

16-bit
Capture

RxCLK

or

TxCLK

0
0
0
0

0
0

T2CON

CP/

RL2

0
0
0
0

1
1

TR2

1
1
1
1

1
1

T2MO

D

DECN

0
0
1
1

X
X

T2CON

EXEN

0
1
X
X

0
1

P1.1

T2EX

X

↓

0
1

reload upon overflow
reload trigger (falling edge)
Down counting
Up counting

Remarks

X↓16-bit Timer/Counter (only

up-counting)
capture

Input Clock

Internal

ƒ

OSC

--------------- -

12

ƒ

OSC

--------------- -

12

External

(P1.0/T2)

max.

max.

TH1, TL2 → RC2H, RC2L

Baud Rate
Generator

1
1

X
X

1
1

X
X

0
1

X↓no overflow interrupt request

(TF2)
extra external interrupt

ƒ

OSC

--------------- -

12

max.

(“Timer 2”)

off X X 0 X X X Timer 2 stops - -

1Note: ↓ = fallingedge

ƒ

OSC

--------------- -

24

ƒ

OSC

--------------- -

24

ƒ

OSC

--------------- -

24

16 OCT. 2000 Ver 1.2

GMS90C320

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated
in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.

Table 6
USART Operating Modes

Mode

Baudrate Description

SM0 SM1

SCON

0 0 0 Serial data enters and exits through RxD.

ƒ

OSC

--------------- -

12

TxD outputs the shift clock.
8-bit are transmitted/received (LSB first)

1 0 1 Timer 1/2 overflow rate 8-bit UART

10 bits are transmitted ( through TxD) or
received (RxD)

2 10

ƒ

OSC

--------------- -

32

ƒ

OSC

--------------- -

or

64

9-bit UART
11 bits are transmitted ( through TxD) or
received (RxD)

3 1 1 Timer 1/2 overflow rate 9-bit UART

Like mode 2 except the variable baud rate

Table 7
Formulas for Calculating Baud rates

Baud Rate

derived from

Oscillator 0

Interface Mode Baud rate

ƒ

OSC

--------------- -

12

2

Timer 1 (16-bit timer)

1, 3
(8-bit timer with 8-bit autore­load)

1, 3

Timer 2 1, 3

SMOD

2

------------------------------------- -----

SMOD

2

----------------------------------- --------------------------------------------- -

SMOD

2

----------------------------------- ----------------------- ­32 12 256 TH1–

-------------------------------------- ----------------------------------------

32 65536

64

timer 1 overflow rate×

32

()××

ƒ

OSC

()–[]×

ƒ

×

OSC

ƒ

×

OSC

RC2H,RC2L

OCT. 2000 Ver 1.2 17

GMS90C320

Interrupt System

The GMS90C320 provides 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt
sources and illustrates the request and control flags.

High Priority

Timer 0 Overflow

TF0

TCON.5

ET0
IE.1

PT0
IP.1

Low Priority

P1.1/
T2EX

Timer 2 Overflow

P3.2/
INT0

P3.3/
INT1

EXEN2

T2CON.3

USART

IT0

TCON.0

IT1

TCON.2

Timer 1 Overflow

TF2

T2CON.7

EXF2

T2CON.6

RI

SCON.0

SCON.1

TF1

TCON.7

TI

IE0

TCON.1

IE1

TCON.3

ET1
IE.3

ET2
IE.5

ES

IE.4

EX0
IE.0

EX1
IE.2

EA

IE.7

PT1
IP.3

PT2
IP.5

PS

IP.4

PX0
IP.0

PX1
IP.2

Figure 3
Interrupt Request Sources

18 OCT. 2000 Ver 1.2

Table 8
Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags) Vector Vector Address

GMS90C320

IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt

0003
000B
0013
001B
0023
002B

H
H
H
H
H
H

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high­priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of
the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within
each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.

Table 9
Interrupt Priority-Within-Level

Interrupt Source Priority

IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt

High

↓

Low

OCT. 2000 Ver 1.2 19

GMS90C320

Power Saving Modes

T wopower down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively.IfthePower Down

mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview
of the power saving modes.

Table 10
Power Saving Modes Overview

Mode Entering Instruction

Idle mode ORL PCON,#01H - enabled interrupt

Power-Down
Mode

Example

ORL PCON,#02H Hardware Reset Oscillator is stopped, contents of

In the Power Down mode of operation, V
that V

is not reduced before the Power Down mode is invoked, and that VCCis restored to its normal operating level, before

CC

Leaving by Remarks

CPU is gated off

- Hardware Reset

can be reduced to minimize power consumption. It must be ensured, however,

CC

CPU status registers maintain
their data.
Peripherals are active

on-chip RAM and SFR’s are main­tained (leaving Power Down Mode
means redefinition of SFR con­tents).

the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The
reset should not be activated before V

is restored to its normal operating level and must be held active long enough to allow

CC

the oscillator to restart and stabilize (similar to power-on reset).

20 OCT. 2000 Ver 1.2

GMS90C320

Absolute Maximum Ratings

Ambient temperature under bias (TA) .......................................................................................................-40 to + 85°C

Storage temperature (T
Voltage on V

pins with respect to ground (VSS).....................................................................................-0.5 V to 6.5 V

CC

Voltage on any pin with respect to ground (V

)..........................................................................................................................-65 to+150°C

ST

).......................................................................................-0.5 to VCC+0.5V

SS

Input current on any pin during overload condition..................................................................................-10mAto+10mA

Absolute sum of all input currents during overload condition..................................................................| 100 mA |

Power dissipation.......................................................................................................................................TBD

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper­ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may
affect device reliability. During overload conditions (VIN> VCCor V
must not exceed the values defined by the absolute maximum ratings.

<

VSS) the Voltageon VCCpins with respect to ground (VSS)

IN

OCT. 2000 Ver 1.2 21

GMS90C320

DC Characteristics

DC Characteristics for GMS90C320

VCC=5V+10%,-15%;VSS=0V; TA=0°Cto70°C

Parameter Symbol

Input low voltage
(except EA, RESET)

Input low voltage (EA)V
Input low voltage (RESET) V
Input high voltage (except

XTAL1, EA, RESET)
Input high voltage to XTAL1 V
Input high voltage to EA,

RESET

V

IL

IL1
IL2

V

IH

IH1

V

IH2

0.2VCC+0.9 VCC+0.5

Output low voltage
(ports 1, 2, 3)

V

OL

Output low voltage
(port0,ALE,PSEN)

Output high voltage
(ports 1, 2, 3)

V

OL1

V

OH

Output high voltage
(port 0 in external bus mode,

V

OH1

ALE, PSEN)
Logic 0 input current

(ports 1, 2, 3)
Logical 1-to-0 transition cur-

rent (ports 1, 2, 3)
Input leakage current

(port 0, EA)
Pin capacitance C

I

IL

I

TL

I

LI

IO

Power supply current:

Active mode, 12MHz
Idle mode, 12MHz

3)

Active mode, 24 MHz
Idle mode, 24MHz

3)

Active mode, 40 MHz
Idle mode, 40 MHz

3)

Active mode, 50 MHz
Idle mode, 50 MHz
Power Down Mode

3)

3)

3)

3)

3)

3)

I
I
I
I
I
I
I
I
I

CC
CC
CC
CC
CC
CC
CC
CC
PD

Limit Values

Unit Test Conditions

Min. Max.

-0.5

-0.5

-0.5

0.2VCC-0.1

0.2VCC-0.3

0.2VCC+0.1

V­V-

V­V-

0.7V

CC

0.6V

CC

-

-

2.4

0.9V

CC

2.4

0.9V

CC

-10 -50 µA

-65 -650 µA

- ±1 µA

-10pF

-

-

-

-

-

-

-

-

-

VCC+0.5
VCC+0.5

V­V-

0.3

0.45

V

1.0

0.3

0.45

V

1.0

-V

-V

16

7.5
26

13.5
44
18
55

22.5
50

mA
mA
mA
mA
mA
mA
mA
mA

µA

IOL=100µA
IOL=1.6mA
IOL=3.5mA

IOL=200µA
IOL=3.2mA
IOL=7.0mA

IOH=-80µA
IOH=-10µA

IOH=-800µA
IOH=-80µA

VIN=0.45V

VIN=2.0V

0.45 < VIN< V
fC=1MHz, TA=25°C

VCC=5V
VCC=5V
VCC=5V
VCC=5V
VCC=5V
VCC=5V
VCC=5V
VCC=5V
VCC=5.5V

1)

1)

2)

2)

CC

4)

5)

4)

5)

4)

5)

4)

5)

6)

22 OCT. 2000 Ver 1.2

1)

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLof ALE and port 3. The
noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions
during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt­trigger strobe input.

2)

Capacitive loading on ports 0 and 2 may cause the VOHon ALE a nd PSEN to momentarily fall below the 0.9VCCspecification
when the address lines are stabilizing.

3)

I

at other frequencies is given by:

CC m ax

active mode: I
idle mode: I
where ƒ

OSC

4)

ICC(active mode) is measured with:
XTAL1 driven with t
EA

=Port0=RESET=VCC; all other pins are disconnected. ICCwould be slightly higher if a crys t al oscillator is used (appr.

=1.0׃

CC

=0.37׃

CC

OSC

OSC

+3.16

+3.63

is the oscillator frequency in MHz. ICCvalues are given in mA and measured at VCC=5V.

CLCH,tCHCL

=5ns,VIL=VSS+0.5V,VIH=VCC- 0.5V; XTAL2 = N.C.;

1mA).

5)

ICC(Idle mode) is me asured with all output pins disconnected a nd with all peripherals disabled;
XTAL1 driven with t
RESET=EA

6)

IPD(Power Down Mode) is measured under following conditions:

=Port0=VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.

EA

CLCH,tCHCL

=VSS;Port0=VCC; all other pins are disconnected;

=5ns,VIL=VSS+0.5V,VIH=VCC- 0.5V; XTAL2 = N.C.;

GMS90C320

OCT. 2000 Ver 1.2 23

GMS90C320

DC Characteristics for GMS90L320

VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA=0°Cto70°C

Parameter Symbol

Input low voltage V
Input high voltage V
Output low voltage

(ports 1, 2, 3)
Output low voltage

(port0,ALE,PSEN)

V

Output high voltage
(ports 1, 2, 3)

Output high voltage
(port 0 in external bus mode, ALE,

V

PSEN)
Logic 0 input current

(ports 1, 2, 3)
Logical 1-to-0 transition current

(ports 1, 2, 3)
Input leakage current

(port 0, EA)
Pin capacitance

Power supply current:

Active mode, 16 MHz
Idle mode, 16MHz
Active mode, 24MHz
Idle mode, 24MHz
Power Down Mode

3)

3)

3)

3)

3)

V

V

C

I
I
I
I
I

OL1

OH1

I

I

TL

I

CC
CC
CC
CC
PD

IL

IH

OL

OH

IL

LI

IO

Limit Values

Unit Test Conditions

Min. Max.

-0.5 0.8 V -

2.0

-

-

2.0

0.9V

CC

2.0

0.9V

CC

-1 -50 µA

-25 -250 µA

- ±1 µA

-10pF

-

-

-

-

-

VCC+0.5

0.45

0.30

0.45

0.30

V-

V

V

-V

-V

10

5.25

mA
mA

16

8.25
10

µA

IOL=1.6mA
IOL=100µA

IOL=3.2mA
IOL=200µA

IOH=-20µA
IOH=-10µA

IOH=-800µA
IOH=-80µA

VIN=0.45V

VIN=2.0V

0.45 < VIN< V
fC=1MHz

TA=25°C

VCC=3.3V
VCC=3.3V
VCC=3.3V
VCC=3.3V
VCC=3.6V

1)

1)

1)

1)

2)

2)

CC

4)

5)

4)

5)

6)

24 OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on
their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters
and what they stand for.

A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal

T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float

For example,
t

= Time from Address Valid to ALE Low

AVLL

t

= Time from ALE Low to PSEN Low

LLPL

OCT. 2000 Ver 1.2 25

GMS90C320

AC Characteristics for 12MHz version

VCC=5V: VCC=5V+ 10%, −15%; VSS=0V;TA=0°Cto70°C

(CLfor port 0. ALE and PSEN outputs = 100pF; CLfor all other outputs = 80pF)

VCC=3.3V: VCC=3.3V+ 0.3V, −0.6V; VSS=0V;TA=0°Cto70°C

(CLforport0.ALEandPSENoutputs = 50pF; CLfor all other outputs = 50pF)

Variable clock: Vcc = 5V: 1/t

Vcc = 3.3V: 1/t

=3.5MHzto12MHz

CLCL

=1MHzto12MHz

CLCL

External Program Memory Characteristics

Parameter Symbol

12 MHz Oscillator

Min. Max. Min. Max.

Variable Oscillator

1/t

= 3.5 to 12MHz

CLCL

Unit

ALE pulse width
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN

1)

Interfacing the GMS90C320 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

1)

1)

127 - 2t

43 - t
43 - t

-233 -4t

58 - t

215 - 3t

-150 -3t

-40 -

CLCL

-40 - ns

CLCL

-40 -

CLCL

-100 ns

CLCL

-25 -

CLCL

-35 - ns

CLCL

-100

CLCL

0- 0 - ns

-63 - t

75 - t

-8 - ns

CLCL

-302 -5t

CLCL

CLCL

-20

-115

-10 - -10 - ns

ns

ns

ns

ns

ns

ns

26 OCT. 2000 Ver 1.2

AC Characteristics for 12MHz version

External Data Memory Characteristics

Parameter Symbol

12 MHz Oscillator

Variable Oscillator

1/t

=3.5to12MHz

CLCL

Min. Max. Min. Max.

GMS90C320

Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD

WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

Advance Information (12MHz)

External Clock Drive

Parameter Symbol

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

400 - 6t
400 - 6t
127 - 2t

-252 -5t

0- 0 -

-97 -2t

-517 -8t

-585 -9t
200 300 3t
203 - 4t

43 123 t
33 - t

433 - 7t

33 - t

-100 -

CLCL

-100 - ns

CLCL

-40 -

CLCL

-165 ns

CLCL

-70 ns

CLCL

-150

CLCL

-165 ns

CLCL

-50 3t

CLCL

-130 - ns

CLCL

-40 t

CLCL

-50 - ns

CLCL

-150 - ns

CLCL

-50 -

CLCL

CLCL

CLCL

+50

+40

ns

ns

ns

ns

ns

ns

ns

-0 - 0ns

Variable Oscillator

(Freq. = 3.5 to 12MHz)

Unit

Min. Max.

Oscillator period (VCC=5V)
Oscillator period (VCC=3.3V)

High time
Low time
Rise time
Fall time

t

CLCL

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

83.3

83.3
20 t
20 t

285.7
1

CLCL-tCLCX

CLCL-tCHCX

ns
ns

ns

-20ns

-20

ns

OCT. 2000 Ver 1.2 27

GMS90C320

AC Characteristics for 16MHz version

VCC=5V: VCC=5V+ 10%, −15%; VSS=0V;TA=0°Cto70°C

(CLfor port 0. ALE and PSEN outputs = 100pF; CLfor all other outputs = 80pF)

VCC=3.3V: VCC=3.3V+ 0.3V, −0.6V; VSS=0V;TA=0°Cto70°C

(CLforport0.ALEandPSENoutputs = 50pF; CLfor all other outputs = 50pF)

Variable clock: Vcc = 5V: 1/t

Vcc = 3.3V: 1/t

=3.5MHzto16MHz

CLCL

=1MHzto16MHz

CLCL

External Program Memory Characteristics

Parameter Symbol

16 MHz Oscillator

Min. Max. Min. Max.

ALE pulse width
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN

1)

InterfacingtheGMS90C320 to devices with float times up to 35 ns is permissible. This limitedbus contentionwill not cause

any damage to port 0 Drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

1)

1)

85 - 2t
23 - t
43 - t

-150 -4t

38 - t

153 - 3t

-88 -3t

0- 0 -ns

-43 - t

55 - t

-198 -5t

-10 - -10 - ns

Variable Oscillator

1/t

=3.5to16MHz

CLCL

-40 -

CLCL

-40 - ns

CLCL

-40 -

CLCL

CLCL

-25 -

CLCL

-35 - ns

CLCL

CLCL

CLCL

-8 - ns

CLCL

CLCL

Unit

ns

ns

-100 ns
ns

-100

-20

-115

ns

ns

ns

28 OCT. 2000 Ver 1.2

AC Characteristics for 16MHz

External Data Memory Characteristics

Parameter Symbol

16 MHz Oscillator

Variable Oscillator

1/t

=3.5to16MHz

CLCL

Min. Max. Min. Max.

GMS90C320

Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD

WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

Advance Information (16MHz)

External Clock Drive

Parameter Symbol

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

275 - 6t
275 - 6t
127 - 2t

-183 -5t

0- 0 -

-75 -2t

-350 -8t

-398 -9t
138 238 3t
120 - 4t

28 97 t
13 - t

288 - 7t

23 - t

-100 -

CLCL

-100 - ns

CLCL

-40 -

CLCL

-130 ns

CLCL

-50 ns

CLCL

-150

CLCL

-165 ns

CLCL

−50 3t

CLCL

-130 - ns

CLCL

−35 t

CLCL

−50 - ns

CLCL

-150 - ns

CLCL

−40 -

CLCL

CLCL

CLCL

+50

+35

ns

ns

ns

ns

ns

ns

ns

-0 - 0ns

Variable Oscillator

(Freq. = 3.5 to 16MHz)

Unit

Min. Max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

62.5 285.7
17 t
17 t

CLCL-tCLCX

CLCL-tCHCX

ns
ns
ns

-17ns

-17

ns

OCT. 2000 Ver 1.2 29

GMS90C320

AC Characteristics for 24MHz version

VCC=5V: VCC=5V+ 10%, −15%; VSS=0V;TA=0°Cto70°C

(CLfor port 0. ALE and PSEN outputs = 100pF; CLfor all other outputs = 80pF)

VCC=3.3V: VCC=3.3V+ 0.3V, −0.6V; VSS=0V;TA=0°Cto70°C

(CLforport0.ALEandPSENoutputs = 50pF; CLfor all other outputs = 50pF)

Variable clock: Vcc = 5V: 1/t

Vcc = 3.3V: 1/t

=3.5MHzto24MHz

CLCL

=1MHzto24MHz

CLCL

External Program Memory Characteristics

Parameter Symbol

24 MHz Oscillator

Min. Max. Min. Max.

ALE pulse width
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN

1)

Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

1)

1)

43 - 2t
17 - t
17 - t

-80 -4t
22 - t
95 - 3t

-60 -3t

0- 0 -ns

-32 - t
37 - t

-148 - 5t

-10 - -10 - ns

Variable Oscillator

1/t

=3.5to24MHz

CLCL

-40 -

CLCL

-25 - ns

CLCL

-25 -

CLCL

CLCL

-20 -

CLCL

-30 - ns

CLCL

CLCL

CLCL

-5 - ns

CLCL

CLCL

-87 ns

-65

-10

-60

Unit

ns

ns

ns

ns

ns

ns

30 OCT. 2000 Ver 1.2

AC Characteristics for 24MHz

External Data Memory Characteristics

Parameter Symbol

24 MHz Oscillator

Variable Oscillator

1/t

=3.5to24MHz

CLCL

Min. Max. Min. Max.

GMS90C320

Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD

WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

Advance Information (24MHz)

External Clock Drive

Table 11.

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

180 - 6t
180 - 6t

56 - 2t

-118 - 5t

0- 0 -

-63 -2t

-200 -8t

-220 -9t
75 175 3t
67 - 4t
17 67 t

5-t

170 - 7t

15 - t

-70 -

CLCL

-70 - ns

CLCL

-27 -

CLCL

-90 ns

CLCL

-20 ns

CLCL

-133

CLCL

-155 ns

CLCL

-50 3t

CLCL

-97 - ns

CLCL

-25 t

CLCL

-37 - ns

CLCL

-122 - ns

CLCL

-27 -

CLCL

CLCL

CLCL

+50

+25

ns

ns

ns

ns

ns

ns

ns

-0 - 0ns

Variable Oscillator

Parameter Symbol

(Freq. = 3.5 to 24MHz)

Unit

Min. Max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

41.7 285.7
12 t
12 t

CLCL-tCLCX

CLCL-tCHCX

ns
ns
ns

-12ns

-12

ns

OCT. 2000 Ver 1.2 31

GMS90C320

AC Characteristics for 40MHz version

VCC=5V+10%,− 15%; VSS=0V;TA=0°Cto70°C

(CLfor port 0. ALE and PSEN outputs = 100pF; CLfor all other outputs = 80pF)

External Program Memory Characteristics

40 MHz Oscillator

Parameter Symbol

Min. Max. Min. Max.

Variable Oscillator

1/t

=3.5to40MHz

CLCL

Unit

ALE pulse width
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN

1)

Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

1)

1)

35 - 2t
10 - t
10 - t

-55 -4t
10 - t
60 - 3t

-25 -3t

−15 -

CLCL

−15 - ns

CLCL

−15 -

CLCL

−45 ns

CLCL

−15 -

CLCL

−15 - ns

CLCL

−50

CLCL

0- 0 -ns

-15 -t
20 - t

−5-ns

CLCL

-65 -5t

CLCL

CLCL

−10

−60

-5 - -5 - ns

ns

ns

ns

ns

ns

ns

32 OCT. 2000 Ver 1.2

AC Characteristics for 40MHz

External Data Memory Characteristics

Parameter Symbol

at 40 MHz Clock

Variable Clock

1/t

=3.5to40MHz

CLCL

Min. Max. Min. Max.

GMS90C320

Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD

WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

Advance Information (40MHz)

External Clock Drive

Parameter Symbol

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

120 - 6t
120 - 6t

10 - t

-75 -5t

0- 0 -

-38 -2t

-150 - 8t

-150 - 9t
60 90 3t
70 - 4t
10 40 t

5-t

125 - 7t

5-t

-30 -

CLCL

-30 - ns

CLCL

-15 -

CLCL

-50 ns

CLCL

-12 ns

CLCL

-50

CLCL

-75 ns

CLCL

-15 3t

CLCL

-30 - ns

CLCL

-15 t

CLCL

-20 - ns

CLCL

-50 - ns

CLCL

-20 -

CLCL

CLCL

CLCL

+15

+15

ns

ns

ns

ns

ns

ns

ns

-0 - 0ns

Variable Oscillator

(Freq. = 3.5 to 40MHz)

Unit

Min. Max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

25 285.7
10 t
10 t

CLCL-tCLCX

CLCL-tCHCX

ns
ns
ns

-10ns

-10

ns

OCT. 2000 Ver 1.2 33

GMS90C320

AC Characteristics for 50MHz version

VCC=5V+10%,− 15%; VSS=0V;TA=0°Cto70°C

(CLfor port 0. ALE and PSEN outputs = 100pF; CLfor all other outputs = 80pF)

Variable Clock : VCC=5V,1/t

=3.5MHzto50MHz

CLCL

External Program Memory Characteristics

Parameter Symbol

50 MHz Oscillator

Min. Max. Min. Max.

ALE pulse width
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN

1)

Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

1)

1)

25 - 2t

5-t
5-t

-40 -4t

5-t

45 - 3t

-20 -3t

0- 0 -ns

-10 -t
15 - t

-45 -5t

-5 - -5 - ns

Variable Oscillator

1/t

=3.5to50MHz

CLCL

−15 -

CLCL

−15 - ns

CLCL

−15 -

CLCL

−40 ns

CLCL

−15 -

CLCL

−15 - ns

CLCL

−40

CLCL

−10

CLCL

−5-ns

CLCL

−55

CLCL

Unit

ns

ns

ns

ns

ns

ns

34 OCT. 2000 Ver 1.2

AC Characteristics for 50MHz

External Data Memory Characteristics

Parameter Symbol

at 50 MHz Clock

Variable Clock

1/t

=3.5to50MHz

CLCL

Min. Max. Min. Max.

GMS90C320

Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD

WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

Advance Information (50MHz)

External Clock Drive

Parameter Symbol

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

90 - 6t
90 - 6t
25 - 2t

-60 -5t

0- 0 -

-28 -2t

- 120 - 8t

- 125 - 9t
45 75 3t
50 - 4t

535t
5-t

100 - 7t

5-t

-30 -

CLCL

-30 - ns

CLCL

-15 -

CLCL

-40 ns

CLCL

-12 ns

CLCL

-40

CLCL

-55 ns

CLCL

-15 3t

CLCL

-30 - ns

CLCL

-15 t

CLCL

-15 - ns

CLCL

-40 - ns

CLCL

-15 -

CLCL

CLCL

CLCL

+15

+15

ns

ns

ns

ns

ns

ns

ns

-0 - 0ns

Variable Oscillator

(Freq. = 3.5 to 50MHz)

Unit

Min. Max.

Oscillator period
High time
Low time
Rise time
Fall time

t

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

20 285.7
10 t
10 t

CLCL-tCLCX

CLCL-tCHCX

ns
ns
ns

-10ns

-10

ns

OCT. 2000 Ver 1.2 35

GMS90C320

ALE

PSEN

PORT 0

t

LHLL

t

AVLL

t

LLAX

A0-A7

t

AZPL

t

AVIV

t

LLPL

t

PLPH

t

LLIV

t

PLIV

t

PXAV

t

PXIZ

t

PXIX

INSTR.

IN

A0-A7

PORT 2

Figure 4 External Program Memory Read Cycle

A8-A15

A8-A15

36 OCT. 2000 Ver 1.2

GMS90C320

ALE

t

LHLL

PSEN

RD

t

AVLL

PORT 0

A0-A7 from

RI or DPL

PORT 2

Figure 5 External Data Memory Read Cycle

ALE

t

LHLL

t

LLDV

t

LLWL

t

LLAX2

t

AVWL

t

AVDV

P2.0-P2.7 or A8-A15from DPH

t

t

RLDV

RLAZ

t

RLRH

t

WHLH

t

RHDZ

t

RHDX

DATA IN A0-A7 from PCL INSTR. IN

A8-A15 from PCH

t

WHLH

PSEN

WR

t

AVLL

PORT 0

t

LLAX

A0-A7 from

RI or DPL

t

AVWL

PORT 2

Figure 6 External Data Memory Write Cycle

t

LLWL

t

QVWX

P2.0-P2.7 or A8-A15 from DPH

t

WLWH

t

QVWH

DATA OUT

t

WHQX

A0-A7 from PCL

A8-A15 from PCH

INSTR. IN

OCT. 2000 Ver 1.2 37

GMS90C320

−0.5V

V

CC

0.45V

AC Inputs during testing are driven at VCC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made a V

Figure 7 AC Testing: Input, Output Waveforms

IH min

0.2VCC+ 0.9
Test Points

− 0.1

0.2V

CC

for a logic ‘1’ and V

for a logic ‘0’.

ILma x

V

− 0.1

OH

+ 0.1

V

OL

V

LOAD

V

V

LOAD

LOAD

+ 0.1

− 0.1

Timing Reference Points

0.2VCC− 0.1

For timing purposes a port pin is no longer floating when a 100mV change from load voltage
occurs and begins to float when a 100mV change from the loaded VOH/VOLlevel occurs.

IOL/IOH≥ 20mA.

Figure 8 Float Waveforms

t

t

CLCH

CLCL

t

CHCX

VCC−0.5V

0.45V

0.7 V

CC

0.2 VCC−0.1

t

CHCL

t

CLCX

Figure 9 External Clock Cycle

38 OCT. 2000 Ver 1.2

OSCILLATOR CIRCUIT

CRYSTAL OSCILLATOR MODE DRIVING FROM EXTERNAL SOURCE

GMS90C320

C2

C1

XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14

XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15

N.C.

External Oscillator
Signal

XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14

XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15

C1, C2 = 30pF ±10pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.

Figure 10 Recommended Oscillator Circuits

Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic
resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.

OCT. 2000 Ver 1.2 39

GMS90C320

Plastic Package P-LCC-44

(Plastic Leaded Chip-Carrier)

44PLCC

0.656

0.650

0.695

0.685

0.695

0.685

0.656

0.650

UNIT: INCH

min. 0.020

0.032

0.026

0.021

0.013

0.630

0.590

0.050 BSC

0.012

0.0075

0.120

0.090

0.180

0.165

40 OCT. 2000 Ver 1.2

Plastic Package P-DIP-40

(Plastic Dual in-Line Package)

40DIP

0.200 max.

2.075

2.045

min. 0.015

UNIT: INCH

0.600 BSC

0.550

0.530

GMS90C320

0.022

0.015

0.065

0.045

0.100 BSC

0.140

0.120
0-15°

2

1

0

.

0

8

0

0

.

0

OCT. 2000 Ver 1.2 41

GMS90C320

Plastic Package P-MQFP-44

(Plastic Metric Quad Flat Package)

P-MQFP-44

9.90

10.10

13.45

12.95

13.45

12.95

10.10

9.90

SEE DETAIL “A”

2.10

1.95

UNIT: MM

0-7°

3

3

2

1

.

.

0

0

2.35 max.

0.45

0.30

0.80 BSC

0.25

0.10

1.60
REF

DETAIL “A”

1.03

0.73

42 OCT. 2000 Ver 1.2