Datasheet GLT6200L16SLI-55FG, GLT6200L16SL-85TC, GLT6200L16SL-85FG, GLT6200L16SL-70TC, GLT6200L16SL-70FG Datasheet (G-LINK)

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 1 -

Features : Description :

∗ Low-power consumption.

-active: 30mA Icc at 55ns.

-stand by :
10 µA (CMOS input / output , LL)
2 µA (CMOS input / output, SL)

∗ Single +2.7V to 3.6V power supply.
∗ Equal access and cycle time.
∗ 55\70\85 ns access time.
∗ Tri-state output.
∗ Automatic power-down when

deselected.

∗ Multiple center power and ground pins

for improved noise immunity.

∗ Individual byte controls for both read

and write cycles.

∗ Industrial grade (-40°C ~ 85°C)

available.

∗ Available in 48-fpBGA/44L TSOPII.

The GLT6200L16 is a low power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW

CE1 and OE pin.

This device has an automatic power – down
mode feature when deselected. Separate Byte

Enable controls ( BLE and BHE ) allow individual
bytes to be accessed. BLE controls the lower bits
I/O0 – I/O7. BHE controls the upper bits I/O8 –

I/O15.

Writing to these devices is performed by taking
Chip Enable CE1 with Write Enable WE and byte

Enable ( BLE / BHE ) Low

Reading from the device is performed by taking
Chip Enable CE1 with Output enable OE and byte

Enable ( BLE / BHE ) Low while Write Enable WE
and CE2 are held HIGH.

Function Block Diagram :

Row Select

Memory Array

1024 x 2048

Pre-Charge Circuit

I/O Circuit

Column Select

Data

Circuit

Data

Circuit

Vcc
Vss

WE

OE

BLE

BHE

CE1

I/O8 - I/O15

I/O0 - I/O7

Control

Logic

Column Address

Row Address

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 2 -

BHE

Pin Configurations :

GLT6200L16

A4

1
2
3
4
5

6
7

9
10

12
13

14

Vcc

8

15
16
17
18
19
20
21 24

25

26

27

28

29

30

31

32

33

35

36

37

38

39

40

41

42

43

44

CE1

I/O0

OE

BLE

22 23

3411Vcc

WE

A3
A2
A1
A0

I/O1
I/O2
I/O3

Vss
I/O4
I/O5
I/O6
I/O7

A16
A15
A14
A13 A11

A10

A9

A8

NC

I/O8

I/O9

I/O10

I/O11

Vss

I/O12

I/O13

I/O14

I/O15

BHE

A7

A6

A5

A12 NC

48 Ball fpBGA :

1 2 3 4 5 6 7 8 A B C D E F G H

¡¡¡¡¡¡¡

¡

1

BLE

I/O8 I/O9 Vss Vcc I/O14 I/O15 NC

¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡

2

OE

I/O10 I/O11 I/O12 I/O13 NC A8

¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡

3

A0 A3 A5 NC NC A14 A12 A9

¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡

4

A1 A4 A6 A7 A16 A15 A13 A10

¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡

5

A2

CE1

I/O1 I/O3 I/O4 I/O5

WE

A11

¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡

6

NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC

Note : NC means no Ball.

Pin Descriptions:

Name

Function

A0 – A

16

Address Inputs

CE

1

Chip Enable Input

OE

Output Enable Input

WE

Write Enable Input

I/O0 – I/O

15

Data Input and Data Output

V

CC

2.7V~3.6V Power Supply

BLE

Lower Byte Enable Input ( I/O0 to I/O7)

BHE

Higher Byte Enable Input ( I/O8 to I/O15)

GND Ground
NC No Connection

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 3 -

Truth Table:

CE1 OE WE BLE BHE

I/O0-I/O7 I/O8-I/O15 Power Mode

HXXXX

High-Z High-Z

Standby

Deselected

XXXXX

High-Z High-Z

Standby

Deselected

XXXHH

High-Z High-Z

Standby

Deselected

LHHLX

High-Z High-Z

Active

Output Disabled

LHHXL

High-Z High-Z

Active

Output Disabled

LLHLH

Data Out High-Z

Active

Lower Byte Read

LLHHL

High-Z Data Out

Active

Upper Byte Read

LLHLL

Data Out Data Out

Active

Word Read

LXLLH

Data In High-Z

Active

Lower Byte Write

LXLHL

High-Z Data In

Active

Upper Byte Write

LXLLL

Data In Data In

Active

Word Write

Note ; X means don care. (Must be low or high state).

Absolute Maximum Ratings*

Parameter Symbol Minimum Maximum Unit

Voltage on Any Pin Relative to Gnd Vt -0.5 Vcc + 0.3 V
Power Dissipation P

T

- 1.0 W

Storage Temperature (Plastic) Tstg -55 +150

°C

Temperature Under Bias Tbias -25 +85

°C

*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Recommended Operating Conditions ( TA = -25°C to 85°C )

Parameter Symbol Min Typ Max Unit

V

CC

2.7 3 3.6 V

Supply Voltage

Gnd 0.0 0.0 0.0 V

V

IH

2.2 - VCC+0.2 V

Input Voltage

V

IL

-0.5* - 0.6 V

* VIL min = -2.0V for pulse width less than tRC/2.

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 4 -

DC Operating Characteristics ( Vcc=2.7 to 3.6V, T

A

= -25°C to 85°C )

55 70 85

UnitParameter Sym. Test Conditions

Min Max Min Max Min Max

Input Leakage Current

I

LI

VCC = Max,
Vin = Gnd to V

CC

1 1 1

µA

Output Leakage
Current

I

LO

CE1 =V

IH

or VCC = Max,

V

OUT

= Gnd to V

CC

1 1 1

µA

Operating Power
Supply Current

I

CC

CE1

=VIL ,VIN=VIH or VIL, I

OUT

=0

5 5 5

mA

I

CC1IOUT

= 0mA,

Min Cycle, 100% Duty

30 30 25 mA
Average Operating
Current

I

CC2

CE1 ≤ 0.2V

I

OUT

= 0mA,

Cycle Time=1µs, 100% = Duty

3 3 3 mA

Standby Power Supply

Current(TTL Level)

I

SB

CE1 =V

IH

0.5 0.5 0.5 mA

GLT6200L16LL

10 10 10

µA

Standby Power Supply
Current (CMOS Level)

I

SB1

CE1 ≥ V

CC

-

0.2V
VIN ≤ 0.2V or
VIN ≥ VCC-0.2V

GLT6200L16SL

2 2 2

µA

Output Low Voltage V

OLIOL

= 2.1 mA 0.4 0.4 0.4 V

Output High Voltage V

OHIOH

= -1 mA 2.4 2.4 2.4 V

Data Retention

Parameter Sym. Test Conditions Min. Max. Unit

VCC for Data retention

V

DR

1.0 - V

Data Retention Current

I

CCDR

- 2

µA

Chip Deselect to Data Retention Time

t

CDR

0 - ns

Operating Recovery Time

(2)

t

R

CE1

≥

VCC -0.2V

V

IN

≥

VCC -0.2V or

V

IN

≤ 0.2V

t

RC

- ns

Data Retention Waveform (TA = -25°C to +85°C)

Data Retention Mode

Vcc

CE1

VDR

VDR >= 1.0V

tRtCDR

2.7V

2.7V

VIH

VIH

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 5 -

AC Test Conditions AC Test Loads and Waveforms

CL*

TTL

Output Load Condition *Including Scope and Jig Capacitance
CL = 30pf + 1TTL Load

Read Cycle

(9)

( Vcc=2.7V to 3.6V, TA = -25°C to 85°C )

55 70 85

Parameter Symbol

Min Max Min Max Min Max

Unit Note

Read Cycle Time t

RC

55 70 85 ns

Address Access Time t

AA

55 70 85 ns

Chip Enable Access Time t

ACE

55 70 85 ns

Output Enable Access Time t

OE

35 40 40 ns

Output Hold from address Change t

OH

10 10 10 ns

Chip Enable to Output in Low-Z t

LZ

10 10 10 ns 4,5

Chip Disable to Output in High-Z t

HZ

25 30 35 ns 3,4,5

Output Enable to Output in Low-Z t

OLZ

5 5 5 ns

Output Disable to Output in High-Z t

OHZ

25 25 30 ns

BLE , BHE Enable to Output in Low-Z

t

BLZ

5 5 5 ns 4,5

BLE , BHE Disable to Output in High-Z

t

BHZ

25 25 30 ns 3,4,5

BLE , BHE Access Time

t

BA

35 40 85 ns

Timing Waveform of Read Cycle 1 (Address Controlled)

D

OUT

tRC

Address

t

OH

tAA

Previous Data Valid

Data Valid

Input Pulse Levels 0.4V to 2.4V
Input Rise and Fall Time
Input and Output Timing
Reference Level

5 ns

1.4V

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 6 -

Timing Waveform of Read Cycle 2

(3~5)

DOUT

tRC

Address

tACE

tAA

tLZ

tOE

tBA

tOLZ

tBLZ

tHZ

tBHZ

tOHZ

tOH

Data Valid

High - Z

CE1

UB / LB

OE

Write Cycle

(11)

( Vcc=2.7 to 3.6V, TA = -25°C to 85°C )

55 70 85

Parameter Symbol

Min Max Min Max Min Max

Unit Note

Write Cycle Time t

WC

55 70 85 ns

Chip Enable to Write End t

CW

50 60 70 ns

Address Setup to Write End t

AW

50 60 70 ns

Address Setup Time t

AS

0 0 0 ns

Write Pulse Width t

WP

45 50 60 ns

Write Recovery Time t

WR

0 0 0 ns

Data Valid to Write End t

DW

25 30 35 ns

Data Hold Time t

DH

0 0 0 ns

Write Enable to Output in High-Z t

WHZ

25 30 35 ns

Output Active from Write End t

OW

5 5 5 ns

BLE , BHE Setup to Write End

t

BW

50 60 70 ns

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 7 -

Timing Waveform of Write Cycle 1 (Address Controlled)

(2~6,8)

DOUT

tWC

Address

tAW tWR

CE1

UB / LB

WE

tCW

tBW

tAS

tWP

tDW tDH

tOW

High-Z

High-Z

D

IN

Timing Waveform of Write Cycle 2 ( CE1 Controlled)

(2~6,8)

DOUT

tWC

Address

tAW

tWR

CE1

UB / LB

WE

tCW

tAS tBW

tWP

tDW

tDH

tWHZtLZ

High - Z

High - Z

High - Z

D

IN

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 8 -

Timing Waveform of Write Cycle 4 ( UB / LB Controlled)

(2~6,8)

DOUT

tWC

Address

t

AW

t

WR

CE1

UB / LB

WE

tCW

t

AS tBW

t

WP

t

DW

tDH

t

WHZ

t

BLZ

High - Z

High - Z

High - Z

DIN

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 9 -

Notes :

1. L-version includes this feature.

2. This Parameter is samples and not 100% tested.

3. For test conditions, see AC Test Condition.

4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is HIGH for read cycle.

7. CE1 and OE are LOW and CE2 is HIGH for read cycle.

8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.

9. All read cycle timings are referenced from the last valid address to the first transition address.

10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 10 -

Ordering Information

Part Number SPEED POWER PACKAGE

GLT6200L16LL-55TC 55ns Normal TSOPII 44L
GLT6200L16LL-70TC 70ns Normal TSOPII 44L

GLT6200L16LL-85TC 85ns Normal TSOPII 44L
GLT6200L16LLI-55TC 55ns Normal TSOPII 44L
GLT6200L16LLI-70TC 70ns Normal TSOPII 44L
GLT6200L16LLI-85TC 85ns Normal TSOPII 44L

GLT6200L16SL-55TC 55ns Normal TSOPII 44L

GLT6200L16SL-70TC 70ns Normal TSOPII 44L

GLT6200L16SL-85TC 85ns Normal TSOPII 44L

GLT6200L16SLI-55TC 55ns Normal TSOPII 44L
GLT6200L16SLI-70TC 70ns Normal TSOPII 44L
GLT6200L16SLI-85TC 85ns Normal TSOPII 44L

GLT6200L16LL-55FG 55ns Normal fpBGA 48L

GLT6200L16LL-70FG 70ns Normal fpBGA 48L

GLT6200L16LL-85FG 85ns Normal fpBGA 48L
GLT6200L16LLI-55FG 55ns Normal fpBGA 48L
GLT6200L16LLI-70FG 70ns Normal fpBGA 48L
GLT6200L16LLI-85FG 85ns Normal fpBGA 48L
GLT6200L16SL-55FG 55ns Normal fpBGA 48L
GLT6200L16SL-70FG 70ns Normal fpBGA 48L
GLT6200L16SL-85FG 85ns Normal fpBGA 48L

GLT6200L16SLI-55FG 55ns Normal fpBGA 48L
GLT6200L16SLI-70FG 70ns Normal fpBGA 48L
GLT6200L16SLI-85FG 85ns Normal fpBGA 48L

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 11 -

Parts Numbers (Top Mark) Definition :

GLT 6 200 L 16 LL I - 55 TC

4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM

-SRAM

064 : 8K
256 : 256K
512 : 512K
100 : 1M

-DRAM

10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)

-SDRAM

40 : 4M
160 : 16M
640 : 64M

VOLTAGE

Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V

CONFIG.

04 : x04
08 : x08
16 : x16
32 : x32

SPEED

-SRAM

12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns

-DRAM

30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns

SDRAM :

5 : 5ns/200 MHZ

5.5 : 5.5ns/182 MHZ
6 : 7ns/166 MHZ
7 : 8ns/125 MHZ
10 : 10ns/100 MHZ

PACKAGE

T : PDIP(300mil)
TS : TSOP(Type I)
ST : sTSOP(Type I)
TC : TSOPll (40/44)
TD : TSOPII (44/50)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8

POWER

Blank : Standard
L : Low Power
LL : Low Low Power
SL : Super Low Power

Temperature Range

E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 12 -

Package Information

44 pin Small Outline J-form Package (TSOPII)

G-LINK

GLT6200L16

Ultra Low Power 128k x 16 CMOS SRAM

May 2001(Rev. 2.3)

G-Link Technology Corporation

2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 13 -

GLT6200L16 fpBGA

ABCDEFGH

1
2
3
4
5
6

OOOOOOOO
OOOOOOOO
OOOOOOOO
OOOOOOOO
OOOOOOOO
OOOOOOOO

PACKAGE OUTLINE DWG.

SYMBOL UNIT : MM

A 1.10±0.1

A1 0.22±0.05

∅b 0.35

C 0.36TYP
D 8.00±0.10

D1 5.25

E 6.00±0.10

E1 3.75

e 0.75TYP

aaa 0.10

aaa

∅b