Datasheet GLT41216-45TC, GLT41216-45J4, GLT41216-40TC, GLT41216-40J4, GLT41216-35TC Datasheet (G-LINK)
...Page 1
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 1 -
Features : Description :
∗ 65,536 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual
WE
Input.
∗ Low power dissipation.
∗ Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ,and 40/44
pin TSOP(II).
∗ Single 5.0V±10% Power Supply, Except
5V+5%,-10% for 30ns TSOPII Package.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
The GLT41216 is a 65,536 x 16 bit highperformance CMOS dynamic random access
memory. The GLT41216 offers Fast Page
mode with Extended Data Output, and has
both BYTE WRITE and WORD WRITE
access cycles via two WE pins. The
GLT41216 accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 256 x 16 bits, within a page, with cycle
times as short as 12ns.
The GLT41216 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE 30 35 40 45
Max.
RAS
Access Time, (t
RAC
)
30 ns 35 ns 40 ns 45 ns
Max. Column Address Access Time, (tAA) 15 ns 18 ns 20 ns 22 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC) 12 ns 13 ns 15 ns 18 ns
Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 75 ns 80 ns
Max.
CAS
Access Time (t
CAC
)
10 ns 11 ns 12 ns 12 ns
Page 2
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 2 -
Pin Configuration :
Pin Descriptions:
Name Function
A0 - A
7
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
UW
Read/Upper Byte Write Enable
LW
Read/Lower Byte Write Enable
OE
Output Enable
DQ0 - DQ
15
Data Inputs / Outputs
V
CC
+5V Power Supply
V
SS
Ground
NC No Connection
GLT41216
SOJ Top View
TSOP(Type II)
Top View
Page 3
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 3 -
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
.......................................-0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS
,
CAS,UW, LW,OE
Data Input/ Output
Max.
5
7
7
Unit
pF
pF
pF
*Note: Operation above Absolute Maximum Ratings
can adversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
WE
means
UW
andLW.
l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
Page 4
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 4 -
Extended Data Output (EDO) Page Mode
The EDO page mode is a kind of page mode with enhanced features. The two major features
of the EDO page mode are as follows.
1. Data output time is extended.
In the EDO page mode, the output data is held to the next
CAS
cycle‘s falling edge,
instead of the rising edge. For this reason, valid data output time in the EDO page mode is
extended compared with the fast page mode (=data extend function). In the fast page mode,
the data output time becomes shorter as the
CAS
cycle time becomes shorter. Therefore, in
the EDO page mode, the timing margin in read cycle is larger than of the fast page mode
even if the
CAS
cycle time becomes shorter.
2. The
CAS
cycle time in the EDO page mode is shorter than that in the fast page mode.
In the EDO page mode, due to the data extend function, the
CAS
cycle time can be
shorter than in the fast page mode if the timing margin is the same.
Taking a device whose t
RAC
is 60ns as an example, the
CAS
cycle time in the EDO page
mode is 25ns while that in the fast page mode is 40ns.
In the EDO page mode, read (data out) and write (data in) cycles can be executed
repeatedly during one
RAS
cycle. The EDO page mode allows both read and write
operations during one cycle, but the performance is equivalent to that of the fast page mode
in that case.
Page 5
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 5 -
Truth Table: GLT41216
Function
RAS
CAS
UWLWOE
ADDRESS DQs Note
s
Standby H
H→X
X X X High-Z
Read: Word L L H H L ROW/COL Data Out
Write: Word(Early Write) L L L L X ROW/COL Data-In
Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
Write: Upper Byte (Early) L L L H X ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
Read Write L L
H→L H→L L→H
ROW/COL Data-Out,Data-In 1,2
EDO-Page- 1st Cycle L
H→L
H H L ROW/COL Data-Out 1
Mode Read 2nd Cycle L
H→L
H H L COL Data-Out 1
EDO-Page- 1st Cycle L
H→L
L L X ROW/COL Data-In 2
Mode Write
2nd Cycle L
H→L
L L X COL Data-In 2
EDO-Page-
1st Cycle L
H→L H→L H→L L→H
ROW/COL Data-Out,Data-In 1,2
Mode ReadWrite
2st Cycle L
H→L H→L H→L L→H
COL Data-Out,Data-In 1,2
Hidden Read
L→H→L
L H H L ROW/COL Data-Out 1
Refresh Write
L→H→L
L L L X ROW/COL Data-In 2,3
RAS
-Only Refresh
L H X X X ROW High-Z
CBR Refresh
H→L
L X X X High-Z
Notes:
1. These READ cycles are always WORD READ cycles.
2. These WRITE cycles may also be BYTE READ cycles (either
UW
or LW active).
3. EARLY WRITE only.
Page 6
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 6 -
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym. Parameter Test Conditions Access
Time
Min. Typ Max. Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V ≤ V
IN
≤ 5.5V
(All other pins not under
test=0V)
-10 +10
µA
I
LO
Output Leakage Current
(for High-Z State)
0V ≤ V
out
≤ 5.5V
Output is disabled (Hiz)
-10 +10
µA
I
CC1
Operating Current,
Random READ/WRITE tRC = tRC (min.)
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
180
170
160
150
mA 1,2
I
CC2
Standby Current,(TTL)
RAS
,
CAS
, at V
IH
other inputs ≥V
SS
2 mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
CAS
, at
V
IH
tRC = tRC (min.)
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
180
170
160
150
mA 2
I
CC4
Operating Current,
EDO Page Mode
RAS
at VIL,
CAS
address cycling:
t
PC
= tPC(min.)
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
180
170
160
150
mA 1,2
I
CC5
Refresh Current,
CAS Before
RAS
RAS
,
CAS
,
address cycling:
t
RC
= tRC (min.)
t
RAC
= 30ns
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 45ns
180
170
160
150
mA 1
I
CC6
Standby Current, (CMOS)
RAS
≥VCC-0.2V,
CAS
≥VCC-0.2V,
All other inputs V
SS
1 mA
V
IL
Input Low Voltage -1 +0.8 V 3
V
IH
Input High Voltage 2.4 VCC+1 V 3
V
OL
Output Low Voltage IOL = 4.2mA 0.4 V
V
OH
Output High Voltage IOH = -5mA 2.4 V
Notes:
1. I
CC
is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with
the output open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of
one transition per address cycle in random Read/Write and EDO Fast Page Mode.
3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period
not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
Page 7
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 7 -
AC Characteristics
TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V
An initial pause of 100 µs and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
30 35 40 45
Parameter Symbol Min. Max. Min. Max. Min.Max. Min.Max. Unit Notes
Read or Write Cycle Time
t
RC
65 70 75 80 ns
Read Modify Write Cycle Time
t
RWC
85 87 93 103 ns
RAS
Precharge Time
t
RP
25 25 25 30 ns
RAS
Pulse Width
t
RAS
30 100k 35 100k 40 100k 45 100k ns
Access Time from
RAS
t
RAC
30 35 40 45 ns 1,2,3
Access Time from
CAS
t
CAC
10 11 12 12 ns 1,5,10
Access Time from Column Address
t
AA
15 18 20 22 ns 1,5,6
CAS
to Output Low-Z
t
CLZ
0 0 0 0 ns
CAS
to Output High-Z
t
CEZ
3 3 8 3 8 3 8 ns
RAS
Hold Time
t
RSH
10 12 12 13 ns
RAS
Hold Time Referenced to
OE
t
ROH
7 8 8 9 ns
CAS
Hold Time
t
CSH
25 30 34 40 ns
CAS
Pulse Width
t
CAS
4.5 6 10K 6 10K 7 10K ns
RAS
to
CAS
Delay Time
t
RCD
13 17 24 18 28 18 33 ns
RAS
to Column Address Delay Time
t
RAD
10 12 17 13 20 13 23 ns 7
CAS
to
RAS
Precharge Time
t
CRP
5 5 5 5 ns
Row Address Set-Up Time
t
ASR
0 0 0 0 ns
Row Address Hold Time
t
RAH
6 7 8 8 ns
Column Address Set-Up Time
t
ASC
0 0 0 0 ns
Column Address Hold Time
t
CAH
6 6 6 6 ns
Column Address to
RAS
Lead Time
t
RAL
15 18 20 23 ns
Column Address Hold Time Referenced to
RAS
t
AR
26 30 34 39 ns
Read Command Set-Up Time
t
RCS
0 0 0 0 ns
Read Command Hold Time Referenced to
CAS
t
RCH
0 0 0 0 ns 4
Read Command Hold Time Referenced to
RAS
t
RRH
0 0 0 0 ns 4
Write Command Set-Up Time
t
WCS
0 0 0 0 ns 8,9
Write Command Hold Time
t
WCH
6 6 6 6 ns
Write Command Pulse Width
t
WP
6 6 6 6 ns
Page 8
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 8 -
AC Characteristics
30 35 40 45
Parameter Symbol Min. Max. Min. Max. Min. Max. Min.Max. Unit Notes
Write Command to
RAS
Lead Time
t
RWL
10 11 12 12 ns
Write Command to
CAS
Lead Time
t
CWL
10 11 12 12 ns
Data Set-Up Time
t
DS
0 0 0 0 ns
Data Hold Time
t
DH
6 7 8 8 ns
Data Hold Time Referenced to
RAS
t
DHR
26 31 36 41 ns
RAS
to WE Delay Time
t
RWD
44 49 54 59 ns
CAS
to WE Delay Time
t
CWD
22 23 24 24 ns
Column Address to WE Delay Time
t
AWD
25 30 32 34 ns
RAS
to
CAS
Precharge Time
t
RPC
0 0 0 0 ns
Access Time from
CAS
Precharge
t
CPA
17 20 22 24 ns
EDO Page Mode Cycle Time
t
PC
12 13 15
18 ns
EDO Page Mode Read-Modify-Write Cycle Time
t
PRWC
43 47 50 52 ns
CAS
Precharge Time (EDO Page Mode)
t
CP
4.5 5 5 7 ns
RAS
Pulse Width (EDO Page Mode Only)
t
RASP
30 100k 35 100k 40 100k 45 100k ns
Access Time from
OE
t
OEA
10 11 12 12 ns
OE
to Data Delay Time
t
OED
8 8 8 8 ns
OE
to Output High-Z
t
OEZ
3 8 3 8 3 8 3 8 ns
OE
Command Hold Time
t
OEH
6 6 7 7 ns
Data Output Hold after
CAS
low
t
DOH
3 3 3 5 ns
RAS
to Output High-Z
t
REZ
3 8 3 8 3 8 3 8 ns
WE
to Output High-Z
t
WEZ
3 10 3 10 3 10 3 10 ns
OE
to
CAS
Hold Time
t
OCH
8 8 8 8 ns
CAS
Hold Time to
OE
t
CHO
8 8 8 8 ns
OE
Precharge Time
t
OEP
8 8 8 8 ns
CAS
Set-Up Time for
CAS
-before-
RAS
Cycle
t
CSR
10 10 10 10 ns
CAS
Hold Time for
CAS
-before-
RAS
Cycle
t
CHR
10 10 10 10 ns
Transition Time
t
T
1.5 50 2 50 2 50 2 50 ns
Refresh Period
t
REF
4 4 4 4 ms
Page 9
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 9 -
Notes:
1. Measure with a load equivalent to 1TTL inputs and 50 pF.
2. Assumes that t
RCD
≤ t
RCD
(max.). If t
RCD
is greater than t
RCD
(max.), access time will be t
AA
dominant.
3. Assumes that t
RAD
≤ t
RAD
(max.). If t
RAD
is greater than t
RCD
(max.), access time will be
controlled by t
CAC
.
4. Either t
RRH
or t
RCH
must be satisfied for a Read Cycle.
5. Access time is determined by the longest of tAA, t
CAC
and t
CPA
.
6. Assumes that t
RAD
≥ t
RAD
(max.).
7. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.)
is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(max.)
limit, the access time is controlled by tAA and t
CAC
.
8. t
WCS
, t
RWD
, t
AWD
and t
CWD
are not restrictive operating parameters.
9. t
WCS
(min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of
CAS
or
WE
.
11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.
Page 10
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 10 -
Read Cycle
ROW
ADDRESS
COLUMN
ADDRESS
DATA-OUT
tRC
tRAS
tRP
tCRP
tCSH
t
RCD
t
RSH
tCAS
tCRP
tASR tRAH
t
RAD
tASC
tCAH
t
RAL
tRCH
tRRH
tAR
tRCS
tAA
t
OEA
tCEZ
tOEZ
t
CAC
tCLZ
tRAC
Don't Care
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
V
IL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
Early Write Cycle NOTE : D
OUT
= OPEN
tRP
tRC
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
tASR
tRAH
tRAD
tASC
tCAH
tRAL
tCWL
tRWL
tWCR
tWCH
tWP
tWCS
tAR
tDS tDH
tDHR
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
Don't Care
tRAS
Page 11
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 11 -
OE Controlled Write Cycle NOTE : D
OUT
= OPEN
t
RP
t
RC
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
RAL
DATA - IN
COLUMN
ADDRESS
ROW
ADDRESS
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
IH-
V
IL-
DQ
Don't Care
t
RAS
t
RCS
t
CWL
t
RWL
t
WP
t
DS
t
OED
t
OEH
t
DH
Read - Modify - Write Cycle
t
RP
t
RC
t
CRP
t
CRPtRCD
t
RSH
VALID
DATA-OUT
COLUMN
ADDRESS
ROW
ADDR.
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
Don't Care
t
RAS
VALID
DATA-IN
t
CAS
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
CSH
t
AWD
t
CWD
t
RWL
t
CWL
t
WP
t
OEA
t
CLZ
t
CAC
t
AA
t
RAC
t
DH
t
DS
t
OED
t
OEZ
Page 12
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 12 -
EDO Page Mode Read Cycle NOTE : D
OUT
= OPEN
tRASP tRP
tCRP
tRCD tCAS
tCSH
tCP
tCAS
tCAS tCAS
tCP tCP
tPC tPC tPC
tCSR
tRAH
tRAD
tASC
tASC
tASC
tASC
tCAH
tCAH
tCAH
tCAH
tRCS
tRCH
tRRH
tOEA
tOEA
tCAC
tCPA
tAA
tOCH
tCPA
tAA
tCAC
tOEP
tCHO
tAA
tCAC
tCPA
tCLZ
tOLZ
tRAC
tCAC
tDOH
tOEZ
tOEP
tOEZ tOEZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VIH-
VIL-
RAS
VIH-
VIL-
CAS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ
VOH-
VOL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COL.
ADDR.
COL.
ADDR.
Don't Care
tRHCP
EDO Page Mode Early Write Cycle NOTE : D
OUT
= OPEN
tRASP tRP
tCRP
tRCD tCAS
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tCAS
tCAS
tCP tCP
t
PC
t
PC
tRSH
tASR
t
RAD
t
RAH
tASC
tCAH
tCSH
tASC tASC
tCAH tCAH
tWCS
tWP
tWCH tWCS tWCStWCH
tWCH
tWP tWP
tDS tDS tDStDH
tDS
tDS
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ
VIH-
VIL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
tRHCP
Page 13
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 13 -
EDO Page Mode Read - Modify - Write Cycle NOTE : D
OUT
= OPEN
t
RASP
t
RP
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
Don't Care
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
RSH
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
t
PRWC
t
RCS
t
WP
t
CWL
t
WP
t
CWL
t
RWL
t
CWD
t
AWD
t
RWD
t
OEA
t
CWD
t
AWD
t
CPWD
t
OEA
t
OEH
t
RAC
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
AA
t
CAC
t
OEZ
t
OED
t
DS
t
DH
t
CLZ
t
CLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
V
I/OH-
V
I/OL-
DQ
EDO Page Read And Write Mixed Ccycle
t
RASP
t
RP
t
CAS
t
HPC
t
CAS
t
CAS
t
CP
t
CP
t
CP
t
ASR
t
HPC
t
HPC
t
RAH
t
ASC
t
CAH
t
ASC
t
ASC
t
ASC
t
CAH
t
CAH
t
CAH
t
RCS
t
RCH
t
RCS
t
RCH
t
RCH
t
WCStWCH
t
WPE
t
CPA
t
CLZ
t
WED
t
WEZ
t
RAC
t
AA
t
CAC
t
OEA
t
WEZ
t
DS
t
DH
t
AA
t
REZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
ROW
ADDR
COL.
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
RAS
CAS
ADDRESS
WE
OE
DQ
0
~DQ
3
Don't Care
Page 14
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 14 -
CAS
- Before -
RAS
Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
CSR
t
CSR
t
CHR
t
CHR
t
RPC
t
RPCtCRP
V
IH-
V
IL-
CAS
t
WRH
t
WRP
V
IH-
V
IL-
WE
t
WRPtWRH
Remark Address, OE : Don’t care DQ : Hi - Z
RAS
-Only Refresh Cycle
V
IH-
V
IL-
RAS
t
RAS
t
RAS
t
RP
t
RP
t
RC
t
RC
t
RPC
t
CRP
V
IH-
V
IL-
CAS
t
CRP
t
ASR
t
ASR
t
RAH
t
RAH
ROW
ADDRESS
ROW
ADDRESS
Address
V
IH-
V
IL-
Remark WE, OE : Don’t care DQ : Hi - Z
Hidden Refresh Cycle ( Read )
tRP
t
CRP
tRCD
VIH-
VIL-
RAS
VIH-
VIL-
CAS
tRAC
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
DQ
V
IH-
VIL-
ROW
ADDRESS
Don't Care
tRP
tCAC
tRCS
tASC tCAHtASR tCAH
tRAD tRAL
tRSH
tCHR
t
RC
tRAS tRAS
COLUMN
ADDRESS
t
RC
tWRH
tAA
tOEA
tCLZ
tREZ
tCEZ
tWEZ
tOEZ
DATA-OUT
OPEN
tWRPtRRH
Page 15
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 15 -
Hidden Refresh Cycle ( Write ) NOTE : D
OUT
= OPEN
t
RP
tCRP
tRCD
V
IH-
V
IL-
RAS
V
IH-
V
IL-
CAS
tDS
V
IH-
V
IL-
Address
V
IH-
V
IL-
WE
V
IH-
V
IL-
OE
DQ
V
IH-
V
IL-
ROW
ADDRESS
Don't Care
tRP
tDH
tWP
tWCH
t
WCS
tASC
tCAHtASC
tCAH
tRAD tRSH
tRSH
tCHR
tRC
t
RAS
t
RAS
COLUMN
ADDRESS
DATA-IN
t
WRPtWRH
Page 16
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 16 -
CAS-Before RAS Refresh Counter Test Cycle
tCAS
tCPT
VIH-
VIL-
RAS
VIH-
VIL-
CAS
t
RP
tRAS
tCSR
tCHR
tRSH
tRAL
tASC
tAA
tCAC
tRCS
tRRH
tRCH
tWRP tWRH
tWRHtWRP
tOEA
tCEZ
tOEZ
tCLZ
tRWL
tCWL
tWCH
tWCS
tWP
tDS
tDH
tRCS
tAWD
tCWD tRWL
tCWL
tWP
tDH
tDS
tOED
tOEZ
tCLZ
tCAC
tAA
tOEA
OPEN
COLUMN
ADDRESS
VALID DATA-OUT
VALID DATA-IN
Don't Care
VALID
DATA-IN
VALID
DATA-OUT
VIH-
VIL-
Address
VIH-
VIL-
WE
VIH-
VIL-
OE
VOH-
VOL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VIH-
VIL-
DQ
VIH-
VIL-
WE
VIH-
VIL-
OE
VI/OH-
VI/OL-
DQ
Read Cycle
Write Cycle
Read-Modify-Write
tCAH
tWRP tWRH
Page 17
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 17 -
Ordering Information
Part Number SPEED POWER FEATURE PACKAGE
GLT41216-30J4 30ns Normal EDO SOJ 400mil 40L
GLT41216-35J4 35ns Normal EDO SOJ 400mil 40L
GLT41216-40J4 40ns Normal EDO SOJ 400mil 40L
GLT41216-45J4 45ns Normal EDO SOJ 400mil 40L
GLT41216-30TC 30ns Normal EDO TSOP 400mil 44L
GLT41216-35TC 35ns Normal EDO TSOP 400mil 44L
GLT41216-40TC 40ns Normal EDO TSOP 400mil 44L
GLT41216-45TC 45ns Normal EDO TSOP 400mil 44L
Parts Numbers (Top Mark) Definition :
GLT 4 12 16 - 30 J4
Note : CÙCDROM , HÙHDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
Page 18
G-LINK
GLT41216
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug 1999 (Rev.2.1)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 18 -
Package Information
400mil 40 pin Small Outline J-form Package (SOJ)
40/44 Lead Thin Small Outline Package TSOP(Type II)
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