Datasheet GAL6002B-20LP, GAL6002B-20LJ, GAL6002B-15LP, GAL6002B-15LJ Datasheet (Lattice Semiconductor Corporation)

GAL6002

High Performance E2CMOS FPLA

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS

®

Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL PINS

• LOW POWER CMOS
— 90mA Typical Icc

2

CELL TECHNOLOGY

• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells

• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL

®

and FPLA Devices

• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration

Description

Functional Block Diagram

ICLK

INPUT

CLOCK

INPUTS

2-11

2

11

ILMC

{

OUTPUT
ENABLE

RESET

D

E

14

23

OLMC

OCLK

0

7

BLMC

AND

OR

D

E

Macrocell Names

ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL

PinNames

I0 - I
ICLK INPUT CLOCK V
OCLK OUTPUT CLOCK GND GROUND

INPUT I/O/Q BIDIRECTIONAL

10

POWER (+5V)

CC

14

23

IOLMC

OUTPUTS

{

OUTPUT

14 - 23

CLOCK

Having an FPLA architecture, the GAL6002 provides superior

Pin Configuration

flexibility in state-machine design. The GAL6002 offers the highest

GND

DIP

1
I
I

GAL

I
I

6002

6

I
I

I
I
I

I

12

Vcc

24

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

18

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK

13

degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E

2

CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.

The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). T wo clock inputs are provided for
independent control of the input and output macrocells.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice

I
I
I

NC

I
I
I

Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

PLCC

NC

Vcc

I/ICLK

I

I

228

4

5

7

GAL6002

9

Top V iew

11

12 14 16 18

I

I

GND

NC

OCLK

I/O/Q

I/O/Q

I/ICLK

I/O/Q

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

I/O/Q

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

6002_02

1

GAL6002 Commercial Device Ordering Information

Commercial Grade Specifications

)sn(dpT)zHM(xamF)Am(ccI#gniredrOegakcaP

5157531PL51-B2006LAGPIDcitsalPniP-42

531JL51-B2006LAGCCLPdaeL-82

0206531PL02-B2006LAGPIDcitsalPniP-42

531JL02-B2006LAGCCLPdaeL-82

Part Number Description

Specifications GAL6002

GAL6002B

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

P = Plastic DIP
J = PLCC

2

Specifications GAL6002

Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)

The GAL6002 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is individually
configurable as asynchronous, latched, or registered inputs. Pin
1 (ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Individually configurable
inputs provide system designers with unparalleled design flexibility .
With the GAL6002, external input registers and latches are not
necessary.

Both the ILMC and the IOLMC are individually configurable and the
ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations and its associated fuse numbers are
shown in the diagrams on the following pages. Note that these
programmable cells are configured by the logic compiler software.
The user does not need to manually manipulate these architecture
bits.

Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)

The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array ,
are available at the device pins. Cells in this group are known as
Output Logic Macrocells (OLMC).

The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinational, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the
programmable polarity control cell called XORD. Polarity selection
for BLMCs is selected through the true and complement forms of
their feedbacks to the AND array. Polarity of all E (Enable) sum
terms is selected through the XORE programmable cells.

When the output or buried logic macrocell is configured as a
D/E type register, the register is clocked from the common OCLK
and the register clock enable input is controlled by the associated
"E" sum term. This configuration is useful for building counters and
state-machines with count hold and state hold functions.

When the macrocell is configured as a D type register with a sum
term clock, the register is always enabled and the associated “E”

sum term is routed directly to the clock input. This permits
asynchronous programmable clocking, selected on a register-by­register basis.

Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. All registers reset
to logic zero. With the inverting output buffers, the output pins will
reset to logic one.

There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer). When the OLMC is used as an output, the second feedback
path is through the IOLMC. With this dual feedback arrangement,
the OLMC can be permanently buried without losing the use of the
associated OLMC pin as an input, or dynamically buried with the
use of the output enable product term.

The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS, JK, and T registers with the same efficiency as a dedicated RS,
JK, or T registers.

The three macrocell configurations are shown in the diagrams on
the following pages. These programmable cells are also configured
by the logic compiler software. The user does not need to manually
manipulate these architecture bits.

3

Y

ILMC and IOLMC Configurations

ICLK

LATCH

E

D

Specifications GAL6002

Q

MUX

0 0

REG.

INPUT
or I/O

D

Generic Logic Block Diagram

Input Macrocell JEDEC Fuse Numbers

INSYNC INLATCH ILMC

INVALID

Q

ILMC/IOLMC

I/O Macrocell JEDEC Fuse Numbers

IOSYNC IOLATCH IOLMC

0 1

1 0

1 1

LATCH(i)

AND
ARRA

ISYN(i)

8218 8219 0
8220 8221 1
8222 8223 2
8224 8225 3
8226 8227 4
8228 8229 5
8230 8231 6
8232 8233 7
8234 8235 8
8236 8237 9

8238 8239 9
8240 8241 8
8242 8243 7
8244 8245 6
8246 8247 5
8248 8249 4
8250 8251 3
8252 8253 2
8254 8255 1
8256 8257 0

4

OLMC and BLMC Configurations

RESET

Specifications GAL6002

OE
PRODUCT
TERM

AND

ARRAY

IOLMC

D

E

OLMC ONLY

XORD(i)

XORE(i)

CKS(i)

Vcc

OCLK

R

D

MUX

0

Q

E

1

MUX

0

1

OLMC/BLMC

Generic Logic Block Diagram

MUX

1

I/O

0

OLMC ONLY

OSYN(i)

OLMC JEDEC Fuse Numbers

OLMC CKS OUTSYNC XORE XORD

0 8178 8179 8180 8181
1 8182 8183 8184 8185
2 8186 8187 8188 8189
3 8190 8191 8192 8193
4 8194 8195 8196 8197
5 8198 8199 8200 8201
6 8202 8203 8204 8205
7 8206 8207 8208 8209
8 8210 8211 8212 8213
9 8214 8215 8216 8217

BLMC JEDEC Fuse Numbers

BLMC CKS OUTSYNC XORE

7 8175 8176 8177
6 8172 8173 8174
5 8169 8170 8171
4 8166 8167 8168
3 8163 8164 8165
2 8160 8161 8162
1 8157 8158 8159
0 8154 8155 8156

5

Logic Diagram

Specifications GAL6002

IOLMC 9

IOLMC 7

IOLMC 5

IOLMC 4

IOLMC 3

IOLMC 2

IOLMC 1

IOLMC 8

IOLMC 6

IOLMC 0

OLMC 0

OLMC 1

OLMC 2

OLMC 3

OLMC 4

OLMC 5

OLMC 6

OLM C 9

OLMC 7

OLMC 8

ICLK

BLMC 0

BLMC 1

BLMC 2

ILMC 0

ILMC 1

ILMC 2

ILMC 3

ILMC 4

ILMC 5

ILMC 6

ILMC 8

ILMC 7

ILMC 9

3(4)

1(2)

2(3)

5(6)

4(5)

6(7)

7(9)

8(10)

9(11)

BLMC 3

10(12)

11(13)

BLMC 7

BLMC 6

BLMC 5

BLMC 4

6

Logic Diagram (Continued)

Specifications GAL6002

23(27)

1

0

Q

R

D

0

OLMC 9

XORD

22(26)

1

0

Q

R

01

E

D

1

XORE

0

OLMC 8

XORD

21(25)

1

0

Q

R

01

E

1

D

0

OLMC 7

XORE

XORD

20(24)

1

0

Q

R

01

E

D

1

XORE

0

OLMC 6

XORD

19(23)

1

0

Q

R

01

E

1

D

0

OLMC 5

XORE

XORD

18(21)

0

1

Q

R

01

E

D

1

XORE

0

OLMC 4

XORD

17(20)

0

1

Q

R

01

E

D

1

XORE

0

OLMC 3

XORD

16(19)

1

0

Q

R

01

E

D

1

XORE

0

OLMC 2

XORD

15(18)

1

0

Q

R

01

E

D

1

XORE

0

OLMC 1

XORD

14(17)

1

0

Q

R

01

E

D

E

1

XORE

0

OLMC 0

XORD

13(16)

01

1

XORE

OCLK

RESET

XORE

BLMC 7

0

1

D

E

0

R

1

Q

1

0

XORE

BLMC 6

0

1

D

E

0

R

1

Q

1

0

XORE

BLMC 5

0

1

D

E

0

R

1

Q

1

0

XORE

BLMC 4

0

1

D

E

0

R

1

Q

1

0

XORE

BLMC 3

0

1

D

E

01

R

Q

0

1

XORE

BLMC 2

0

1

D

E

01

R

Q

0

1

XORE

BLMC 1

0

1

01

D

E

R

Q

1

0

XORE

BLMC 0

0

1

01

D

E

R

Q

1

0

7

Specifications GAL6002

Absolute Maximum Ratings

(1)

Supply voltage VCC...................................... –0.5 to +7V

Input voltage applied .......................... –2.5 to VCC +1.0V

Off-state output voltage applied ......... –2.5 to VCC +1.0V

Storage Temperature ................................ –65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient Temperature with

Power Applied ........................................ –55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——-100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 ——V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —–130 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/-20 — 90 135 mA

Supply Current f

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

8

Specifications GAL6002

AC Switching Characteristics

Over Recommended Operating Conditions

COM COM

PARAM.

TEST

COND

DESCRIPTION

1

.

-15

MIN. MAX.

tpd1 A Combinatorial Input to Combinatorial Output — 15 — 20 ns
tpd2 A Feedback or I/O to Combinational Output — 15 — 20 ns
tpd3 A Transparent Latch Input to Combinatorial Output — 18 — 23 ns
tco1 A Input Latch ICLK to Combinatorial Output Delay — 20 — 25 ns
tco2 A Input Reg. ICLK to Combinatorial Output Delay — 20 — 25 ns
tco3 A Output D/E Reg. OCLK to Output Delay — 6.5 — 8ns
tco4 A Output D Reg. Sum Term CLK to Output Delay — 18 — 20 ns

2

tcf1
tcf2

— Output D/E Reg. OCLK to Buried Feedback Delay — 3.6 — 7ns

2

— Output D Reg. STCLK to Buried Feedback Delay — 10.1 — 13 ns

tsu1 — Setup Time, Input before Input Latch ICLK 1.5 — 2 — ns

-20
UNITS

MIN. MAX.

tsu2 — Setup Time, Input before Input Reg. ICLK 1.5 — 2 — ns
tsu3 — Setup Time, Input or Fdbk before D/E Reg. OCLK 1 1.5 — 13 — ns
tsu4 — Setup Time, Input or Fdbk before D Reg. Sum Term CLK 5 — 7 — ns
tsu5 — Setup Time, Input Reg. ICLK before D/E Reg. OCLK 15 — 20 — ns
tsu6 — Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK 7 — 9 — ns

th1 — Hold Time, Input after Input Latch ICLK 3 — 4 — ns
th2 — Hold Time, Input after Input Reg. ICLK 3 — 4 — ns
th3 — Hold Time, Input or Feedback after D/E Reg. OCLK 0 — 0 — ns
th4 — Hold Time, Input or Feedback after D Reg. Sum Term CLK 4 — 6 — ns

3

fmax1
fmax2
fmax3
fmax4
fmax5
fmax6

— Max. Clock Frequency w/External Feedback, 1/(tsu3+tco3) 55.5 — 47.6 — MHz

3

— Max. Clock Frequency w/External Feedback, 1/(tsu4+tco4) 43.4 — 37 — MHz

3

— Max. Clock Frequency w/Internal Feedback, 1/(tsu3+tcf1) 66 — 50 — MHz

3

— Max. Clock Frequency w/Internal Feedback, 1/(tsu4+tcf2) 66 — 50 — MHz

3

— Max. Clock Frequency w/No Feedback, OCLK 75 — 60 — MHz

3

— Max. Clock Frequency w/No Feedback, STCLK 70 — 60 — MHz

twh1 — ICLK Pulse Duration, High 6 — 7 — ns
twh2 — OCLK Pulse Duration, High 6 — 7 — ns
twh3 — STCLK Pulse Duration, High 7 — 8 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

9

Specifications GAL6002

AC Switching Characteristics (Continued)

Over Recommended Operating Conditions

COM COM

TEST

COND1.

DESCRIPTION

-15

MIN. MAX.

twl1 — ICLK Pulse Duration, Low 6 — 7 — ns
twl2 — OCLK Pulse Duration, Low 6 — 7 — ns
twl3 — STCLK Pulse Duration, Low 7 — 8 — ns
tarw — Reset Pulse Duration 12 — 15 — ns

ten B Input or I/O to Output Enabled — 15 — 20 ns

tdis C Input or I/O to Output Disabled — 15 — 20 ns

tar A Input or I/O to Asynchronous Reg. Reset — 16 — 20 ns
tarr1 — Asynchronous Reset to OCLK Recovery Time 1 1 — 14 — ns
tarr2 — Asynchronous Reset to Sum Term CLK Recovery Time 4 — 6 — ns

-20

MIN. MAX.

UNITSPARAMETER

1) Refer to Switching T est Conditions section.

10

REGISTERED
OUTPUT

t

arw

t

ar

INPUT or
I/O FEEDBACK
DRIVING AR

OCLK

Sum Term CLK

t

arr2

t

arr1

Switching Waveforms

Specifications GAL6002

INPUT or
I/O FEEDBACK

COMBINATORIAL
OUTPUT

INPUT or
I/O FEEDBACK

ICLK (LATCH)

COMBINATORIAL
OUTPUT

INPUT or
I/O FEEDBACK

Sum Term CLK

REGISTERED
OUTPUT

Registered Output (Sum T erm CLK)

t

Combinatorial Output

VALID INPUT

t

t

su1

pd3

t

h1

Latched Input

VALID INPUT

su4

t

t

1/ fmax2

VALID INPUT

pd1,2

t

h4

t

co4

co1

INPUT or
I/O FEEDBACK

ICLK (REGISTER)

COMBINATORIAL
OUTPUT

OCLK

Sum Term CLK

INPUT or
I/O FEEDBACK

OCLK

REGISTERED
OUTPUT

VALID INPUT

t

su2

t

t

co2

h2

t

Registered Input

VALID INPUT

su3

t

t

t

1/ fmax1

Registered Output (OCLK)

t

su6

h3

co3

su5

INPUT or
I/O FEEDBACK

OUTPUT

Input or I/O to Output Enable/Disable

ICLK or
OCLK

Sum Term CLK

wh1,2

t

Clock Width

t

tdis

wh3

wl1,2

t

ten

t

wl3

Asynchronous Reset

11

TEST POINT

C *

L

FROM OUTPUT (O/Q)
UNDER TEST

+5V

*C

L

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

R 2

R 1

fmax Descriptions

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured
tsu and tco.

Specifications GAL6002

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

CLK

LOGIC
ARRAY

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

Output Load Conditions (see figure)

Test Condition R1 R2 CL

A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF

Active Low 300Ω 390Ω 50pF

C Active High ∞ 390Ω 5pF

Active Low 300Ω 390Ω 5pF

12

Specifications GAL6002

Array Description

The GAL6002 contains two E2 reprogrammable arrays. The first is
an AND array and the second is an OR array . These arrays are de­scribed in detail below.

AND ARRA Y

The AND array is organized as 78 inputs by 75 product term outputs.
The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC feed­backs, and ICLK comprise the 39 inputs to this array (each available
in true and complement forms). 64 product terms serve as inputs
to the OR array . The RESET product term generates the RESET
signal described in the Output and Buried Logic Macrocells sec­tion. There are 10 output enable product terms which allow device
I/O pins to be bi-directional or tri-state.

OR ARRA Y

The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data ( “D”) terms and 18
are enable/clock (“E”) terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one “D” term and one “E” term to each.

The programmable OR array offers unparalleled versatility in prod­uct term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.

Register Preload

When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because certain events may occur during sys­tem operation that cause the logic to be in an illegal state (power­up, line voltage glitches, brown-out, etc.). T o test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.

All of the registers in the GAL6002 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the con­tents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.

Latch-Up Protection

GAL6002 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos­sibility of SCR induced latching.

Input Buffers

Electronic Signature

An electronic signature is provided with every GAL6002 device. It
contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided with every GAL6002 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND array. This cell
can be erased only during a bulk erase cycle, so the original con­figuration can never be examined once this cell is programmed.
The Electronic Signature is always available to the user, regard­less of the state of this control cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manufac­turers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

GAL6002 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

GAL6002 input buffers have active pull-ups within their input struc­ture. This pull-up will cause any un-terminated input or I/O to float
to a TTL high (logical 1). Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise

immunity and reduce Icc for the device.

Typical Input Pull-up Characteristic

0

-20

-40

Input Current (uA)

-60

1.0 2.0 3.0 4.0 5. 0

0

Input Voltage (Volts)

13

Power-Up Reset

Vcc

Specifications GAL6002

Vcc (min.)

tsu

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Circuitry within the GAL6002 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr , 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature

tpr

of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6002. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum
pulse width requirements.

twl

Internal Register
Reset to Logic "0"

Device P in
Reset to Logic "1"

Differential Product Term Switching (DPTS) Applications

The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.

DPTS =

(P-Terms)

- (P-Terms)

LH



HL

DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.

The majority of designs fall below 15 DPTS, with the upper limit
being approximately 25 DPTS. Lattice Semiconductor guarantees
and tests the commercial grade GAL6002 for functionality at
DPTS ≤30.

A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6002 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor Applications Engineering Dept. (Tel: [phone]
or 1-888-ISP-PLDS; FAX: [phone]).

14

Typical AC and DC Characteristic Diagrams

Specifications GAL6002

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55 -25 0 2 5 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 2 5 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE

FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55 -25 0 2 5 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tpd (ns)

-2
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tco (ns)

-2
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

12
10

8
6
4
2

Delta Tco (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

15

Typical AC and DC Characteristic Diagrams

Specifications GAL6002

Vol vs Iol

2.5

2

1.5

1

Vol (V)

0.5

0

0.00 20.00 40.00 60.00 80.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

0.8

Normalized Icc

0.7

-55 -25 0 25 75 100 125

Temperature (deg. C)

Voh vs Ioh

4.5

4.25

4

Voh (V)

3.75

3.5

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.20

1.10

1.00

0.90

Normalized Icc

0.80
0 255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

3

2.5

2

1.5

1

Delta Icc (mA)

0.5

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50
60

Iik (mA)

70
80
90

100

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

16