Page 1
GAL6001
High Performance E2CMOS FPLA
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS
• LOW POWER CMOS
— 90mA Typical Icc
2
CELL TECHNOLOGY
• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL
and FPLA Devices
®
Advanced CMOS Technology
®
Functional Block Diagram
ICLK
INPUT
CLOCK
2
INPUTS
2-11
11
{
ILMC
OUTPUT
ENABLE
RESET
D
E
0
7
BLMC
AND
OR
D
E
Macrocell Names
ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL
14
23
OLMC
OCLK
14
23
IOLMC
OUTPUTS
{
14 - 23
OUTPUT
CLOCK
• APPLICATIONS INCLUDE:
— Sequencers
Pin Names
— State Machine Control
— Multiple PLD Device Integration
Description
- I
I
0
INPUT I/O/Q BIDIRECTIONAL
10
ICLK INPUT CLOCK V
POWER (+5)
CC
OCLK OUTPUT CLOCK GND GROUND
Using a high performance E2CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). T wo clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E
2
CMOS reprogrammable cells, enable 100% AC, DC,
programmability , and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
Pin Configuration
PLCC
NC
I/ICLK
I
I
228
4
5
I
I
I
7
NC
1
GAL6001
I
9
T op View
I
11
I
12 14 16 18
I
I
GND
NC
Vcc
OCLK
I/O/Q
I/O/Q
DIP
1
I/ICLK
I
GND
I
I
GAL
I
6001
6
I
I
I
I
I
I
12
I/O/Q
26
25
I/O/Q
I/O/Q
23
I/O/Q
NC
21
I/O/Q
I/O/Q
19
I/O/Q
I/O/Q
Vcc
24
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OCLK
13
Page 2
GAL6001 Ordering Information
Commercial Grade Specifications
)sn(dpT)zHM(xamF)Am(ccI#gniredrOegakcaP
0372051PL03-B1006LAGPIDcitsalPniP-42
051JL03-B1006LAGCCLPdaeL-82
Part Number Description
Specifications GAL6001
GAL6001B
Device Name
Speed (ns)
PowerL = Low Power
XXXXXXXX XX X X X
_
Grade
Package
Blank = Commercial
P = Plastic DIP
J = PLCC
2
Page 3
Specifications GAL6001
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
The GAL6001 features two configurable input sections. The ILMC
section corresponds to the dedicated input pins (2-11) and the
IOLMC to the I/O pins (14-23). Each input section is configurable
as a block for asynchronous, latched, or registered inputs. Pin 1
(ICLK) is used as an enable input for latched macrocells or as a
clock input for registered macrocells. Configurable input blocks
provide system designers with unparalleled design flexibility . With
the GAL6001, external registers and latches are not necessary .
Both the ILMC and the IOLMC are block configurable. However,
the ILMC can be configured independently of the IOLMC. The three
valid macrocell configurations are shown in the macrocell equivalent
diagrams on the following pages.
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
The outputs of the OR array feed two groups of macrocells. One
group of eight macrocells is buried; its outputs feed back directly
into the AND array rather than to device pins. These cells are called
the Buried Logic Macrocells (BLMC), and are useful for building
state machines. The second group of macrocells consists of 10
cells whose outputs, in addition to feeding back into the AND array, are available at the device pins. Cells in this group are known
as Output Logic Macrocells (OLMC).
The Output and Buried Logic Macrocells are configurable on a
macrocell by macrocell basis. Buried and Output Logic Macrocells
may be set to one of three configurations: combinatorial, D-type
register with sum term (asynchronous) clock, or D/E-type register.
Output macrocells always have I/O capability, with directional control
provided by the 10 output enable (OE) product terms. Additionally,
the polarity of each OLMC output is selected through the “D” XOR.
Polarity selection is available for BLMCs, since both the true and
complemented forms of their outputs are available in the AND array .
Polarity of all “E” sum terms is selected through the “E” XOR.
When the macrocell is configured as a D/E type register, it is clocked
from the common OCLK and the register clock enable input is controlled by the associated “E” sum term. This configuration is useful
for building counters and state-machines with state hold functions.
When the macrocell is configured as a D-type register with a sum
term clock, the register is always enabled and its “E” sum term is
routed directly to the clock input. This permits asynchronous programmable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are reset
to a logic zero. If connected to an output pin, a logic one will occur because of the inverting output buffer .
There are two possible feedback paths from each OLMC. The first
path is directly from the OLMC (this feedback is before the output
buffer and always present). When the OLMC is used as an output, the second feedback path is through the IOLMC. With this dual
feedback arrangement, the OLMC can be permanently buried (the
associated OLMC pin is an input), or dynamically buried with the
use of the output enable product term.
The D/E registers used in this device offer the designer the ultimate
in flexibility and utility. The D/E register architecture can emulate
RS-, JK-, and T-type registers with the same ef ficiency as a dedicated RS-, JK-, or T -register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
3
Page 4
Y
ILMC and IOLMC Configurations
ICLK
LATCH
E
D
Specifications GAL6001
Q
MUX
0 0
INPUT
or I/O
REG.
10
Q
D
ILMC/IOLMC
Generic Logic Block Diagram
ILMC (Input Logic Macrocell)
JEDEC Fuse Numbers
INVALID
0 1
10
1 0
1 1
LATCH ISYN
IOLMC (I/O Logic Macrocell)
JEDEC Fuse Numbers
AND
ARRA
ISYN LATCH
8218 8219
ISYN LATCH
8220 8221
4
Page 5
OLMC and BLMC Configurations
RESET
Specifications GAL6001
OE
PRODUCT
TERM
AND
ARRAY
IOLMC
OLMC ONLY
XORD(i)
D
Vcc
XORE(i)
E
CKS(i)
OCLK
OLMC (Output Logic Macrocell)
JEDEC Fuse Numbers
MUX
1
0
OSYN(i)
MUX
0
R
D
Q
E
1
MUX
0
1
OLMC/BLMC
Generic Logic Block Diagram
I/O
OLMC ONLY
BLMC (Buried Logic Macrocell)
JEDEC Fuse Numbers
OLMC OCLK OSYN XORE XORD
0 8178 8179 8180 8181
1 8182 8183 8184 8185
2 8186 8187 8188 8189
3 8190 8191 8192 8193
4 8194 8195 8196 8197
5 8198 8199 8200 8201
6 8202 8203 8204 8205
7 8206 8207 8208 8209
8 8210 8211 8212 8213
9 8214 8215 8216 8217
BLMC OCLK OSYN XORE
7 8175 8176 8177
6 8172 8173 8174
5 8169 8170 8171
4 8166 8167 8168
3 8163 8164 8165
2 8160 8161 8162
1 8157 8158 8159
0 8154 8155 8156
5
Page 6
GAL6001 Logic Diagram
Specifications GAL6001
IOLMC 9
LTCH.
REG.
MUX
OLMC 2
OLMC 3
IOLMC 8
IOLMC 7
IOLMC 6
IOLMC 5
IOLMC 4
IOLMC 3
IOLMC 2
OLMC 0
IOLMC 1
IOLMC 0
OLMC 4
OLMC 1
OLMC 8
OLMC 5
OLMC 6
OLMC 7
OLMC 9
MUX
BLMC 0
BLMC 1
BLMC 7
BLMC 6
BLMC 5
BLMC 4
BLMC 2
BLMC 3
ICLK
LTCH. REG.
3(4)
4(5)
5(6)
6(7)
7(9)
8(10)
9(11)
10(12)
11(13)
1(2)
2(3)
6
Page 7
GAL6001 Logic Diagram (Continued)
Specifications GAL6001
23(27)
1
0
Q
R
D
0
OLMC 9
XORD
E
1
XORE
1
01
22(26)
0
Q
R
D
0
OLMC 8
XORD
21(25)
1
0
Q
R
01
E
D
1
XORE
0
OLMC 7
XORD
20(24)
1
0
Q
R
01
E
D
1
XORE
0
OLMC 6
XORD
19(23)
1
0
Q
R
01
E
1
D
0
OLMC 5
XORE
XORD
18(21)
0
1
Q
R
01
E
D
1
XORE
0
OLMC 4
XORD
17(20)
0
1
Q
R
01
E
1
D
0
OLMC 3
XORE
XORD
16(19)
1
0
Q
R
01
E
D
1
XORE
0
OLMC 2
XORD
15(18)
1
0
Q
R
01
E
1
D
0
OLMC 1
XORE
XORD
E
1
XORE
1
01
14(17)
0
Q
R
D
E
0
OLMC 0
XORD
13(16)
01
1
XORE
The number of Differential Product Terms that may
OCLK
switch is limited to a maximum of 15. Refer to the
RESET
Differential Product Term Switching Applications section of this data sheet for a full explanation.
XORE
BLMC 7
0
1
D
E
0
R
1
Q
1
0
XORE
BLMC 6
0
1
D
E
0
R
1
Q
1
0
XORE
BLMC 5
0
1
D
E
0
R
1
Q
1
0
XORE
BLMC 4
0
1
D
E
0
R
1
Q
1
0
XORE
BLMC 3
0
1
D
E
01
R
Q
0
1
XORE
BLMC 2
0
1
D
E
01
R
Q
0
1
XORE
BLMC 1
0
1
01
D
E
R
Q
1
0
XORE
BLMC 0
0
1
01
D
E
R
Q
1
0
7
Page 8
Specifications GAL6001
Absolute Maximum Ratings
(1)
Supply voltage VCC...................................... –0.5 to +7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ................................–65 to 150°C
Recommended Operating Conditions
Commercial Devices:
Ambient T emperature (TA) ...............................0 to 75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................–55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——-10 µA
IIH Input or I/O High Leakage Current 3.5VIH ≤ VIN ≤ VCC ——10 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V
VOH Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 ——V
IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA
1
IOS
Output Short Circuit Current VCC = 5V VOUT = 0.5V –30 —–130 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -30 — 90 150 mA
Supply Current f
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
2) T ypical values are at Vcc = 5V and TA = 25 °C
toggle = 15MHz Outputs Open
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
C
I
C
I/O
*Characterized but not 100% tested.
Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V
I/O Capacitance 10 pF VCC = 5.0V , V
= 2.0V
I/O
8
Page 9
Specifications GAL6001
AC Switching Characteristics
Over Recommended Operating Conditions
COM
TEST
COND1.
DESCRIPTION
tpd1 A Combinatorial Input to Combinatorial Output — 30 ns
tpd2 A Feedback or I/O to Combinatorial Output — 30 ns
tpd3 A Transparent Latch Input to Combinatorial Output — 35 ns
tco1 A Input Latch ICLK to Combinatorial Output Delay — 35 ns
tco2 A Input Reg. ICLK to Combinatorial Output Delay — 35 ns
tco3 A Output D/E Reg. OCLK to Output Delay — 12 ns
tco4 A Output D Reg. Sum Term CLK to Output Delay — 35 ns
tsu1 — Setup T ime, Input before Input Latch ICLK 2.5 — ns
tsu2 — Setup T ime, Input before Input Reg. ICLK 2.5 — ns
tsu3 — Setup T ime, Input or Feedback before D/E Reg. OCLK 25 — ns
-30
MIN. MAX.
UNITSPARAMETER
tsu4 — Setup T ime, Input or Feedback before D Reg. Sum Term CLK 7.5 — ns
tsu5 — Setup T ime, Input Reg. ICLK before D/E Reg. OCLK 30 — ns
tsu6 — Setup T ime, Input Reg. ICLK before D Reg. Sum Term CLK 15 — ns
th1 — Hold Time, Input after Input Latch ICLK 5 — ns
th2 — Hold Time, Input after Input Reg. ICLK 5 — ns
th3 — Hold Time, Input or Feedback after D/E Reg. OCLK 0 — ns
th4 — Hold Time, Input or Feedback after D Reg. Sum Term CLK 10 — ns
fmax — Maximum Clock Frequency, OCLK 27 — MHz
twh1 — ICLK or OCLK Pulse Duration, High 10 — ns
twh2 — Sum Term CLK Pulse Duration, High 15 — ns
twl1 — ICLK or OCLK Pulse Duration, Low 10 — ns
twl2 — Sum T erm CLK Pulse Duration, Low 15 — ns
tarw — Reset Pulse Duration 15 — ns
ten B Input or I/O to Output Enabled — 25 ns
tdis C Input or I/O to Output Disabled — 25 ns
tar A Input or I/O to Asynchronous Reg. Reset — 35 ns
tarr1 — Asynchronous Reset to OCLK Recovery Time 20 — ns
tarr2 — Asynchronous Reset to Sum Term CLK Recovery Time 10 — ns
1) Refer to Switching T est Conditions section.
9
Page 10
Switching Waveforms
Specifications GAL6001
INPUT or
I/O FEEDBACK
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
ICLK (LATCH)
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
Sum Term CLK
REGISTERED
OUTPUT
t
Combinatorial Output
VALID INPUT
t
t
su1
pd3
t
h1
Latched Input
VALID INPUT
su4
t
t
VALID INPUT
pd1,2
t
h4
t
co4
co1
INPUT or
I/O FEEDBACK
ICLK (REGISTER)
COMBINATORIAL
OUTPUT
OCLK
Sum Term CLK
INPUT or
I/O FEEDBACK
OCLK
REGISTERED
OUTPUT
VALID INPUT
tsu2
Registered Input
VALID INPUT
su3
t
1/ fmax
th2
co2
t
tsu6
t
co3
t
tsu5
h3
INPUT or
I/O FEEDBACK
OUTPUT
Input or I/O to Output Enable/Disable
ICLK or
OCLK
Sum Term CLK
Registered Output (Sum T erm CLK)
t
t
wh1
wh2
t
dis
t
en
wl1
t
wl2
t
Clock Width
INPUT or
I/O FEEDBACK
DRIVING AR
REGISTERED
OUTPUT
Sum Term CLK
OCLK
Registered Output (OCLK)
arw
t
t
ar
Asynchronous Reset
arr2
t
t
arr1
10
Page 11
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
fmax Descriptions
CLK
LOGIC
ARRAY
t
su
REGISTER
t
co
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
Specifications GAL6001
CLK
LOGIC
ARRAY
REGISTER
t
cf
t
pd
CLK
LOGIC
ARRAY
REGISTER
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
Test Condition R
A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 300Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 300Ω 390Ω 5pF
1 R2 CL
11
Page 12
Specifications GAL6001
Array Description
The GAL6001 contains two E2 reprogrammable arrays. The first
is an AND array and the second is an OR array. These arrays are
described in detail below.
AND ARRA Y
The AND array is organized as 78 inputs by 75 product term outputs. The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC
feedbacks, and ICLK comprise the 39 inputs to this array (each
available in true and complement forms). 64 product terms serve
as inputs to the OR array . The RESET product term generates the
RESET signal described in the Output and Buried Logic Macrocells
section. There are 10 output enable product terms which allow
device pins 14-23 to be bi-directional or tri-state.
OR ARRA Y
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the OR
array. Of the 36 sum term outputs, 18 are data (“D”) terms and 18
are enable/clock (“E”) terms. These terms feed into the 10 OLMCs
and 8 BLMCs, one “D” term and one “E” term to each.
The programmable OR array offers unparalleled versatility in product term usage. This programmability allows from 1 to 64 product
terms to be connected to a single sum term. A programmable OR
array is more flexible than a fixed, shared, or variable product term
architecture.
Electronic Signature
An electronic signature (ES) is provided in every GAL6001 device.
It contains 72 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
NOTE: The ES is included in checksum calculations. Changing the
ES will alter the checksum.
Security Cell
A security cell is provided in every GAL6001 device as a deterrent
to unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the AND and OR arrays.
This cell can be erased only during a bulk erase cycle, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user ,
regardless of the state of this control cell.
Bulk Erase
Before writing a new pattern into a previously programmed part,
the old pattern must first be erased. This erasure is done automatically by the programming hardware as part of the programming
cycle and takes only 50 milliseconds.
Register Preload
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because in system operation, certain events
may occur that cause the logic to assume an illegal state: powerup, brown out, line voltage glitches, etc. To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (i.e., illegal) into the
registers. Then the machine can be sequenced and the outputs
tested for correct next state generation.
All of the registers in the GAL6001 can be preloaded, including the
ILMC, IOLMC, OLMC, and BLMC registers. In addition, the contents of the state and output registers can be examined in a special
diagnostics mode. Programming hardware takes care of all preload
timing and voltage requirements.
Latch-Up Protection
GAL6001 devices are designed with an on-board charge pump to
negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any possibility of SCR induced latching.
Input Buffers
GAL devices are designed with TTL level compatible input buffers.
These buffers, with their characteristically high impedance, load
driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic.
GAL6001 devices do not possess active pull-ups within their input
structures. As a result, Lattice Semiconductor recommends that
all unused inputs and tri-stated I/O pins be connected to another
active input, Vcc, or GND. Doing this will tend to improve noise
immunity and reduce Icc for the device.
12
Page 13
Power-Up Reset
Specifications GAL6001
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Circuitry within the GAL6001 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
Vcc (min.)
twl
tpr
Internal Register
Reset to Logic "0"
Device P in
Reset to Logic "1"
of system power-up, some conditions must be met to provide a
valid power-up reset of the GAL6001. First, the VCC rise must
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse
width requirements.
Differential Product Term Switching (DPTS) Applications
tsu
The number of Differential Product Term Switching (DPTS ) for
a given design is calculated by subtracting the total number of
product terms that are switching from a Logical HI to a Logical LO
from those switching from a Logical LO to a Logical HI within a
5ns period. After subtracting take the absolute value.
DPTS =
(P-Terms)
- (P-Terms)
LH
HL
DPTS restricts the number of product terms that can be switched
simultaneously - there is no limit on the number of product terms
that can be used.
A software utility is available from Lattice Semiconductor
Applications Engineering that will perform this calculation on any
GAL6001 JEDEC file. This program, DPTS, and additional
information may be obtained from your local Lattice
Semiconductor representative or by contacting Lattice
Semiconductor's Applications Engineering Dept. (Tel: 503-6810118 or 1-888-ISP-PLDS; FAX: 681-3037).
13
Page 14
Typical AC and DC Characteristic Diagrams
Specifications GAL6001
Normalized Tpd vs Vcc
1.2
1.1
1
0.9
Normalized Tpd
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Normalized Tpd vs Temp
1.3
1.2
1.1
1
0.9
Normalized Tpd
0.8
0.7
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Temperature (deg. C)
PT H->L
PT L->H
Normalized Tco vs Vcc
1.2
1.1
1
0.9
Normalized Tco
0.8
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Normalized Tco vs Temp
1.3
1.2
1.1
1
0.9
Normalized Tco
0.8
0.7
-55 -25 0 25 50 75 100 125
RISE
FALL
Temperature (deg. C)
RISE
FALL
Normalized Tsu vs Vcc
1.2
1.1
1
0.9
Normalized Tsu
0.8
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Supply Voltage (V)
Normalized Tsu vs Temp
1.4
1.3
1.2
1.1
1
0.9
Normalized Tsu
0.8
0.7
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
0
-0.5
-1
-1.5
Delta Tpd (ns)
-2
12345678910
Number of Outputs Switching
Delta Tpd vs Output Loading
12
10
8
6
4
2
Delta Tpd (ns)
0
-2
0 50 100 150 200 250 300
RISE
FALL
Output Loading (pF)
RISE
FALL
Delta Tco vs # of Outputs
Switching
0
-0.5
-1
-1.5
Delta Tco (ns)
-2
12345678910
Number of Outputs Switching
Delta Tco vs Output Loading
12
10
8
6
4
2
Delta Tco (ns)
0
-2
0 50 100 150 200 250 300
RISE
FALL
Output Loading (pF)
RISE
FALL
14
Page 15
Typical AC and DC Characteristic Diagrams
Specifications GAL6001
Vol vs Iol
2.5
2
1.5
1
Vol (V)
0.5
0
0.00 20.00 40.00 60.00 80.00
Iol (mA)
Normalized Icc vs Vcc
1.20
1.10
1.00
0.90
Normalized Icc
0.80
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Voh vs Ioh
5
4
3
2
Voh (V)
1
0
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Ioh(mA)
Normalized Icc vs Temp
1.2
1.1
1
0.9
0.8
Normalized Icc
0.7
-55 -25 0 25 75 100 125
Temperature (deg. C)
Voh vs Ioh
4.5
4.25
4
Voh (V)
3.75
3.5
0.00 1.00 2.00 3.00 4.00
Ioh(mA)
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
Normalized Icc
0.80
0 25 50 75 100
Frequency (MHz)
Delta Icc vs Vin (1 input)
3
2.5
2
1.5
1
Delta Icc (mA)
0.5
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
Input Clamp (Vik)
0
10
20
30
40
50
60
Iik (mA)
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
Vik (V)
15
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