Datasheet GAL22V10D-25LPN Specification

Specifications GAL22V10

1

12

13

24

I/CLK

I
I
I
I
I

I
I

I
I
I

GND

Vcc
I/O/Q

I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I

6

18

GAL22V10

High Performance E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and UVCMOS 22V10 Devices

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA T ypical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device

2

CELL TECHNOLOGY

•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

ESCRIPTION

Description

Functional Block Diagram

I/CLK

I

I

I

I

I

I

(132X44)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

Pin Configuration

PRESET

RESET

8

10

12

14

16

16

14

12

10

8

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
floating gate technology to provide the highest performance avail­able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E

2

technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently .

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com­patible with standard bipolar and CMOS 22V10 devices.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat­tice Semiconductor delivers 100% field programmability and func­tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

22v10_06

2

)

I
I
I

NC

I
I
I

11

PLCC

NC

NC

I/O/Q

I/O/Q

Vcc

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

18

161412

I

I/O/Q

I/O/Q

I/CLK

I

I

228

426

5

7

GAL22V10

9

Top V iew

I

I

GND

1

DIP

GAL

22V10

Specifications GAL22V10

GAL22V10 Ordering Information

Commercial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

45.25.3041JL4-D01V22LAG CCLPdaeL-82
534 041JL5-D01V22LAG CCLPdaeL-82

051JL5-C01V22LAG CCLPdaeL-82

5.75.45.4041PL7-D01V22LAG PIDcitsalPniP-42

55.4041PL7-C01V22LAG PIDcitsalPniP-42

5.45.4041JL7-C01V22LAGroJL7-D01V22LAG CCLPdaeL-82

5.65041PL7-B01V22LAG PIDcitsalPniP-42
041JL7-B01V22LAG CCLPdaeL-82

017755PQ01-D01V22LAG PIDcitsalPniP-42

55JQ01-D01V22LAG CCLPdaeL-82

031PL01-B01V22LAGroPL01-C01V22LAG,PL01-D01V22LAG PIDcitsalPniP-42
031JL01-B01V22LAGroJL01-C01V22LAG,JL01-D01V22LAG CCLPdaeL-82

5101855PQ51-B01V22LAGroPQ51-D01V22LAG PIDcitsalPniP-42

55JQ51-B01V22LAGroJQ51-D01V22LAG CCLPdaeL-82

031PL51-B01V22LAGroPL51-D01V22LAG PIDcitsalPniP-42
031JL51-B01V22LAGroJL51-D01V22LAG CCLPdaeL-82

52515155PQ52-B01V22LAGroPQ52-D01V22LAG PIDcitsalPniP-42

55JQ52-B01V22LAGroJQ52-D01V22LAG CCLPdaeL-82
09PL52-B01V22LAGroPL52-D01V22LAG piDcitsalPniP-42
09JL52-B01V22LAGroJL52-D01V22LAG CCLPniP-82

Industrial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.755.4061

5.45.4061

0177 061

061

51018 051roIPL51-D01V22LAGIPL51-B01V22LAGPIDcitsalPniP-42

051roIJL51-D01V22LAGIJL51-B01V22LAGCCLPdaeL-82

024101051roIPL02-D01V22LAGIPL02-B01V22LAGPIDcitsalPniP-42

051roIJL02-D01V22LAGIJL02-B01V22LAGCCLPdaeL-82

525151051roIPL52-D01V22LAGIPL52-B01V22LAGPIDcitsalPniP-42

051roIJL52-D01V22LAGIJL52-B01V22LAGCCLPdaeL-82

01V22LAGDIPL7-roIPL7-C01V22LAG
01V22LAGDIJL7-roIJL7-C01V22LAG
01V22LAGDIPL01-roIPL01-C01V22LAG
01V22LAGDIJL01-roIJL01-C01V22LAG

PIDcitsalPniP-42

CCLPdaeL-82

PIDcitsalPniP-42

CCLPdaeL-82

Part Number Description

GAL22V10D
GAL22V10C
GAL22V10B

Q = Quarter Power

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

2

Grade

Package

Blank = Commercial
I = Industrial

P = Plastic DIP
J = PLCC

Output Logic Macrocell (OLMC)

Specifications GAL22V10

The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and

21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an addi­tional product-term dedicated to output enable control.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.

AR

D

The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod­uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.

NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.

Q

QCLK

4 TO 1

MUX

SP

2 TO 1

MUX

GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

Output Logic Macrocell Configurations

Each of the Macrocells of the GAL22V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the following page.

REGISTERED

In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in­dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg­istered is an output only , and cannot be used for dynamic
I/O, as can the combinatorial pins.

COMBINA TORIAL I/O

In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out­put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.

3

Registered Mode

Specifications GAL22V10

CLK

S0 = 0
S1 = 0

Combinatorial Mode

AR

D

SP

Q

Q

S0 = 1
S1 = 0

CLK

AR

D

ACTIVE HIGHACTIVE LOW

Q

Q

SP

S0 = 0
S1 = 1

ACTIVE HIGHACTIVE LOW

S0 = 1
S1 = 1

4

GAL22V10 Logic Diagram / JEDEC Fuse Map

DIP (PLCC) Package Pinouts

1 (2)

2 (3)

3 (4)

4 (5)

5 (6)

6 (7)

7 (9)

8 (10)

9 (11)

10 (12)
11 (13) 13 (16)

0 4 8 1216202428323640

0000
0044

.
.
.

0396

0440

.
.
.
.

0880

0924

.
.
.
.
.

1452

1496

.
.
.
.
.
.

2112

2156

.
.
.
.
.
.
.

2860

2904

.
.
.
.
.
.
.

3608

3652

.
.
.
.
.
.

4268

4312

.
.
.
.
.

4840

4884

.
.
.
.

5324

5368

.
.
.

5720

5764

Specifications GAL22V10

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

8

10

12

14

16

16

14

12

10

OLMC

S0

5808

S1

5809

OLMC

S0

5810

S1

5811

OLMC

S0

5812

S1

5813

OLMC

S0

5814

S1

5815

OLMC

S0

5816

S1

5817

OLMC

S0

5818

S1

5819

OLMC

S0

5820

S1

5821

OLMC

S0

5822

S1

5823

OLMC

S0

5824

S1

5825

8

OLMC

S0

5826

S1

5827

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

23 (27)

22 (26)

21 (25)

20 (24)

19 (23)

18 (21)

17 (20)

16 (19)

15 (18)

14 (17)

Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3

Electronic Signature 5828, 5829 ... ... 5890, 5891

M

L

S

S

B

B

5

Specifications GAL22V10D

Specifications GAL22V10

Absolute Maximum Ratings

Supply voltage VCC....................................... -0.5 to +7V

Input voltage applied ...........................-2.5 to VCC +1.0V

Off-state output voltage applied...........-2.5 to V

Storage Temperature..................................-65 to 150°C

Ambient T emperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

1

Recommended Operating Conditions

Commercial Devices:

) .............................0 to +75°C

A

+1.0V

CC

Ambient T emperature (T
Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

Ambient T emperature (T

) ............................-40 to 85°C

A

Supply voltage (VCC)

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL P ARAMETER CONDITION MIN. TYP.3MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High V oltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low V oltage IOL = MAX. Vin = VIL or VIH ——0.4 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —–130 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA

Supply Current f

toggle = 15MHz Outputs Open L-10 — 90 130 mA

L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA

INDUSTRIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA

Supply Current f

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA

6

AC Switching Characteristics

Specifications GAL22V10D

Specifications GAL22V10

Over Recommended Operating Conditions

PARAM

TEST

COND.

COM

1

DESCRIPTION

-4

MIN. MAX.

-5

MIN. MAX.

COM/INDCOM

-7

MIN. MAX.

tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns
tco A Clock to Output Delay 1 3.5 1 4 1 4.5 ns

2

tcf

— Clock to Feedback Delay — 2.5 — 3 — 3ns

tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 3 — 4.5 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — ns

A Maximum Clock Frequency with 167 — 142.8 — 111 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 200 — 166 — 133 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 200 — 166 — MHz

No Feedback

twh — Clock Pulse Duration, High 2 — 2.5 — 3 — ns

twl — Clock Pulse Duration, Low 2 — 2.5 — 3 — ns

ten B Input or I/O to Output Enabled 1 5 1 6 1 7.5 ns

tdis C Input or I/O to Output Disabled 1 5 1 5.5 1 7.5 ns

UNITS

tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 5.5 1 9 ns

tarw — Asynch. Reset Pulse Duration 4.5 — 4.5 — 7 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 4 — 5 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 3 — 4 — 5 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these

parameters.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

7

Specifications GAL22V10

Specifications GAL22V10D

AC Switching Characteristics

Over Recommended Operating Conditions

COM / IND IND COM / INDCOM / IND

PARAM.

TEST

COND.

DESCRIPTION

1

-10

MIN. MAX.

-15

MIN. MAX.

-20

MIN. MAX.

-25

MIN. MAX.

tpd A Input or I/O to Comb. Output 1 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 1 7 2 8 2 10 2 15 ns

2

tcf

— Clock to Feedback Delay — 2.5 — 2.5 — 8 — 13 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 6 — 10 — 12 — 15 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 83.3 — 55.5 — 41.6 — 33.3 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 1 10 — 80 — 45.4 — 35.7 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 125 — 83.3 — 50 — 38.5 — MHz

No Feedback

UNITS

twh — Clock Pulse Duration, High 4 — 6 — 10 — 13 — ns

twl — Clock Pulse Duration, Low 4 — 6 — 10 — 13 — ns

ten B Input or I/O to Output Enabled 1 10 3 15 3 20 3 25 ns

tdis C Input or I/O to Output Disabled 1 9 3 15 3 20 3 25 ns

tar A Input or I/O to Asynch. Reset of Reg. 1 13 3 20 3 25 3 25 ns

tarw — Asynch. Reset Pulse Duration 8 — 15 — 20 — 25 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 10 — 20 — 25 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 8 — 10 — 14 — 15 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

8

Specifications GAL22V10

Specifications GAL22V10C

Absolute Maximum Ratings

Supply voltage VCC....................................... -0.5 to +7V

Input voltage applied ...........................-2.5 to VCC +1.0V

Off-state output voltage applied ..........-2.5 to VCC +1.0V

Storage Temperature .................................-65 to 150°C

Ambient T emperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

1

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (T

) .............................0 to +75°C

A

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

Ambient T emperature (T
Supply voltage (V

CC

) ............................-40 to 85°C

A

)

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

3

SYMBOL PARAMETER CONDITION MIN. TYP.

MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low V oltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —–130 mA

COMMERCIAL

ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-5 — 90 150 mA

ftoggle = 15MHz Outputs Open L-7 — 90 140 mA

L-10 — 90 130 mA

INDUSTRIAL

ICC Operating Power Supply Current VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA

toggle = 15MHz Outputs Open

f

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 5V and TA = 25 °C

9

AC Switching Characteristics

Specifications GAL22V10

Specifications GAL22V10C

Over Recommended Operating Conditions

PARAM

TEST

COND.

DESCRIPTION

1

-5

MIN. MAX.

COM/INDCOM

-7 (PLCC)

MIN. MAX.

-7 (PDIP)

MIN. MAX.

COMCOM/IND

-10

MIN. MAX.

IND

-10

MIN. MAX.

tpd A Input or I/O to Combinatorial Output 1 5 1 7.5 1 7.5 3 10 1 10 ns
tco A Clock to Output Delay 1 4 1 4.5 1 4.5 2 7 1 7 ns

2

tcf

— Clock to Feedback Delay — 3 — 3 — 3 — 2.5 — 2.5 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 3 — 4.5 — 5 — 7 — 7 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 142.8 — 111 — 105 — 71.4 — 71.4 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 166 — 133 — 125 — 105 — 105 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 200 — 166 — 142.8 — 105 — 105 — MHz

No Feedback

twh — Clock Pulse Duration, High 2.5 — 3 — 3.5 — 4 — 4 — ns

twl — Clock Pulse Duration, Low 2.5 — 3 — 3.5 — 4 — 4 — ns

ten B Input or I/O to Output Enabled 1 6 1 7.5 1 7.5 3 10 1 10 ns

tdis C Input or I/O to Output Disabled 1 6 1 7.5 1 7.5 3 9 1 9 ns

UNITS

tar A Input or I/O to Asynch. Reset of Reg. 1 5.5 1 9 1 9 3 13 1 13 ns

tarw — Asynch. Reset Pulse Duration 5.5 — 7 — 7 — 8 — 8 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 4 — 5 — 5 — 8 — 8 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 4 — 5 — 5 — 10 — 10 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these

parameters.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

10

Specifications GAL22V10

Specifications GAL22V10B

Absolute Maximum Ratings

Supply voltage VCC....................................... -0.5 to +7V

Input voltage applied ...........................-2.5 to VCC +1.0V

Off-state output voltage applied ..........-2.5 to V

Storage Temperature .................................-65 to 150°C

Ambient T emperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

1

Recommended Operating Conditions

Commercial Devices:

+1.0V

CC

Ambient T emperature (T
Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

) .............................0 to +75°C

A

Industrial Devices:

Ambient T emperature (T
Supply voltage (V

CC

) ............................-40 to 85°C

A

)

with Respect to Ground ..................... +4.50 to +5.50V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low V oltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —–130 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L-7 — 90 140 mA

Supply Current f

toggle = 15MHz Outputs Open L-10/-15 — 90 130 mA

L-25 — 75 90 mA
Q-15/-25 — 45 55 mA

INDUSTRIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L-15/-20/-25 — 90 150 mA

Supply Current f

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

11

Specifications GAL22V10

Specifications GAL22V10B

AC Switching Characteristics

AC SWITCHING CHARACTERISTICS

Over Recommended Operating Conditions

COM / IND

-25

MIN. MAX.

PARAM.

TEST

COND.

DESCRIPTION

1

COM COM COM / IND IND

-7

MIN. MAX.

-10

MIN. MAX.

-15

MIN. MAX.

-20

MIN. MAX.

tpd A Input or I/O to Comb. Output 3 7.5 3 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 2 5 2 7 2 8 2 10 2 15 ns

2

tcf

— Clock to Feedback Delay — 2.5 — 2.5 — 2.5 — 8 — 13 ns

UNITS

tsu
tsu

— Setup Time, Input or Fdbk before Clk↑ 6.5 — 7 — 10 — 14 — 15 — ns

1

— Setup Time, SP before Clock↑ 10 — 10 — 10 — 14 — 15 — ns

2

th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 87 — 71.4 — 55.5 — 41.6 — 33.3 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 1 11 — 105 — 80 — 45.4 — 35.7 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 1 11 — 105 — 83.3 — 50 — 38.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 4 — 4 — 6 — 10 — 13 — ns

twl — Clock Pulse Duration, Low 4 — 4 — 6 — 10 — 13 — ns

ten B Input or I/O to Output Enabled 3 8 3 10 3 15 3 20 3 25 ns

tdis C Input or I/O to Output Disabled 3 8 3 9 3 15 3 20 3 25 ns

tar A Input or I/O to Asynch. Reset of Reg. 3 13 3 13 3 20 3 25 3 25 ns

tarw — Asynch. Reset Pulse Duration 8 — 8 — 15 — 20 — 25 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 20 — 25 — ns

tspr — Synch. Preset to Clk↑ Recovery Time 10 — 10 — 10 — 14 — 15 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

12

= 2.0V

I/O

INPUT or
I/O FEEDBACK

REGISTERED
OUTPUT

CLK

VALID INPUT

t

su

t

co

t

h

(external fdbk)

1/ fmax

Switching Waveforms

Specifications GAL22V10

INPUT or
I/O FEEDBACK

COMBINATORIAL
OUTPUT

INPUT or
I/O FEEDBACK

OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

Combinatorial Output

t

dis

t

pd

Registered Output

t

en

CLK

1/ fmax (internal fdbk)

t

cf t

REGISTERED
FEEDBACK

su

CLK

INPUT or
I/O FEEDBACK
DRIVING SP

CLK

REGISTERED
OUTPUT

Clock Width

t

wh

1/

f

(w/o fdbk)

t

su

max

fmax with Feedback

t

wl

INPUT or
I/O FEEDBACK
DRIVING AR

t

h

t

spr

CLK

t

co

REGISTERED
OUTPUT

Asynchronous ResetSynchronous Preset

t

arw

t

ar

t

arr

13

fmax Descriptions

Specifications GAL22V10

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi­natorial output is equal to tcf + tpd.

14

Switching Test Conditions

Specifications GAL22V10

Input Pulse Levels GND to 3.0V
Input Rise and D-4/-5/-7, C-5 1.5ns 10% – 90%
Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%

B & C-7/-10

B-15/-20/-25 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (except D-4) (see figure below)

T est Condition R

1 R2 CL

A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF

Active Low 300Ω 390Ω 50pF

C Active High ∞ 390Ω 5pF

Active Low 300Ω 390Ω 5pF

+5V

GAL22V10D-4 Output Load Conditions (see figure below)

T est Condition R

1 CL

A50Ω 50pF
B Z to Active High at 1.9V 50Ω 50pF

Z to Active Low at 1.0V 50Ω 50pF

C Active High to Z at 1.9V 50Ω 50pF

Active Low to Z at 1.0V 50Ω 50pF

+1.45V

FROM OUTPUT (O/Q)
UNDER TEST

TEST POINT

Z

= 50Ω, CL*

0

R

1

R

1

FROM OUTPUT (O/Q)
UNDER TEST

R

2

*C

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

L

C *

L

TEST POINT

15

Specifications GAL22V10

Electronic Signature

An electronic signature (ES) is provided in every GAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se­curity cell.

The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com­piling a set of logic equations. In addition, many device program­mers have two separate selections for the device, typically a
GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig­nature) or GAL22V10-ES. This allows users to maintain compat­ibility with existing 22V10 designs, while still having the option to
use the GAL device's extra feature.

The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro­grammer.

Security Cell

A security cell is provided in every GAL22V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail­able to the user, regardless of the state of this control cell.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi­tions.

The GAL22V10 device includes circuitry that allows each regis­tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically .

Input Buffers

GAL22V10 devices are designed with TTL level compatible in­put buffers. These buffers have a characteristically high imped­ance, and present a much lighter load to the driving logic than bi­polar TTL devices.

The input and I/O pins also have built-in active pull-ups. As a re­sult, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat­ics on the following page.)

T ypical Input Current

Latch-Up Protection

GAL22V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos­sibility of SCR induced latching.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers (see the the GAL Development Tools section). Com­plete programming of the device takes only a few seconds. Eras­ing of the device is transparent to the user, and is done automati­cally as part of the programming cycle.

16

0

-20

-40

Input Current (uA)

-60
0

1.0 2.0 3.0 4.0 5.0

Input Voltage (Volts)

Power-Up Reset

Specifications GAL22V10

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

Vcc (min.)

Circuitry within the GAL22V10 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q out­puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-

t

su

t

wl

pr

t

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Device Pin
Reset to Logic "0"

chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor­mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.

Input/Output Equivalent Schematics

PIN

Vcc

(Vref Typical = 3.2V)

ESD
Protection
Circuit

PIN

ESD
Protection
Circuit

Active Pull-up
Circuit

Vcc

Vref

Vcc

T ypical Input T ypical Output

Data
Output

Feedback

Tri-State
Control

Active Pull-up
Circuit

Vcc

Feedback
(To Input Buffer)

PIN

(Vref Typical = 3.2V)

Vref

PIN

17

Specifications GAL22V10

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.1

1.05

1

0.95

Normalized TpdNormalized Tpd

0.9

RISE
FALL

Normalized TcoNormalized Tco

5.55.2554.754.5

Normalized Tco vs Vcc

1.1

1.05

1

0.95

0.9

RISE
FALL

1.05

0.95

Normalized TNormalized T su

5.55.2554.754.5 5.55.2554.754.5

Normalized Tsu vs Vcc

1.1

1

0.9

RISE
FALL

Supply Voltage (V)Supply Voltage (V)Supply Voltage (V)

Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp

1.3

1.2

1.1

0.9

0.8

RISE
FALL

1

1251007550250-25-55

1.2

RISE

1.1

1

0.9

FALL

1251007550250-25-55

1.3

1.2

1.1

1

0.9

0.8

RISE
FALL

1251007550250-25-55

Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)

Delta Tpd vs # of Outputs

0

-0.1

-0.2

Delta Tpd (ns)

-0.3
12345678910

Switching

Number of Outputs Switching

Delta Tpd vs Output Loading

12

RISE
FALL

Delta Tpd (ns)

8

4

0

-4

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

0

-0.1

-0.2

Delta Tco (ns)Delta Tco (ns)

-0.3

-0.4
12345678910

Switching

RISE
FALL

Number of Outputs Switching

Delta Tco vs Output Loading

12

8

4

0

300250200150100500

-4

RISE
FALL

300250200150100500

Output Loading (pF)

18

Specifications GAL22V10

GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams

Vol vs Iol

0.6

0.4

Vol (V)

0.2

0

0 5 10 15 20 25 30 35 40

Iol (mA)

Normalized Icc vs Vcc

1.2

1.1

1

0.9

Normalized Icc

0.8

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Voh vs Ioh

4

3

2

Voh (V)

1

0

0 5 10 15 20 25 30 35 40 45 50 55 60

Ioh(mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

-55-25 0 255088100125

Temperature (deg. C)

Voh vs Ioh

3.95

3.85

3.75

3.65

3.55

Voh (V)

3.45

3.35

3.25

3.15

0.00 1.00 2.00 3.00 4.00 5.00

Ioh(mA)

Normalized Icc vs Freq

1.2

1.15

1.1

1.05

Normalized Icc

1

0.95
1 15255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

6

5

4

3

2

Delta Icc (mA)

1

0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin (V)

Iik (mA)

Input Clamp (Vik)

0

20

40

60

80

100

-3

-2.5 -2 -1.5 -1 -0.5 1

Vik (V)

19

Specifications GAL22V10

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.1

1.05

1

0.95

Normalized Tpd

0.9

4.5 4.75 5 5.25 5.5

RISE
FALL

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

Normalized Tpd

0.9

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Normalized Tco vs Vcc

1.1

RISE

1.05

1

FALL

Normalized Tco

0.95

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Normalized Tco vs Temp

1.2

1.1

1

Normalized Tco

0.9

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.5 4.75 5 5.25 5.5

RISE
FALL

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.2

1.1

1

Normalized Tsu

0.9

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Delta Tpd vs # of Outputs

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

Delta Tpd (ns)

-0.8

-0.9

-1

-1.1
12345678910

Switching

Number of Outputs Switching

Delta Tpd vs Output Loading

12

8

4

Delta Tpd (ns)

0

-4

RISE
FALL

0 50 100 150 200 250 300

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

Delta Tco (ns)

-0.8

-0.9

-1

-1.1
12345678910

Switching

Number of Outputs Switching

Delta Tco vs Output Loading

12

8

4

Delta Tco (ns)

0

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

20

Specifications GAL22V10

GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams

Vol vs Iol

0.5

0.4

0.3

0.2

Vol (V)

0.1

0

0 5 10 15 20 25 30

Iol (mA)

Normalized Icc vs Vcc

1.15

1.1

1.05

1

0.95

Normalized Icc

0.9

0.85

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Voh vs Ioh

4

3

2

Voh (V)

1

0

0 5 10 15 20 25 30 35 40

Ioh (mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

-55 0 25 100

Temperature (deg. C)

Voh vs Ioh

3.8

3.7

3.6

3.5

3.4

3.3

3.2

Voh (V)

3.1
3

2.9

2.8

0.00 1.00 2.00 3.00 4.00 5.00

Ioh (mA)

Normalized Icc vs Freq

1.2

1.15

1.1

1.05

Normalized Icc

1

0.95
1 15255075100

Frequency (MHz)

Delta Isb vs Vin (1 input)

10

9
8
7
6
5
4
3

Delta Icc (mA)

2
1
0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50
60

Iik (mA)

70
80
90

100

-2.5 -2 -1.5 -1 -0.5 0

Vik (V)

21

Specifications GAL22V10

GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.1

1.05

1

0.95

Normalized Tpd

0.9

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

RISE
FALL

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

RISE
FALL

Normalized Tco vs Vcc

1.15

1.1

1.05

1

Normalized Tco

0.95

0.9

4.5 4.75 5 5.25 5.5

RISE
FALL

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

Normalized Tco

0.9

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Normalized Tsu vs Temp

1.45

1.35

1.25

1.15

1.05

0.95

Normalized Tsu

0.85

0.75

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Delta Tpd vs # of Outputs

0

-0.4

-0.8

Switching

Delta Tpd (ns)

-1.2
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

20

Delta Tpd (ns)

16
12

8
4
0

-4

-8

RISE
FALL

0 50 100 150 200 250 300

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

0

-0.4

-0.8

Switching

Delta Tco (ns)

-1.2
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

20

16

12

8

4

Delta Tco (ns)

0

-4
0 50 100 150 200 250 3 00

RISE
FALL

Output Loading (pF)

RISE
FALL

22

Specifications GAL22V10

GAL22V10DQ-10 and Slower (L & Q): Typical AC and DC Characteristic Diagrams

Vol vs Iol

0.6

0.4

Vol (V)

0.2

0

0 5 10 15 20 25 30 35 4 0

Iol (mA)

Normalized Icc vs Vcc

1.2

1.1

1

0.9

Normalized Icc

0.8

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

Voh vs Ioh

4.5
4

3.5
3

2.5
2

Voh (V)

1.5
1

0.5
0

0204060

Ioh (mA)

Normalized Icc vs Temp

1.35

1.25

1.15

1.05

0.95

Normalized Icc

0.85

0.75

-55 -25 0 25 50 88 100 125

Temperature (deg. C)

Voh vs Ioh

4.5

4

3.5

Voh (V)

3

2.5

0.00 1.00 2.00 3.00 4.00 5.00

Ioh (mA)

Normalized Icc vs Freq

1.4

1.3

1.2

1.1

Normalized Icc

1

0.9
1 15255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

7

6

5

4

3

2

Delta Icc (mA)

1

0

00.511.522.533.544.55

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-2.5 -2 -1.5 -1 -0.5 0

Vik (V)

23

Specifications GAL22V10

GAL22V10C-5/-7/-10: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55 -25 0 25 50 7 5 100 125

PT H->L
PT L->H

Temperature (deg. C)

PT H->L
PT L->H

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 7 5 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

-1

Delta Tpd (ns)

-1.25

-1.5
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

Delta Tco (ns)

-1
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

12
10

8
6
4
2

Delta Tco (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

24

Specifications GAL22V10

GAL22V10C-5/-7/-10: Typical AC and DC Characteristic Diagrams

Vol vs Iol

3

2.5

2

1.5

Vol (V)

1

0.5

0

0.00 20.00 40.00 60.00 80.00 100.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

4

3.75

3.5

Voh (V)

3.25

3

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.30

1.20

1.10

1.00

Normalized Icc

0.90
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40

Iik (mA)

50
60
70

-2.50 -2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

25

Specifications GAL22V10

GAL22V10B-7/-10/-15/-25L: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

-55

-25

PT H->L
PT L->H

0

25

50

75

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

Temperature (deg. C)

PT H->L
PT L->H

100

125

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

-25

RISE
FALL

0

25

50

75

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55

Temperature (deg. C)

RISE
FALL

100

125

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55

-25

PT H->L
PT L->H

0

25

50

75

Temperature (deg. C)

100

125

Delta Tpd vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tpd (ns)

-2
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tco (ns)

-2
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

12
10

8
6
4
2

Delta Tco (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

26

Specifications GAL22V10

GAL22V10B-7/-10/-15/-25L: Typical AC and DC Characteristic Diagrams

Vol vs Iol

3

2.5

2

1.5

Vol (V)

1

0.5

0

0.00 20.00 40.00 60.00 80.00 100.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

4.5

4.25

4

Voh (V)

3.75

3.5

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.20

1.10

1.00

0.90

Normalized Icc

0.80
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50
60

Iik (mA)

70
80
90

100

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

27

Specifications GAL22V10

GAL22V10B-15/-25Q: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55

-25

0

25

50

75

Temperature (deg. C)

100

125

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55

-25

0

25

50

75

Temperature (deg. C)

100

125

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55

-25

0

25

50

75

Temperature (deg. C)

100

125

Delta Tpd vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

Delta Tpd (ns)

-1
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

Delta Tco vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tco (ns)

-2
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

14
12
10

8
6
4
2

Delta Tco (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

28

Specifications GAL22V10

GAL22V10B-15/-25Q: Typical AC and DC Characteristic Diagrams

Vol vs Iol

1

0.8

0.6

0.4

Vol (V)

0.2

0

0.00 20.00 40.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00

Ioh(mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

-55 -25 0 25 75 100 125

Temperature (deg. C)

Voh vs Ioh

4

3.75

3.5

Voh (V)

3.25

3

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

2.00

1.80

1.60

1.40

1.20

Normalized Icc

1.00

0.80
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

29