Datasheet GAL20VP8B-25LP, GAL20VP8B-15LP, GAL20VP8B-15LJ Datasheet (Lattice Semiconductor Corporation)

GAL20VP8

High-Speed E2CMOS PLD

Generic Array Logic™

Features

• HIGH DRIVE E2CMOS® GAL® DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS

• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins

2

CELL TECHNOLOGY

•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL20V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

®

Advanced CMOS Technology

Functional Block Diagram

I/CLK

I

I

I

I

(64 X 40)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

I

I

IMUX

CLK

8

OLMC

8

OLMC

8

OLMC

8

OLMC

8

OLMC

8

OLMC

8

OLMC

8

OLMC

OE

IMUX

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I
I/OE

Description

Pin Configuration

The GAL20VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli­cations. The GAL20VP8 is manufactured using Lattice
Semiconductor's advanced E2CMOS process which combines
CMOS with Electrically Erasable (E

2

) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently .

System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL20VP8
combines the familiar GAL20V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex­ibility by allowing the Output Logic Macrocell (OLMC) to be con­figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus-driving capability.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles

I/CLK

I

426

5

I
I

Vcc

7

NC

I

9
I
I

11

12 14 16 18

I

NC

I

228

GAL20VP8

T op View

I

NC

I/OE

I/O/Q

I

I

25

23

21

19

I

I/O/Q

I/O/Q

I/O/Q
I/O/Q
I/O/Q
NC
GND
I/O/Q
I/O/Q

I/CLK

Vcc

I/OE

I
I
I
I

I
I

I
I
I

DIPPLCC

1

GAL

20VP8

6

12

I

24

I
I/O/Q
I/O/Q
I/O/Q
I/O/Q

GND

18

I/O/Q
I/O/Q
I/O/Q
I/O/Q

I

13

and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

20vp8_03

1

Specifications GAL20VP8

GAL20VP8 Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package

15 8 10 115 GAL20VP8B-15LP 24-Pin Plastic DIP

115 GAL20VP8B-15LJ 28-Lead PLCC

25 10 15 115 GAL20VP8B-25LP 24-Pin Plastic DIP

115 GAL20VP8B-25LJ 28-Lead PLCC

Part Number Description

GAL20VP8B

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

P = Plastic DIP
J = PLCC

2

Output Logic Macrocell (OLMC)

Specifications GAL20VP8

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina­torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft­ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1(2) and pin 12(14) are permanently con-
figured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible con­figurations in a GAL20VP8. The information given on these archi­tecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.

In complex mode pin 1(2) and pin 12(14) become dedicated in-
puts and use the feedback paths of pin 22(26) and pin 14(17) re­spectively . Because of this feedback path usage, pin 22(26) and
pin 14(17) do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins (pins
17(20) and 19(23)) will not have the feedback option as these pins
are always configured as dedicated combinatorial output.

In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or open­drain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.

3

Registered Mode

Specifications GAL20VP8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub­sets of the I/O function.

CLK

DQ

XOR

OE

Q

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 1(2) controls common CLK for the registered
outputs.

- Pin 12(14) controls common OE for the registered
outputs.

- Pin 1(2) & Pin 12(14) are permanently configured as
CLK & OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 1(2) & Pin 12(14) are permanently configured as
CLK & OE. for registered output configuration.

4

Registered Mode Logic Diagram

1(2)

Specifications GAL20VP8

DIP (PLCC) Package Pinouts

2824 3632201612840

PTD

2640

24(28)

23(27)

2(3)

3(4)

4(5)

5(6)

7(9)

0000

0280

0320

0600

0640

0920

0960

1240

1280

1560

OLMC

XOR-2560
AC1-2632
AC2-2706

OLMC

XOR-2561
AC1-2633
AC2-2707

OLMC

XOR-2562
AC1-2634
AC2-2708

OLMC

XOR-2563
AC1-2635
AC2-2709

OLMC

XOR-2564
AC1-2636
AC2-2710

22(26)

21(25)

20(24)

19(23)

17(20)

8(10)

9(11)

10(12)

11(13)

1600

1880

1920

2200

2240

2520

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

OLMC

XOR-2565
AC1-2637
AC2-2711

16(19)

OLMC

XOR-2566
AC1-2638
AC2-2712

15(18)

OLMC

OE

14(17)

13(16)

12(14)

XOR-2567
AC1-2639
AC2-2713

2703

SYN-2704
AC0-2705

5

Complex Mode

Specifications GAL20VP8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 14(17) & 22(26)) do not have input capability .
Designs requiring eight I/Os can be implemented in the Registered
mode.

XOR

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1(2) and
12(14) are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 15(18) through Pin 21(25) are configured to this
function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 14(17) and Pin 22(26) are configured to this
function.

6

Complex Mode Logic Diagram

1(2)

Specifications GAL20VP8

DIP (PLCC) Package Pinouts

2824 3632201612840

PTD 2640

24(28)

23(27)

2(3)

3(4)

4(5)

5(6)

7(9)

8(10)

0000

0280

0320

0600

0640

0920

0960

1240

1280

1560

1600

1880

OLMC

XOR-2560
AC1-2632
AC2-2706

OLMC

XOR-2561
AC1-2633
AC2-2707

OLMC

XOR-2562
AC1-2634
AC2-2708

OLMC

XOR-2563
AC1-2635
AC2-2709

OLMC

XOR-2564
AC1-2636
AC2-2710

OLMC

XOR-2565
AC1-2637
AC2-2711

22(26)

21(25)

20(24)

19(23)

17(20)

16(19)

9(11)

10(12)

11(13)

1920

2200

2240

2520

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

OLMC

XOR-2566
AC1-2638
AC2-2712

15(18)

OLMC

XOR-2567
AC1-2639
AC2-2713

2703

SYN-2704
AC0-2705

14(17)

13(16)

12(14)

7

Simple Mode

Specifications GAL20VP8

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Vcc

XOR

Pins 1(2) and 12(14) are always available as data inputs into the
AND array. The center two macrocells (pins 17(20) & 19(23)) can­not be used in the input configuration.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- All OLMC except pins 17(20) & 19(23) can be
configured to this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pins 17(20) & 19(23) are permanently configured to
this function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- All OLMC except pins 17(20) & 19(23) can be
configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

8

Simple Mode Logic Diagram

1(2)

Specifications GAL20VP8

DIP (PLCC) Package Pinouts

28

24

201612840

36

32

PTD

2640

24(28)

23(27)

2(3)

3(4)

4(5)

5(6)

7(9)

8(10)

0000

0280

0320

0600

0640

0920

0960

1240

1280

1560

1600

1880

OLMC

XOR-2560
AC1-2632
AC2-2706

OLMC

XOR-2561
AC1-2633
AC2-2707

OLMC

XOR-2562
AC1-2634
AC2-2708

OLMC

XOR-2563
AC1-2635
AC2-2709

OLMC

XOR-2564
AC1-2636
AC2-2710

OLMC

XOR-2565
AC1-2637
AC2-2711

22(26)

21(25)

20(24)

19(23)

17(20)

16(19)

9(11)

10(12)

11(13)

1920

2200

2240

2520

64-USER ELECTRONIC SIGNA TURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

OLMC

XOR-2566
AC1-2638
AC2-2712

15(18)

OLMC

XOR-2567
AC1-2639
AC2-2713

2703

SYN-2704
AC0-2705

14(17)

13(16)

12(14)

9

Specifications GAL20VP8

Absolute Maximum Ratings

(1)

Supply voltage VCC........................................ –.5 to +7V

Input voltage applied .......................... –2.5 to VCC +1.0V

Off-state output voltage applied ......... –2.5 to VCC +1.0V

Storage Temperature ................................–65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient Temperature with

Power Applied ...........................................–55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.4MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

VI
IIL

Input Clamp Voltage Vcc = Min. IIN = –32mA — –1.2 V

2

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High V oltage IOH = MAX. Vin = VIL or VIH 2.4 ——V

IOL Low Level Output Current ——64 mA

IOH High Level Output Current ——–32 mA

3

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –60 —–400 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/-25 — 90 115 mA

Supply Current f

1) Characterized but not 100% tested.

2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.

4) Typical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

10

AC Switching Characteristics

Specifications GAL20VP8

Over Recommended Operating Conditions

COM

PARAMETER UNITS

TEST

COND1.

DESCRIPTION

-15

MIN. MAX.

COM

-25

MIN. MAX.

tpd A Input or I/O to Combinational Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns

2

tcf

— Clock to Feedback Delay — 4.5 — 10 ns

tsu — Setup Time, Input or Feedback before Clock↑ 8 — 10 — ns

th — Hold Time, Input or Feedback after Clock ↑ 0 — 0 — ns

A Maximum Clock Frequency with 55.5 — 40 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 80 — 50 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 80 — 50 — MHz

No Feedback

twh — Clock Pulse Duration, High 6 — 10 — ns

twl — Clock Pulse Duration, Low 6 — 10 — ns

ten B Input or I/O to Output Enabled — 15 — 20 ns

B OE to Output Enabled — 12 — 15 ns

tdis C Input or I/O to Output Disabled — 15 — 20 ns

C OE to Output Disabled — 12 — 15 ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 10 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 15 pF VCC = 5.0V , V

I/O

= 2.0V

11

(

)

Switching Waveforms

Specifications GAL20VP8

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

VALID INPUT

t

pd

tentdis

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

OE

REGISTERED
OUTPUT

VALID INPUT

su

t

(external fdbk)

h

t

t

co

1/

max

f

Registered OutputCombinatorial Output

dis

t

en

t

OE to Output Enable/DisableInput or I/O to Output Enable/Disable

CLK

wh

t

1/fmax

w/o fb

wl

t

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

su

t

Clock Width

fmax with Feedback

12

fmax Descriptions

Specifications GAL20VP8

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured
tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)

T est Condition R

A 500Ω 500Ω 50pF
B Active High ∞ 500Ω 50pF

Active Low 500Ω 500Ω 50pF

C Active High ∞ 500Ω 5pF

Active Low 500Ω 500Ω 5pF

1 R2 CL

13

+5V

R

1

FROM OUTPUT (O/Q)
UNDER TEST

R

2

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

*C

L

C *

L

TEST POINT

Specifications GAL20VP8

Electronic Signature

An electronic signature word is provided in every GAL20VP8 de­vice. It contains 64 bits of reprogrammable memory that can contain
user defined data. Some uses include user ID codes, revision num­bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Signature Cell

The security cell is provided on all GAL20VP8 devices to prevent
unauthorized copying of the array patterns. Once programmed,
the circuitry enabling array is disabled, preventing further program­ming or verification of the array . The cell can only be erased by re­programming the device, so the original configuration can never
be examined once this cell is programmed. Signature data is al­ways available to the user.

Latch-Up Protection

GAL20VP8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos­sibility of SCR induced latching.

operation, certain events occur that may throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

The GAL20VP8 device includes circuitry that allows each registered

output to be synchronously set either high or low. Thus, any present

state condition can be forced for test sequencing. If necessary,

approved GAL programmers capable of executing test vectors can

perform output register preload automatically .

Input Buffers

The GAL20VP8 devices are designed with TTL level compatible

input buffers. These buffers have a characteristically high imped-

ance, and present a much lighter load to the driving logic than

bipolar TTL devices.

GAL20VP8 input buffers have active pull-ups within their input

structure. As a result, unused inputs and I/O's will float to a TTL

"high" (logical "1"). Lattice Semiconductor recommends that all un-

used inputs and tri-stated I/O pins for both devices be connected

to another active input, V

noise immunity and reduce ICC for the device.

T ypical Input Pull-up Characteristic

, or GND. Doing this will tend to improve

CC

Bulk Erase Mode

During a programming cycle, a clear function performs a bulk erase
of the array and the architecture word. In addition, the electronic
signature word and the security cell are erased. This mode resets
a previously configured device back to its original state, which is
all JEDEC ones.

Schmitt Trigger Inputs

One of the enhancements of the GAL20VP8 for bus interface logic
implementation is input gysteresis. The threshold of the positive
going edge is 1.5V , while the threshold of the negative going edge
is 1.3V. This provides a typical hysteresis of 200mV between
positive and negative transitions of the inputs.

Bulk Erase Mode

All eight outputs of the GAL20VP8 are capable of driving 64 mA
loads when driving low and 32 mA loads when driving high. Near
symmetrical high and low output drive capability provides small

skews between high-to-low and low-to-high output transitions.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system

0

-20

-40

Input Current (µA)

-60
0

1.0 2.0 3.0 4.0 5.0

Input Voltage (Volts)

Programmable Open-Drain Outputs

In addition to the standard GAL20V8 type configuration, the out­puts of the GAL20VP8 are individually programmable either as a
standard totempole output or an open-drain output. The totempole
output drives the specified VOH and VOL levels whereas the open­drain output drives only the specified VOL. The VOH level on the
open-drain output depends on the external loading and pull-up. This
output configuration is controlled by the AC2 fuse. When AC2 cell
is erased (JEDEC "1") the output is configured as a totempole out­put and when AC2 cell is programmed (JEDEC "0") the output is
configured as an open-drain. The default configuration when the
device is in bulk erased state is totempole configuration. The AC2
fuses associated with each of the outputs is included in all of the
logic diagrams.

14

Power-Up Reset

Vcc

Specifications GAL20VP8

Vcc (min.)

tsu

CLK

INTERNAL REGISTER

FEEDBACK/EXTERNAL

Q - OUTPUT

OUTPUT REGISTER

Circuitry within the GAL20VP8 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q out-

puts set low after a specified time (

tpr, 1 µs MAX). As a result, the

state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of
the output pins. This feature can greatly simplify state machine
design by providing a known state on power-up. The timing dia­gram for power-up is shown above. Because of the asynchro-

Input/Output Equivalent Schematics

PIN

twl

tpr

Internal Register
Reset to Logic "0"

Device P in
Reset to Logic "1"

nous nature of system power-up, some conditions must be met
to provide a valid power-up reset of the GAL20VP8. First, the VCC
rise must be monotonic. Second, the clock input must be at static
TTL level as shown in the diagram during power up. The registers

will reset within a maximum of tpr time. As in normal system op­eration, avoid clocking the device until all input and feedback path

setup times have been met. The clock must also meet the mini­mum pulse width requirements.

PIN

PIN

Vref = 3.1V

ESD
Protection
Circuit

ESD
Protection
Circuit

Active Pull-up

Circuit

Vcc

Vref

Vcc

Vcc

Data
Output

Vref = 3.1V

Feedback

Tri-State
Control

Active Pull-up
Circuit

Vcc

Vref

PIN

Feedback
(To Input Buffer)

T ypical OutputTypical Input

15

Typical AC and DC Characteristic Diagrams

Specifications GAL20VP8

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

PT H->L
PT L->H

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

PT H->L
PT L->H

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE

FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

Delta Tpd (ns)

-0.5
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

6

4

2

0

Delta Tpd (ns)

-2

0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

-1

Delta Tco (ns)

-1.25
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

6

4

2

0

Delta Tco (ns)

-2

0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

16

Typical AC and DC Characteristic Diagrams

Specifications GAL20VP8

Vol vs Iol

0.5

0.4

0.3

0.2

Vol (V)

0.1

0

0.00 20.00 40.00 60.00 80.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

0.8

Normalized Icc

0.7

-55 -25 0 2 5 75 100 125

Temperature (deg. C)

Voh vs Ioh

4.5

4.25

4

Voh (V)

3.75

3.5

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.40

1.30

1.20

1.10

1.00

Normalized Icc

0.90
0 25 50 7 5 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

3

2.5

2

1.5

1

Delta Icc (mA)

0.5

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

17