Datasheet GAL20LV8ZD-25QJ, GAL20LV8ZD-15QJ Datasheet (Lattice Semiconductor Corporation)

GAL20LV8ZD

Low V oltage, Zero Power E2CMOS PLD

Generic Array Logic™

Features

• 3.3V LOW VOL TAGE, ZERO POWER OPERATION
— JEDEC Compatible 3.3V Interface Standard
— Interfaces with Standard 5V TTL Devices

µA Typical Standby Current (100µA Max.)

—50
— 45mA Typical Active Current (55mA Max.)
— Dedicated Power-down Pin

2

• HIGH PERFORMANCE E
— TTL Compatible Balanced 8 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 62.5 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS

2

CELL TECHNOLOGY

•E

®

Advanced CMOS Technology

— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— Ideal for Mixed 3.3V and 5V Systems

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

CMOS TECHNOLOGY

Functional Block Diagram

I/CLK

I

I

DPP

I

I

(64 X 40)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

8

8

8

8

8

8

8

8

IMUX

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

IMUX

I

CLK

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I
I/OE

Description

The GAL20LV8ZD, at 100 µA standby current and 15ns propagation
delay provides the highest speed low-voltage PLD available in the
market. The GAL20LV8ZD is manufactured using Lattice
Semiconductor's advanced 3.3V E
bines CMOS with Electrically Erasable (E2) floating gate technology.

The GAL20L V8ZD utilizes a dedicated power-down pin (DPP) to
put the device into standby mode. It has 19 inputs available to the
AND array and is capable of interfacing with both 3.3V and stan­dard 5V devices.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

2

CMOS process, which com-

Pin Configuration

I

4

5

DPP

I

GAL20LV8ZD

I

7

NC

I

9
I
I

11

12 14 16 18

I

PLCC

I/CLK

NC

I

228

T op V iew

I

NC

GND

Vcc

I/OE

I/O/Q

I

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

I

I/O/Q

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

20lv8zd_03

1

Specifications GAL20LV8ZD

GAL20LV8ZD Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (µA) Ordering # Package

15 12 10 55 100 GAL20LV8ZD-15QJ 28-Lead PLCC
25 15 15 55 100 GAL20LV8ZD-25QJ 28-Lead PLCC

Part Number Description

GAL20LV8ZD (Zero Power DPP)

Device Name

Speed (ns)

Active Power

Q = Quarter Power

XXXXXXXX XX X X X

_

Grade

Blank = Commercial

Package

J = PLCC

2

Output Logic Macrocell (OLMC)

Specifications GAL20LV8ZD

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina­torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft­ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.

In registered mode pin 2 and pin 16 are permanently configured
as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in­put/output configuration. These two global and 16 individual archi­tecture bits define all possible configurations in a GAL20L V8ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans­parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively . Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

When using the standard GAL20V8 JEDEC fuse pattern generated
by the logic compilers for the GAL20L V8ZD, special attention must
be given to pin 5 (DPP) to make sure that it is not used as one of
the functional inputs.

3

Registered Mode

Specifications GAL20LV8ZD

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub­sets of the I/O function.

CLK

DQ

XOR

OE

Q

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

Pin 5 is used as dedicated power-down pin on GAL20LV8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 2 controls common CLK for the registered
outputs.

- Pin 16 controls common OE for the registered
outputs.

- Pin 2 & Pin 16 are permanently configured as
CLK & OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1=1 defines this output configuration.

- Pin 2 & Pin 16 are permanently configured as

CLK & OE for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL20LV8ZD

PLCC Package Pinout

2

28

24

201612840

32

3

0000

0280

4

0320

2640

36

PTD

27

OLMC

26

XOR-2560
AC1-2632

OLMC

25

5

6

7

9

0600

Power

Management

Control

0640

0920

0960

1240

1280

1560

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

24

23

21

10

11

12
13

MSB LSB

1600

1880

1920

2200

2240

2520

2703

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

OLMC

XOR-2565
AC1-2637

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

SYN-2704
AC0-2705

OE

20

19

18

17
16

5

Complex Mode

Specifications GAL20LV8ZD

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability . De­signs requiring eight I/Os can be implemented in the Registered
mode.

XOR

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.

Pin 5 is used as dedicated power-down pin on GAL20L V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1 has no effect on this mode.

- Pin 18 and Pin 26 are configured to this function.

6

Complex Mode Logic Diagram

Specifications GAL20LV8ZD

PLCC Package Pinout

2

3

4

5

6

7

9

0000

0280

0320

0600

Power

Management

Control

0640

0920

0960

1240

1280

1560

24

32

201612840

28

2640

36

PTD

27

OLMC

XOR-2560

26

AC1-2632

OLMC

25

XOR-2561
AC1-2633

OLMC

24

XOR-2562
AC1-2634

OLMC

23

XOR-2563
AC1-2635

OLMC

21

XOR-2564
AC1-2636

10

11

12
13

MSB LSB

1600

1880

1920

2200

2240

2520

64-USER ELECTRONIC SIGNA TURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

7

2703

OLMC

XOR-2565
AC1-2637

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

20

19

18

17
16

SYN-2704
AC0-2705

Simple Mode

Specifications GAL20LV8ZD

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of ge­neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Pins 2 and 16 are always available as data inputs into the AND
array . The center two macrocells (pins 21 & 23) cannot be used
in the input configuration.

Pin 5 is used as dedicated power-down pin on GAL20L V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 21 & 23 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

Vcc

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 21 & 23 are permanently configured to
this function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 21 & 23 can be configured to
this function.

8

Simple Mode Logic Diagram

2

3

Specifications GAL20LV8ZD

PLCC Package Pinouts

24

32

201612840

28

2640

36

PTD

27

10

0000

0280

OLMC

XOR-2560
AC1-2632

26

4

0320

5

0600

Power

Management

Control

0640

0920

OLMC

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

25

24

6

0960

1240

OLMC

XOR-2563
AC1-2635

23

7

1280

1560

OLMC

XOR-2564
AC1-2636

21

9

1600

1880

OLMC

XOR-2565
AC1-2637

20

11

12
13

1920

2200

2240

2520

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

OLMC

XOR-2566
AC1-2638

19

OLMC

XOR-2567
AC1-2639

2703

SYN-2704
AC0-2705

18

17
16

9

Specifications GAL20LV8ZD

Absolute Maximum Ratings

Supply voltage VCC.................................... -0.5 to +5.6V

Input voltage applied ................................. -0.5 to +5.6V

Off-state output voltage applied ................ -0.5 to +5.6V

Storage Temperature .................................-65 to 150°C

Ambient Temperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

(1)

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) .............................0 to +75°C

Supply voltage (VCC)

with Respect to Ground ......................... +3.0 to +3.6V

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — 5.25 V

IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA

IIH Input or I/O High Leakage Current (VCC-0.2)V ≤ VIN ≤ VCC ——10µA

VCC ≤ VIN ≤ 5.25V —— 1mA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

OH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V

I
IOH = -100µA Vin = VIL or VIH Vcc-0.2 — — V

IOL Low Level Output Current — — 8 mA

IOH High Level Output Current — — -8 mA

1

IOS

Output Short Circuit Current VCC = 3.3V VOUT = GND TA = 25°C -30 — -130 mA

COMMERCIAL

ISB Stand-by Power VIL = GND VIH = Vcc Outputs Open ZD -15/-25 — 50 100 µA

Supply Current

ICC Operating Power VIL = 0.5V VIH = 3.0V ZD -15/-25 — 45 55 mA

Supply Current f

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

2) T ypical values are at Vcc = 3.3V and TA = 25 °C

toggle = 15 MHz Outputs Open

10

Specifications GAL20LV8ZD

AC Switching Characteristics

Over Recommended Operating Conditions

COMCOM

PARAM

TEST

COND.

DESCRIPTION

1

-15

MIN. MAX.

tpd A Input or I/O to Combinatorial Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns

2

tcf

— Clock to Feedback Delay — 8 — 10 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 12 — 15 — ns

th — Hold Time, Input or Fdbk after Clk↑ 0—0—ns

A Maximum Clock Frequency with 45.5 — 33.3 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 50 — 40 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 62.5 — 41.6 — MHz

No Feedback

-25

MIN. MAX.

UNITS

twh — Clock Pulse Duration, High 8 — 12 — ns

twl — Clock Pulse Duration, Low 8 — 12 — ns

ten B Input or I/O to Output Enabled — 17 — 25 ns

BOE↓ to Output Enabled — 16 — 20 ns

tdis C Input or I/O to Output Disabled — 18 — 25 ns

COE↑ to Output Disabled — 17 — 20 ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C

I

C

I/O

Input Capacitance 8 pF VCC = 3.3V , VI = 0V

I/O Capacitance 8 pF VCC = 3.3V , V

I/O

= 0V

11

Dedicated Power-Down Pin Specications

Over Recommended Operating Conditions

Specifications GAL20LV8ZD

COM

PARAMETER UNITS

TEST

COND1.

DESCRIPTION

-15

MIN. MAX.

COM

-25

MIN. MAX.

twhd — DPP Pulse Duration High 40 — 40 — ns

twld — DPP Pulse Duration Low 30 — 40 — ns

ACTIVE TO STANDBY

tivdh — Valid Input before DPP High 0 — 0 — ns

tgvdh — Valid OE before DPP High 0 — 0 — ns

tcvdh — Valid Clock before DPP High 0 — 0 — ns

tdhix — Input Don't Care after DPP High — 15 — 25 ns

tdhgx — OE Don't Care after DPP High — 15 — 25 ns

tdhcx — Clock Don't Care after DPP High — 15 — 25 ns

ST ANDBY T O ACTIVE

tixdl — Input Don't Care before DPP Low — 0 — 0 ns
tgxdl — OE Don't Care before DPP Low — 0 — 0 ns
tcxdl — Clock Don't Care before DPP Low — 0 — 0 ns

tdliv — DPP Low to Valid Input 20 — 25 — ns
tdlgv — DPP Low to Valid OE 20 — 25 — ns
tdlcv — DPP Low to Valid Clock 30 — 35 — ns
tdlov A DPP Low to Valid Output 5 45 5 45 ns

1) Refer to Switching T est Conditions section.

Dedicated Power-Down Pin Timing Waveforms

DPP

t

INPUT or
I/O FEEDBACK

OE

CLK

OUTPUT

t

cvdh

t

ivdh

gvdh

t

co

t

dhix

t

dhgx

t

dhcx

t

pd,ten,tdis

t

t

t

dlov

dlcv

t

dliv

dlgv

t

ixdl

t

gxdl

t

cxdl

12

(

)

Switching Waveforms

Specifications GAL20LV8ZD

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

t

pd

Combinatorial Output

dis

t

wh

t

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

su

t

t

t

1/

f

max

(external fdbk)

h

co

Registered Output

en

t

OE

en

t

REGISTERED
OUTPUT

dis

t

OE to Output Enable/Disable

wl

t

CLK

1/fmax

w/o fb

Clock Width

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

fmax with Feedback

su

t

13

TEST POINT

C *

L

FROM OUTPUT (O/Q)
UNDER TEST

+3.3V

*C

L

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

R

2

R

1

fmax Descriptions

Specifications GAL20LV8ZD

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from

measured tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh

+ twl). This is to allow for a clock duty cycle of other
than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf

= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed­back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 2ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level. 3-state to active transitions are measured at (Voh - 0.5)
V and (Vol + 0.5) V.

Output Load Conditions (see figure)

Test Condition R

A 270Ω 220Ω 35pF
B Active High 270Ω 220Ω 35pF

C Active High 270Ω 220Ω 5pF

1 R2 CL

Active Low 270Ω 220Ω 35pF

Active Low 270Ω 220Ω 5pF

14

Specifications GAL20LV8ZD

Electronic Signature

An electronic signature word is provided in every GAL20LV8ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al­ways available to the user independent of the state of the security
cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter checksum.

Security Cell

A security cell is provided in the GAL20LV8ZD devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de­vice, so the original configuration can never be examined once this
cell is programmed. The electronic signature data is always avail­able to the user, regardless of the state of this security cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL20LV8ZD devices includes circuitry that allows each reg­istered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec­essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically .

Input Buffers

GAL20LV8ZD devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

Dedicated Power-Down Pin

The GAL20LV8ZD uses pin 5 as the dedicated power-down sig­nal to put the device in to the power-down state. DPP is an active
high signal where a logic high driven on this signal puts the device
into power-down state. Input pin 5 cannot be used as a logic func­tion input on this device.

15

Power-Up Reset

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

Vcc (min.)

Specifications GAL20LV8ZD

t

su

t

wl

t

pr

Internal Register
Reset to Logic "0"

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Circuitry within the GAL20L V8ZD provides a reset signal to all reg­isters during power-up. All internal registers will have their Q out­puts set low after a specified time (

tpr, 10µs MAX). As a result,

the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the

Input/Output Equivalent Schematic

PIN

Vcc

ESD
Protection
Circuit

Vcc

Vcc

Device P in
Reset to Logic "1"

asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL20L V8ZD.
First, the V

CC rise must be monotonic. Second, the clock input

must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of

tpr time. As in

normal system operation, avoid clocking the device until all input
and feedback path setup times have been met. The clock must
also meet the minimum pulse width requirements.

PIN

Feedback

Tri-State
Control

Vcc

PIN

ESD
Protection
Circuit

16

Data
Output

PIN

Feedback
(To Input Buffer)

Typical OutputT ypical Input

Typical AC and DC Characteristics

Specifications GAL20LV8ZD

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

-55

-25

PT H->L
PT L->H

0

25

50

75

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

Temperature (deg. C)

PT H->L
PT L->H

100

125

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tco vs Temp

1.3

-25

RISE
FALL

0

25

50

75

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55

Temperature (deg. C)

RISE
FALL

100

125

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

3.00 3.15 3.30 3.45 3.60

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55

-25

PT H->L
PT L->H

0

25

50

75

Temperature (deg. C)

100

125

Delta Tpd vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

Delta Tpd (ns)

-1
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

12
10

8
6
4
2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

Delta Tco (ns)

-0.5
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

12
10

8
6
4
2
0

Delta Tco (ns)

-2

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

17

Typical AC and DC Characteristics

Specifications GAL20LV8ZD

Vol vs Iol

1.5

1.25

1

0.75

Vol (V)

0.5

0.25

0

0.00 20.00 40.00 60.00 80.00

Iol (mA)

Normalized Icc vs Vcc

1.30

1.20

1.10

1.00

0.90

Normalized Icc

0.80

0.70

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Voh vs Ioh

3

2.5

2

1.5

Voh (V)

1

0.5

0

0.00 10.00 20.00 30.00 40.00 50.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.15

1.1

1.05

1

Normalized Icc

0.95

0.9

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

3

2.975

2.95

2.925

Voh (V)

2.9

2.875

2.85

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

2.00

1.75

1.50

1.25

1.00

Normalized Icc

0.75
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

4

3

2

1

Delta Icc (mA)

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50
60

Iik (mA)

70
80
90

100

-1.50 -1.20 -0.90 -0.60 -0.30 0.00

Vik (V)

18