Datasheet GAL20LV8D-5LJ, GAL20LV8D-3LJ, GAL20LV8D-7LJ Datasheet (Lattice Semiconductor Corporation)

New 5V

Tolerant

Inputs on
20LV8D

GAL20LV8

Low V oltage E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— TTL-Compatible Balanced 8mA Output Drive

• 3.3V LOW VOL TAGE 20V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs

• ACTIVE PULL-UPS ON ALL PINS

2

CELL TECHNOLOGY

•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

®

Advanced CMOS Technology

Functional Block Diagram

I/CLK

I

I

I

I

I

(64 X 40)

I

AND-ARRAY

PROGRAMMABLE

I

I

I

I

8

8

8

8

8

8

8

8

IMUX

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

IMUX

I

CLK

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I
I/OE

Description

The GAL20LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL20LV8D is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com­bines CMOS with Electrically Erasable (E

2

) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro­grammed quickly and efficiently .

The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura­tions possible with the GAL20L V8D are the P AL

architectures listed
in the table of the macrocell description section. GAL20LV8D
devices are capable of emulating any of these P AL architectures
with full function/fuse map compatibility .

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 2000
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

20lv8_05

Pin Configuration

I
I
I

NC

I
I
I

11

1

PLCC

I/CLK

I

I

4

5

7

GAL20LV8D

9

12 14 16 18

I

I

NC

Vcc

228

Top V iew

NC

GND

I/OE

I/O/Q

I

26

25

I/O/Q
I/O/Q

23

I/O/Q
NC

21

I/O/Q
I/O/Q

19

I/O/Q

I

I/O/Q

Specifications GAL20LV8

GAL20LV8D Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package

3.5 3 2.5
5 4 3 70 GAL20LV8D-5LJ 28-Lead PLCC

7.5 5 5

70

70 GAL20LV8D-7LJ

Part Number Description

GAL20LV8D-3LJ 28-Lead PLCC

28-Lead PLCC

GAL20LV8D

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

J = PLCC

2

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in­put/output configuration. These two global and 16 individual archi­tecture bits define all possible configurations in a GAL20LV8D . The
information given on these architecture bits is only to give a bet­ter understanding of the device. Compiler software will transpar­ently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.

The following is a list of the P AL architectures that the GAL20L V8D
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.

Specifications GAL20LV8

PAL Architectures GAL20LV8D

Emulated by GAL20L V8D Global OLMC Mode

20R8 Registered
20R6 Registered

20R4 Registered
20RP8 Registered
20RP6 Registered
20RP4 Registered

20L8 Complex

20H8 Complex

20P8 Complex

14L8 Simple

16L6 Simple

18L4 Simple

20L2 Simple

14H8 Simple

16H6 Simple

18H4 Simple

20H2 Simple

14P8 Simple

16P6 Simple

18P4 Simple

20P2 Simple

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft­ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 2 and pin 16 are permanently configured

Registered Complex Simple Auto Mode Select

ABEL P20V8R P20V8C P20V8AS P20V8
CUPL G20V8MS G20V8MA G20V8AS G20V8
LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8
OrCAD-PLD "Registered"
PLDesigner P20V8R

1

2

"Complex"

P20V8C

TANGO-PLD G20V8R G20V8C G20V8AS

as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

In complex mode pin 2 and pin 16 become dedicated inputs and
use the feedback paths of pin 26 and pin 18 respectively . Because
of this feedback path usage, pin 26 and pin 18 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
21 and 23) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

1

2

"Simple"
P20V8C

1
2

3

GAL20V8A

P20V8A

G20V8

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

3

Registered Mode

Specifications GAL20LV8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.

CLK

DQ

XOR

OE

Q

Dedicated input or output functions can be implemented as sub­sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 2 controls common CLK for the registered outputs.

- Pin 16 controls common OE for the registered outputs.

- Pin 2 & Pin 16 are permanently configured as CLK &
OE for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- Pin 2 & Pin 16 are permanently configured as CLK &
OE for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL20LV8

PLCC Package Pinout

2

41612802024283236

3

0000

0280

4

0320

0600

5

0640

0920

6

0960

1240

7

1280

1560

9

PTD

2640

OLMC

XOR-2560
AC1-2632

OLMC

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

27

26

25

24

23

21

10

11

12

13

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

1600

1880

1920

2200

2240

2520

2703

OLMC

XOR-2565
AC1-2637

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

SYN-2704
AC0-2705

OE

20

19

18

17

16

5

Complex Mode

Specifications GAL20LV8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 18 & 26) do not have input capability . De-

XOR

signs requiring eight I/Os can be implemented in the Registered
mode.

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 2 and
16 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 19 through Pin 25 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 18 and Pin 26 are configured to this function.

6

Complex Mode Logic Diagram

2

41612802024283236

3

Specifications GAL20LV8

PLCC Package Pinout

2640

PTD

27

0000

0280

4

0320

0600

5

0640

0920

6

0960

1240

7

1280

1560

9

1600

1880

10

OLMC

XOR-2560
AC1-2632

OLMC

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

OLMC

XOR-2565
AC1-2637

26

25

24

23

21

20

11

12

13

MSB LSB

1920

2200

2240

2520

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

7

2703

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

19

18

17

16

SYN-2704
AC0-2705

Simple Mode

Specifications GAL20LV8

In the Simple mode, pins are configured as dedicated inputs or as
dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 14L8 and 16P6 devices with many permutations of ge­neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Pins 2 and 16 are always available as data inputs into the AND
array . The "center" two macrocells (pins 21 & 23) cannot be used
in the input configuration.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 21 & 23 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

Vcc

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 21 & 23 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 21 & 23 can be configured to
this function.

8

Simple Mode Logic Diagram

2

3

Specifications GAL20LV8

PLCC Package Pinout

41612802024283236

2640

PTD

27

0000

0280

4

0320

0600

5

0640

0920

6

0960

1240

7

1280

1560

9

1600

1880

10

OLMC

XOR-2560
AC1-2632

OLMC

XOR-2561
AC1-2633

OLMC

XOR-2562
AC1-2634

OLMC

XOR-2563
AC1-2635

OLMC

XOR-2564
AC1-2636

OLMC

XOR-2565
AC1-2637

26

25

24

23

21

20

1920

2200

11

2240

2520

12

13

2703

OLMC

XOR-2566
AC1-2638

OLMC

XOR-2567
AC1-2639

19

18

17

16

64-USER ELECTRONIC SIGNATURE FUSES

2568, 2569, .... .... 2630, 2631

Byte7 Byte6 .... .... Byte1 Byte0

SYN-2704
AC0-2705

MSB LSB

9

Specifications GAL20LV8

Absolute Maximum Ratings

(1)

Supply voltage VCC................................... –0.5 to +4.6V

Input voltage applied ................................ –0.5 to +5.6V

I/O voltage applied ................................... –0.5 to +4.6V

Off-state output voltage applied ............... –0.5 to +4.6V

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ......................... +3.0 to +3.6V

Storage Temperature ................................–65 to 150°C

Ambient Temperature with

Power Applied........................................ –55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

3

SYMBOL PARAMETER CONDITION MIN. TYP.

MAX. UNITS

VIL Input Low Voltage Vss – 0.3 — 0.8 V
VIH Input High V oltage 2.0 — 5.25 V

I/O High Voltage 2.0 — Vcc+0.5 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC ——10µA

Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA
I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V

IOL = 500µA Vin = VIL or VIH — — 0.2 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOH = -100µA Vin = VIL or VIH Vcc-0.2V — — V

IOL Low Level Output Current — — 8 mA
IOH High Level Output Current — — –8 mA

2

IOS

Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA= 25°C –15 — –80 mA

COMMERCIAL

ICC Operating Power VIL = 0V VIH = 3.0V Unused Inputs at VIL —4570mA

Supply Current f

toggle = 1MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 3.3V and TA = 25 °C

10

AC Switching Characteristics

Specifications GAL20LV8

Over Recommended Operating Conditions

COM

-5

MIN. MAX.

-7

MIN. MAX.

UNITSPARAMETER

tpd

tco

tcf

COM COM

TEST

COND

2

2

3

A Input or I/O to Combinational Output 1 3.5 1 5 1 7.5 ns
A Clock to Output Delay 1 2.5 1 3 1 5 ns

— Clock to Feedback Delay — 2 — 2 — 3 ns

DESCRIPTION

1

.

-3

MIN. MAX.

tsu — Setup Time, Input or Feedback before Clock ↑ 3—4—5—ns

th — Hold Time, Input or Feedback after Clock↑ 0—0—0—ns

A Maximum Clock Frequency with 180 — 142.8 — 100 — MHz

External Feedback, 1/(tsu + tco)

4

fmax

twh

twl

4

4

A Maximum Clock Frequency with 200 — 166 — 125 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 166 — 125 — MHz

No Feedback

— Clock Pulse Duration, High 2 — 3 — 4 — ns
— Clock Pulse Duration, Low 2 — 3 — 4 — ns

ten B Input or I/O to Output Enabled — 4.5 — 6 — 7.5 ns

B OE to Output Enabled — 3.5 — 5 — 6.5 ns

tdis C Input or I/O to Output Disabled — 4.5 — 6 — 7.5 ns

C OE to Output Disabled — 3.5 — 5 — 6.5 ns

1) Refer to Switching T est Conditions section.

2) Minimum values for tpd and tco are not 100% tested but established by characterization.

3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

4) Refer to fmax Descriptions section. Characterized but not 100% tested.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C

I

C

I/O

Input Capacitance 5 pF VCC = 3.3V , VI = 0V

I/O Capacitance 5 pF VCC = 3.3V , V

I/O

= 0V

11

(

)

Switching Waveforms

Specifications GAL20LV8

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

VALID INPUT

t

pd

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

su

t

t

t

1/

f

max

(external fdbk)

h

co

Registered OutputCombinatorial Output

OE

dis

t

en

t

REGISTERED
OUTPUT

dis

t

en

t

OE to Output Enable/DisableInput or I/O to Output Enable/Disable

CLK

wh

t

1/fmax

w/o fb

wl

t

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

su

t

Clock Width

fmax with Feedback

12

fmax Descriptions

Specifications GAL20LV8

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured
tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 1.5ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure

TEST POINT

FROM OUTPUT (O/Q)
UNDER TEST

*CL includes test fixture and probe capacitance.

Output Load Conditions (see figure)

Test Condition R

A50Ω 35pF
B High Z to Active High at 1.9V 50Ω 35pF

High Z to Active Low at 1.0V 50Ω 35pF

C Active High to High Z at 1.9V 50Ω 35pF

Active Low to High Z at 1.0V 50Ω 35pF

+1.45V

0

= 50Ω, CL = 35pF*

Z

1 CL

R

1

13

Specifications GAL20LV8

Electronic Signature

An electronic signature is provided in every GAL20L V8D device.
It contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided in the GAL20LV8D devices to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de­vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.

Latch-Up Protection

GAL20LV8D devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential of latch-up caused by negative input undershoots.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers. Complete programming of the device takes only a few
seconds. Erasing of the device is transparent to the user, and is
done automatically as part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state

transitions must be verified in the design, not just those required

in the normal machine operations. This is because, in system

operation, certain events occur that may throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

GAL20L V8D devices include circuitry that allows each registered

output to be synchronously set either high or low. Thus, any present

state condition can be forced for test sequencing. If necessary,

approved GAL programmers capable of executing text vectors

perform output register preload automatically .

Input Buffers

GAL20LV8D devices are designed with TTL level compatible input

buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

devices.

The GAL20L V8D input and I/O pins have built-in active pull-ups.

As a result, unused inputs and I/Os will float to a TTL “high”

(logical “1”). Lattice Semiconductor recommends that all unused

inputs and tri-stated I/O pins be connected to another active input,

VCC, or Ground. Doing this will tend to improve noise immunity

and reduce ICC for the device.

T ypical Input Pull-up Characteristic

0

-10

-20

-30

-40

-50

-60

Input Current (µA)

-70

-80
0

0.5

1

1.5

Input Voltage (V)

2

2.5

3

3.5

4

14

Power-Up Reset

Specifications GAL20LV8

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Circuitry within the GAL20L V8D provides a reset signal to all reg­isters during power-up. All internal registers will have their Q outputs
set low after a specified time (

tpr, 1µs MAX). As a result, the state

on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro­nous nature of system power-up, some conditions must be met to

Input/Output Equivalent Schematics

t

su

t

wl

t

pr

Internal Register
Reset to Logic "0"

Device P in
Reset to Logic "1"

provide a valid power-up reset of the device. First, the V

CC rise must

be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will re­set within a maximum of

tpr time. As in normal system operation,

avoid clocking the device until all input and feedback path setup
times have been met. The clock must also meet the minimum pulse
width requirements.

PIN

ESD
Protection
Circuit

PIN

Typ. V ref = Vcc

ESD
Protection
Circuit

Active Pull-up
Circuit

Vcc

Vref

T ypical Input

Vcc

Vcc

Feedback

Tri-State
Control

Data
Output

Typ. V ref = Vcc

Active Pull-up
Circuit

Vcc

Vref

Feedback
(To Input Buffer)

T ypical Output

PIN

PIN

15

Typical AC and DC Characteristic Diagrams

Specifications GAL20LV8

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tpd vs Temp

1.2

1.1

1

0.9

Normalized Tpd

0.8

PT H->L
PT L->H

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

PT H->L
PT L->H

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tco vs Temp

1.2

1.1

1

0.9

Normalized Tco

0.8

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

3.00 3.15 3.30 3.45 3.60

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.2

1.1

1

0.9

Normalized Tsu

0.8

PT H->L
PT L->H

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

Delta Tpd (ns)

-0.5
12345678

Number of Outputs Switching

Delta Tpd vs Output

Loading

18

14

10

6

2

Delta Tpd (ns)

-2

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

Delta Tco (ns)

-0.5
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

16

12

8

4

0

Delta Tco (ns)

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

16

Typical AC and DC Characteristic Diagrams

Specifications GAL20LV8

Vol vs Iol

1

0.75

0.5

Vol (V)

0.25

0

0.00 5.00 10.00 15.00 20.00 25.00 30.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Voh vs Ioh

3

2.5

2

1.5

Voh (V)

1

0.5

0

0.00 5.00 10.00 15.00 20.00 25.00 30.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

3

2.95

2.9

Voh (V)

2.85

2.8

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.40

1.30

1.20

1.10

1.00

Normalized Icc

0.90

0.80
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0

5
10
15
20
25

Iik (mA)

30
35
40

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

17