Datasheet GAL18V10B-7LJ, GAL18V10B-20LP, GAL18V10B-20LJ, GAL18V10B-15LP, GAL18V10B-15LJ Datasheet (Lattice Semiconductor Corporation)

GAL18V10

High Performance E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 11 1 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS

®

Advanced CMOS Technology

• LOW POWER CMOS
— 75 mA T ypical Icc

• ACTIVE PULL-UPS ON ALL PINS

2

CELL TECHNOLOGY

• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

Description

The GAL18V10, at 7.5 ns maximum propagation delay time, com­bines a high performance CMOS process with Electrically Eras­able (E2) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E2 technol­ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently .

By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com­patible with the OLMC in standard bipolar and CMOS 22V10 de­vices.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Functional Block Diagram

I/CLK

I

I

I

I

AND-ARRAY

RESET

8

8

8

10

10

(96X36)

8

PROGRAMMABLE

I

I

I

8

8

PRESET

Pin Configuration

PLCC

I/CLKI

2

T op View

11

Vcc

I/O/Q

20

18

I/O/Q

I/O/Q

I/O/Q

16

I/O/Q

I/O/Q

14

13

I

4

I

I

I

I

I

GAL18V10

6

8

9

GND I/O/Q I/O/QI/O/Q I/O/Q

8

8

I/CLK

I/O/Q

GND

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

I

I

I

I

I

I

I

DIP

1

GAL

18V10

5

10

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

20

15

11

Vcc

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. [phone]; 1-888-ISP-PLDS; FAX [phone]; http://www.latticesemi.com

18v10_03

1

GAL18V10 Ordering Information

Commercial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.765.5511
511

0177 511

511

51801511

511
511PL51-01V81LAGPIDcitsalPniP-02
511JL51-01V81LAGCCLPdaeL-02

022121511

511
511PL02-01V81LAGPIDcitsalPniP-02
511JL02-01V81LAGCCLPdaeL-02

01V81LAG B-7 PL
01V81LAG B-7 JL
01V81LAGB1-0PL
01V81LAGB1-0JL
01V81LAGBPL51­01V81LAGBJL51-

01V81LAGBPL02­01V81LAGBJL02-

Specifications GAL18V10

PIDcitsalPniP-02

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

PIDcitsalPniP-02

CCLPdaeL-02

Part Number Description

GAL18V10B

GAL18V10

Device Name

Speed (ns)

PowerL = Low Power

XXXXXXXX XX X X X

_

Grade

Package

Blank = Commercial

P = Plastic DIP
J = PLCC

2

Output Logic Macrocell (OLMC)

Specifications GAL18V10

The GAL18V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to ten prod­uct terms (pins 14 and 15), and the other eight OLMCs have eight
product terms each. In addition to the product terms available for
logic, each OLMC has an additional product-term dedicated to out­put enable control.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.

AR

D

The GAL18V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod­uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registered outputs to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.

NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.

Q
QCLK

4 TO 1

MUX

SP

2 TO 1

MUX

GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)

Output Logic Macrocell Configurations

Each of the Macrocells of the GAL18V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the the following page.

REGISTERED

In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in­dividual product term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg­istered is an output only , and cannot be used for dynamic
I/O, as can the combinatorial pins.

COMBINAT ORIAL I/O

In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out­put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer . Both polarities (true and inverted)
of the pin are fed back into the AND array.

3

Registered Mode

Specifications GAL18V10

CLK

S0 = 0
S1 = 0

Combinatorial Mode

AR

D

SP

Q

Q

S0 = 1
S1 = 0

CLK

AR

D

ACTIVE HIGHACTIVE LOW

Q

Q

SP

S0 = 0
S1 = 1

ACTIVE HIGHACTIVE LOW

S0 = 1
S1 = 1

4

GAL18V10 Logic Diagram/JEDEC Fuse Map

DIP and PLCC Package Pinouts

1

0000

0036

0324

0360

0648

2

0684

0972

3

1008

1296

4

1332

1692

5

1728

2088

6

2124

2412

7

2448

2736

8

2772

3060

3096

3384

3420

0 4 8 12 16 20 24 28 32

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.
.

.
.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

L
S
B

Electronic Signature

3476, 3477 ...

Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0

M
S
B

... 3538, 3539

Specifications GAL18V10

ASYNCHRONOUS RESET
(TO ALL REGISTERS)

8

8

8

8

10

10

8

8

8

8

OLMC

S0

3456

S1

3457

OLMC

S0

3458

S1

3459

OLMC

SO

3460

S1

3461

OLMC

S0

3462

S1

3463

OLMC

S0

3464

S1

3465

OLMC

S0

3466

S1

3467

OLMC

S0

3468

S1

3469

OLMC

S0

3470

S1

3471

OLMC

S0

3472

S1

3473

OLMC

S0

3474

S1

3475

SYNCHRONOUS PRESET
(TO ALL REGISTERS)

19

18

17

16

15

14

13

12

11

9

5

Specifications GAL18V10B

Absolute Maximum Ratings

Supply voltage VCC....................................... -0.5 to +7V

Input voltage applied ...........................-2.5 to VCC +1.0V

Off-state output voltage applied ..........-2.5 to VCC +1.0V

Storage Temperature .................................-65 to 150°C

(1)

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) .............................0 to +75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient T emperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.

3

MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 —— V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 —–130 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15/-20 — 75 1 15 mA

Supply Current f

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) Typical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

6

AC Switching Characteristics

Specifications GAL18V10B

Over Recommended Operating Conditions

COM COM COM

-10

MIN. MAX.

-15

MIN. MAX.

-20

MIN. MAX.

PARAM.

TEST

COND.

DESCRIPTION

1

COM

-7

MIN. MAX.

tpd A Input or I/O to Comb. Output — 7.5 — 10 — 15 — 20 ns
tco A Clock to Output Delay — 5.5 — 7 — 10 — 12 ns

2

tcf

— Clock to Feedback Delay — 3.5 — 3.5 — 7 — 10 ns

tsu — Setup Time, Input or Fdbk before Clk↑ 5.5 — 6 — 8 — 12 — ns

th — Hold Time, Input or Fdbk after Clk ↑ 0 — 0 — 0 — 0 — ns

A Maximum Clock Frequency with 90.9 — 76.9 — 55.5 — 41.6 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 1 11 — 105 — 66.7 — 45.4 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 1 11 — 105 — 66.7 — 62.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 4 — 4 — 6 — 8 — ns

twl — Clock Pulse Duration, Low 4 — 4 — 6 — 8 — ns

ten B Input or I/O to Output Enabled — 8 — 10 — 15 — 20 ns

tdis C Input or I/O to Output Disabled — 8 — 9 — 15 — 20 ns

UNITS

tar A Input or I/O to Asynch. Reset of Reg. — 13 — 13 — 20 — 20 ns

tarw — Asynch. Reset Pulse Duration 8 — 8 — 10 — 15 — ns

tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 8 — 10 — 15 — ns
tspr — Synch. Preset to Clk↑ Recovery T ime 10 — 10 — 10 — 12 — ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 8 pF VCC = 5.0V , V

= 2.0V

I/O

7

Specifications GAL18V10

Absolute Maximum Ratings

(1)

Supply voltage VCC....................................... -0.5 to +7V

Input voltage applied ...........................-2.5 to VCC +1.0V

Off-state output voltage applied ..........-2.5 to VCC +1.0V

Storage Temperature .................................-65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) .............................0 to +75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient T emperature with

Power Applied.........................................-55 to 125°C

1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

3

SYMBOL PARAMETER CONDITION MIN. TYP.

MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 ——V

IOL Low Level Output Current ——16 mA
IOH High Level Output Current ——–3.2 mA

2

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –50 —–135 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/-20 — 75 115 mA

Supply Current f

1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

8

AC Switching Characteristics

Specifications GAL18V10

Over Recommended Operating Conditions

COM

PARAMETER UNITS

TEST

COND.

DESCRIPTION

1

-15

MIN. MAX.

COM

-20

MIN. MAX.

tpd A Input or I/O to Combinatorial Output — 15 — 20 ns
tco A Clock to Output Delay — 10 — 12 ns

2

tcf

— Clock to Feedback Delay — 7 — 10 ns

tsu — Setup T ime, Input or Feedback before Clock↑ 10 — 12 — ns

th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns

A Maximum Clock Frequency with 50 — 41.6 — MHz

External Feedback, 1/(tsu +tco)

3

fmax

A Maximum Clock Frequency with 58.8 — 45.4 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 62.5 — 62.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 8 — 8 — ns

twl — Clock Pulse Duration, Low 8 — 8 — ns
ten B Input or I/O to Output Enabled — 15 — 20 ns

tdis C Input or I/O to Output Disabled — 15 — 20 ns

tar A Input or I/O to Asynchronous Reset of Register — 20 — 20 ns

tarw — Asynchronous Reset Pulse Duration 10 — 15 — ns

tarr — Asynchronous Reset to Clock Recovery T ime 15 — 15 — ns
tspr — Synchronous Preset to Clock Recovery Time 10 — 12 — ns

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 8 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 10 pF VCC = 5.0V , V

I/O

= 2.0V

9

(

)

Switching Waveforms

Specifications GAL18V10

INPUT or
I/O FEEDBACK

COMBINA TORIAL
OUTPUT

INPUT or
I/O FEEDBACK

OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

Combinatorial Output

dis

t

t

pd

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

t

su

(exter nal fdbk)

1/ fmax

t

t

co

h

Registered Output

en

t

CLK

1/ fmax (internal fdbk)

cf

t

REGISTERED
FEEDBACK

t

su

CLK

INPUT or
I/O FEEDBACK
DRIVING SP

CLK

REGISTERED
OUTPUT

fmax with Feedback

t

wh

Clock Width

t

su

Synchronous Preset Asynchronous Reset

f

max

1/

w/o fdbk

t

wl

INPUT or
I/O FEEDBACK
DRIVING AR

t

h

t

spr

CLK

t

co

REGISTERED
OUTPUT

t

arw

t

ar

t

arr

10

TEST POINT

C *

L

FROM OUTPUT (O/Q)
UNDER TEST

+5V

*C

L

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

R

2

R

1

fmax Descriptions

Specifications GAL18V10

CLK

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi­natorial output is equal to tcf + tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and -7/-10 2ns 10% – 90%
Fall Times -15/-20 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)

Test Condition R

A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF

C Active High ∞ 390Ω 5pF

1 R2 CL

Active Low 300Ω 390Ω 50pF

Active Low 300Ω 390Ω 5pF

11

Specifications GAL18V10

Electronic Signature

An electronic signature is provided in every GAL18V10 device. It
contains 64 bits of reprogrammable memory that can contain user­defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

Security Cell

A security cell is provided in every GAL18V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de­vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.

Latch-Up Protection

GAL18V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos­sibility of SCR induced latching.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.

The GAL18V10 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors
perform output register preload automatically.

Input Buffers

GAL18V10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.

The input and I/O pins also have built-in active pull-ups. As a result,
floating inputs will float to a TTL high (logic 1). However, Lattice
Semiconductor recommends that all unused inputs and tri-stated
I/O pins be connected to an adjacent active input, Vcc, or ground.
Doing so will tend to improve noise immunity and reduce Icc for the
device.

T ypical Input Current

0

12

-20

-40

Input Current (uA)

-60
0

1.0 2.0 3.0 4.0 5.0

Input Voltage (Volts)

Power-Up Reset

Specifications GAL18V10

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

Vcc (min.)

Circuitry within the GAL18V10 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be­cause of the asynchronous nature of system power-up, some

t

su

t

wl

pr

t

Internal Register
Reset to Logic "0"

Device Pin
Reset to Logic "1"

Device Pin
Reset to Logic "0"

conditions must be met to provide a valid power-up reset of the
device. First, the V

CC rise must be monotonic. Second, the clock

input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

Input/Output Equivalent Schematics

PIN

(Vref Typical = 3.2V)

ESD
Protection
Circuit

PIN

ESD
Protection
Circuit

Active Pull-up
Circuit

Vcc

Vref

T ypical Input T ypical Output

Vcc

Vcc

Data
Output

Feedback

Tri-State
Control

Active Pull-up
Circuit

Vcc

Feedback
(To Input Buffer)

PIN

(Vref Typical = 3.2V)

Vref

PIN

13

Specifications GAL18V10

GAL18V10B: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

PT H->L
PT L->H

-55 -25 0 25 5 0 7 5 100 125

Temperature (deg. C)

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

RISE
FALL

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1

1

0.9

Normalized Tsu

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tpd (ns)

-2
12345678910

Number of Outputs Switching

Delta Tpd vs Output Loading

10

8

6

4

2

0

Delta Tpd (ns)

-2

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tco (ns)

-2
12345678910

Number of Outputs Switching

Delta Tco vs Output Loading

10

8

6

4

2

0

Delta Tco (ns)

-2

-4
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

14

Specifications GAL18V10

GAL18V10B: Typical AC and DC Characteristic Diagrams

Vol vs Iol

1

0.75

0.5

Vol (V)

0.25

0

0 10203040

Iol (mA)

Normalized Icc vs Vcc

1.2

1.1

1

0.9

Normalized Icc

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0 102030405060

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

5.25
5

4.75

4.5

4.25
4

Voh (V)

3.75

3.5

3.25
3

01234

Ioh(mA)

Normalized Icc vs Freq.

1.4

1.3

1.2

1.1

1

Normalized Icc

0.9

0.8
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

8
7
6
5
4
3

Delta Icc (mA)

2
1
0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0

-20

-40

-60

Iik (mA)

-80

-100

-120

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

15

Specifications GAL18V10

GAL18V10B: Typical AC and DC Characteristic Diagrams

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

Normalized Tpd vs. Vcc

PT H -> L
PT L -> H

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

1.3

1.2

1.1

0.9

Normalized Tpd

0.8

0.7

0

Normalized Tpd vs. Temperature

1

-50

0 25 50 75 100 125

-25

Ambient Temperature (°C)

Delta Tpd vs. # of Outputs Switching

1.3

Normalized Tsu vs. Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

PT L -> H

PT H -> L

0.7

4.5 4.75 5 5.25 5.5

Supply Voltage (V)

1.3

1.2

1.1

1

0.9

Normalized Tsu

0.8

0.7

10

Normalized Tsu vs. Temperature

-55 -25 0 25 50 75 100 125

Ambient Temperature (°C)

Delta Tpd vs. Output Loading

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

4.5 4.75 5 5.25 5.5

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

Normalized Tco vs. Vcc

Supply Voltage (V)

Normalized Tco vs. Temperature

Ambient Temperature (°C)

1.3

Normalized Icc vs. Vcc

-1

-2

Delta Tpd (ns)

-3
0

Max. - 8

# of Outputs

250

200

150

IOL vs. V

(mA)

OL

100

I

50

0

012

VOL (V)

Max. - 4

OL

8

6

4

2

Delta Tpd (ns)

0

-2

Max.

0 100 200 300 400

Output Loading Capacitance (pf)

IOH vs. V

-150

-100

OH

(mA)

OH

I

-50

3

0

4

0123

4

VOH (V)

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

4.5 4.75 5 5.25 5.5

1.3

1.2

1.1

1

0.9

Normalized Icc

0.8

0.7

-55 -25 0 25 50 75 100 125

Supply Voltage (V)

Normalized Icc vs. Temperature

Icc vs. Temperature
Isb vs. Temperature

Ambient Temperature (°C)

16