Datasheet GAL16VP8B-25LP, GAL16VP8B-25LJ Datasheet (Lattice Semiconductor Corporation)

GAL16VP8

1

10

11

20

I/CLK

I

I

I

I

I

I

I

I

GND

Vcc

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/OE

5

15

I

I

I

I

I

I

II

CLK

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/CLK

OE

8

8

8

8

8

8

8

8

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

PROGRAMMABLE

AND-ARRAY

(64 X 32)

I

I/OE

High-Speed E2CMOS PLD

Generic Array Logic™

Features

• HIGH DRIVE E2CMOS® GAL® DEVICE
— TTL Compatible 64 mA Output Drive
— 15 ns Maximum Propagation Delay
— Fmax = 80 MHz
— 10 ns Maximum from Clock Input to Data Output
— UltraMOS

• ENHANCED INPUT AND OUTPUT FEATURES
— Schmitt Trigger Inputs
— Programmable Open-Drain or Totem-Pole Outputs
— Active Pull-Ups on All Inputs and I/O pins

2

CELL TECHNOLOGY

• E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Compatible with Standard GAL16V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Ideal for Bus Control & Bus Arbitration Logic
— Bus Address Decode Logic
— Memory Address, Data and Control Circuits
— DMA Control

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

®

Advanced CMOS Technology

Functional Block Diagram

Description

The GAL16VP8, with 64 mA drive capability and 15 ns maximum
propagation delay time is ideal for Bus and Memory control appli­cations. The GAL16VP8 is manufactured using Lattice
Semiconductor's advanced E2CMOS process which combines
CMOS with Electrically Erasable (E

2

) floating gate technology. High
speed erase times (<100ms) allow the devices to be reprogrammed
quickly and efficiently .

System bus and memory interfaces require control logic before
driving the bus or memory interface signals. The GAL16VP8
combines the familiar GAL16V8 architecture with bus drivers as
its outputs. The generic architecture provides maximum design flex­ibility by allowing the Output Logic Macrocell (OLMC) to be con­figured by the user. The 64mA output drive eliminates the need for
additional devices to provide bus driving capability .

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

16vp8_03

Pin Configuration

PLCC

I/CLKII

2

4

I

Vcc

GAL16VP8

I

6

I

I

1

T op View

8

911

I I/O/QII/O/Q I/O/Q

I/OE

DIP

I/O/Q

20

18

I/O/Q

I/O/Q

16

I/O/Q

GND

I/O/Q

14

13

GAL

16VP8

Specifications GAL16VP8

Blank = Commercial

Grade

Package

PowerL = Low Power

Speed (ns)

XXXXXXXX XX X X X

Device Name

_

P = Plastic DIP
J = PLCC

GAL16VP8B

GAL16VP8 Ordering Information

Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package

15 8 10 115 GAL16VP8B-15LP 20-Pin Plastic DIP

115 GAL16VP8B-15LJ 20-Lead PLCC

25 10 15 115 GAL16VP8B-25LP 20-Pin Plastic DIP

115 GAL16VP8B-25LJ 20-Lead PLCC

Part Number Description

2

Output Logic Macrocell (OLMC)

Specifications GAL16VP8

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina­torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft­ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 10 are permanently configured
as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible con­figurations in a GAL16VP8. The information given on these archi­tecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.

In complex mode pin 1 and pin 10 become dedicated inputs and
use the feedback paths of pin19 and pin 1 1 respectively . Because
of this feedback path usage, pin19 and pin 11 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
14 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or open­drain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.

3

Registered Mode

Specifications GAL16VP8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub­sets of the I/O function.

CLK

DQ

XOR

OE

Q

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signa­ture (UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 1 controls common CLK for the registered outputs.

- Pin 10 controls common OE for the registered outputs.

- Pin 1 & Pin 10 are permanently configured as CLK & OE
for registered output configuration.

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 1 & Pin 10 are permanently configured as CLK & OE
for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL16VP8

DIP and PLCC Package Pinouts

1

0000

0224

0256

0480

2

0512

0736

3

0768

0992

4

2128

2824201612840

PTD

20

OLMC

XOR-2048
AC1-2120
AC2-2194

19

OLMC

XOR-2049
AC1-2121
AC2-2195

18

OLMC

XOR-2050
AC1-2122
AC2-2196

17

OLMC

XOR-2051
AC1-2123
AC2-2197

16

6

7

8

9

MSB LSB

1024

1248

1280

1504

1536

1760

1792

2016

2191

64-USER ELECTRONIC SIGNATURE FUSES

2056, 2055, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

OLMC

XOR-2052
AC1-2124
AC2-2198

OLMC

XOR-2053
AC1-2125
AC2-2199

OLMC

XOR-2054
AC1-2126
AC2-2200

OLMC

XOR-2055
AC1-2127
AC2-2201

SYN-2192
AC0-2193

OE

14

13

12

11

10

5

Complex Mode

Specifications GAL16VP8

In the Complex mode, macrocells are configured as output only or
I/O functions.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 1 1 & 19) do not have input capability. De­signs requiring eight I/Os can be implemented in the Registered
mode.

XOR

All macrocells have seven product terms per output. One prod­uct term is used for programmable output enable control. Pins 1
and 10 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no ef fect on this mode.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 12 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1 has no ef fect on this mode.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pin 1 1 and Pin 19 are configured to this function.

6

Complex Mode Logic Diagram

Specifications GAL16VP8

DIP and PLCC Package Pinouts

1

0000

0224

0256

0480

2

0512

0736

3

0768

0992

4

2128

2824201612840

PTD

20

OLMC

XOR-2048
AC1-2120
AC2-2194

19

OLMC

XOR-2049
AC1-2121
AC2-2195

18

OLMC

XOR-2050
AC1-2122
AC2-2196

17

OLMC

XOR-2051
AC1-2123
AC2-2197

16

1024

1248

6

1280

1504

7

1536

1760

8

1792

2016

9

2191

OLMC

XOR-2052
AC1-2124
AC2-2198

OLMC

XOR-2053
AC1-2125
AC2-2199

OLMC

XOR-2054
AC1-2126
AC2-2200

OLMC

XOR-2055
AC1-2127
AC2-2201

14

13

12

11

10

64-USER ELECTRONIC SIGNATURE FUSES

2056, 2055, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

SYN-2192

AC0-2193

MSB LSB

7

Simple Mode

Specifications GAL16VP8

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Vcc

XOR

Pins 1 and 10 are always available as data inputs into the AND
array . The center two macrocells (pins 14 & 16) cannot be used
in the input configuration.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- All OLMC except pins 14 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- Pins 14 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- AC2=1 defines totem pole output.

- AC2=0 defines open-drain output.

- All OLMC except pins 14 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

8

Simple Mode Logic Diagram

Specifications GAL16VP8

DIP and PLCC Package Pinouts

1

24

201612840

0000

0224

0256

0480

2

0512

0736

3

0768

0992

4

1024

6

1248

2128

PTD

28

20

OLMC

XOR-2048
AC1-2120
AC2-2194

19

OLMC

XOR-2049
AC1-2121
AC2-2195

18

OLMC

XOR-2050
AC1-2122
AC2-2196

17

OLMC

XOR-2051
AC1-2123
AC2-2197

16

OLMC

XOR-2052
AC1-2124
AC2-2198

14

1280

1504

7

1536

1760

8

1792

2016

9

2191

OLMC

XOR-2053
AC1-2125
AC2-2199

OLMC

XOR-2054
AC1-2126
AC2-2200

OLMC

XOR-2055
AC1-2127
AC2-2201

13

12

11

10

64-USER ELECTRONIC SIGNA TURE FUSES

2056, 2055, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

SYN-2192
AC0-2193

MSB LSB

9

Specifications GAL16VP8

Absolute Maximum Ratings

(1)

Supply voltage VCC........................................ –.5 to +7V

Input voltage applied .......................... –2.5 to VCC +1.0V

Off-state output voltage applied ......... –2.5 to VCC +1.0V

Storage Temperature ................................–65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ............................... 0 to 75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient Temperature with

Power Applied ........................................... –55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

4

SYMBOL PARAMETER CONDITION MIN. TYP.

MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

1

VI

IIL

Input Clamp Voltage Vcc = Min. IIN = –32mA —–1.2 V

2

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) ——–100 µA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10 µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH ——0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 ——V

IOL Low Level Output Current ——64 mA

IOH High Level Output Current ——–32 mA

3

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –60 —–400 mA

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/-25 — 90 115 mA

Supply Current f

1) Characterized but not 100% tested.

2) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.

4) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15MHz Outputs Open

10

Specifications GAL16VP8

AC Switching Characteristics

Over Recommended Operating Conditions

COM COM

PARAMETER UNITS

TEST

COND1.

DESCRIPTION

-15

MIN. MAX.

tpd A Input or I/O to Combinational Output 3 15 3 25 ns
tco A Clock to Output Delay 2 10 2 15 ns

2

tcf

— Clock to Feedback Delay — 4.5 — 10 ns

tsu — Setup Time, Input or Feedback before Clock↑ 8 — 10 — ns

th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns

A Maximum Clock Frequency with 55.5 — 40 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 80 — 50 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 80 — 50 — MHz

No Feedback

-25

MIN. MAX.

twh — Clock Pulse Duration, High 6 — 10 — ns

twl — Clock Pulse Duration, Low 6 — 10 — ns
ten B Input or I/O to Output Enabled — 15 — 20 ns

B OE to Output Enabled — 12 — 15 ns

tdis C Input or I/O to Output Disabled — 15 — 20 ns

C OE to Output Disabled — 12 — 15 ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL P ARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 10 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 15 pF VCC = 5.0V , V

I/O

= 2.0V

11

(

)

Switching Waveforms

Specifications GAL16VP8

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

t

pd

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

su

t

t

t

1/

f

max

(external fdbk)

h

co

Registered OutputCombinatorial Output

OE

dis

t

en

t

REGISTERED
OUTPUT

OEOE

OE to Output Enable/Disable

OEOE

dis

t

en

t

CLK

wh

t

1/fmax

w/o fb

Clock Width

wl

t

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

fmax with Feedback

su

t

12

fmax Descriptions

Specifications GAL16VP8

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note:

fmax with external feedback is calculated

from measured

LOGIC
ARRAY

t

su + th

tsu and tco.

CLK

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting
feedback (

is used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-

natorial output is equal to

tsu from the period of fmax w/internal

tcf = 1/fmax - tsu). The value of tcf

tcf + tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)

Test Condition R

A 500Ω 500Ω 50pF
B Active High ∞ 500Ω 50pF

Active Low 500Ω 500Ω 50pF

C Active High ∞ 500Ω 5pF

Active Low 500Ω 500Ω 5pF

1 R2 CL

FROM OUTPUT (O/Q)
UNDER TEST

13

+5V

R

1

TEST POINT

C *

R

2

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

*C

L

L

Specifications GAL16VP8

Electronic Signature

An electronic signature word is provided in every GAL16VP8 de­vice. It contains 64 bits of reprogrammable memory that can contain
user defined data. Some uses include user ID codes, revision num­bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Security Cell

The security cell is provided on all GAL16VP8 devices to prevent
unauthorized copying of the array patterns. Once programmed,
the circuitry enabling array is disabled, preventing further program­ming or verification of the array . The cell can only be erased by re­programming the device, so the original configuration can never
be examined once this cell is programmed. Signature data is al­ways available to the user.

Latch-Up

GAL16VP8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally , outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos­sibility of SCR induced latching.

operation, certain events occur that may throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

The GAL16VP8 device includes circuitry that allows each registered

output to be synchronously set either high or low. Thus, any present

state condition can be forced for test sequencing.

If necessary , approved GAL programmers capable of executing test

vectors can perform output register preload automatically.

Input Buffers

GAL16VP8 devices are designed with TTL level compatible input

buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

devices.

GAL16VP8 input buffers have active pull-ups within their input

structure. As a result, unused inputs and I/O's will float to a TTL

"high" (logical "1"). Lattice Semiconductor recommends that all un-

used inputs and tri-stated I/O pins for both devices be connected

to another active input, VCC, or GND. Doing this will tend to improve

noise immunity and reduce ICC for the device.

T ypical Input Pull-up Characteristic

Bulk Erase Mode

During a programming cycle, a clear function performs a bulk erase
of the array and the architecture word. In addition, the electronic
signature word and the security cell are erased. This mode resets
a previously configured device back to its original state, which is
all JEDEC ones.

Scmitt Trigger Inputs

One of the enhancements of the GAL16VP8 for bus interface logic
implementation is input hysteresis. The threshold of the positive
going edge is 1.5V , while the threshold of the negative going edge
is 1.3V. This provides a typical hysteresis of 200mV between
positive and negative transitions of the inputs.

High Drive Outputs

All eight outputs of the GAL16VP8 are capable of driving 64 mA
loads when driving low and 32 mA loads when driving high. Near
symmetrical high and low output drive capability provides small
skews between high-to-low and low-to-high output transitions.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system

0

-20

-40

Input Current (uA)

-60

1.0 2.0 3.0 4.0 5.0

0

Input Voltage (Volts)

Programmable Open-Drain Outputs

In addition to the standard GAL16V8 type configuration, the out-

puts of the GAL16VP8 are individually programmable either as a

standard totempole output or an open-drain output. The totempole

output drives the specified VOH and VOL levels whereas the open-

drain output drives only the specified VOL. The VOH level on the

open-drain output depends on the external loading and pull-up. This

output configuration is controlled by the AC2 fuse. When AC2 cell

is erased (JEDEC "1") the output is configured as a totempole out-

put and when AC2 cell is programmed (JEDEC "0") the output is

configured as an open-drain. The default configuration when the

device is in bulk erased state is totempole configuration. The AC2

fuses associated with each of the outputs is included in all of the

logic diagrams.

14

Power-Up Reset

Specifications GAL16VP8

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Circuitry within the GAL16VP8 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q out­puts set low after a specified time (

tpr, 1µs MAX). As a result, the

state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown above. Because of the asynchronous nature

Input/Output Equivalent Schematics

tsu

twl

tpr

Internal Register
Reset to Logic "0"

Device P in
Reset to Logic "1"

of system power-up, some conditions must be met to provide a valid

power-up reset of the GAL16VP8. First, the VCC rise must be

monotonic. Second, the clock input must be at static TTL level as

shown in the diagram during power up. The registers will reset

within a maximum of tpr time. As in normal system operation, avoid

clocking the device until all input and feedback path setup times

have been met. The clock must also meet the minimum pulse width

requirements.

PIN

Vref = 3.1V

PIN

ESD
Protection
Circuit

ESD
Protection
Circuit

Active Pull-up

Circuit

Vcc

Vref

Vcc

Vcc

Data
Output

Vref = 3.1V

Feedback

Tri-State
Control

PIN

Active Pull-up
Circuit

Vcc

Vref

PIN

Feedback
(To Input Buffer)

Typical OutputT ypical Input

15

Typical AC and DC Characteristic Diagrams

Specifications GAL16VP8

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

PT H->L
PT L->H

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE

FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55 -25 0 25 5 0 7 5 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

-0.4

Delta Tpd (ns)

-0.5
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

6

4

2

0

Delta Tpd (ns)

-2

0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.25

-0.5

-0.75

-1

Delta Tco (ns)

-1.25
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

6

4

2

0

Delta Tco (ns)

-2

0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

16

Typical AC and DC Characteristic Diagrams

Specifications GAL16VP8

Vol vs Iol

0.5

0.4

0.3

0.2

Vol (V)

0.1

0

0.00 20.00 40.00 60.00 80.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

0.8

Normalized Icc

0.7

-55 -25 0 25 7 5 100 125

Temperature (deg. C)

Voh vs Ioh

4.5

4.25

4

Voh (V)

3.75

3.5

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.40

1.30

1.20

1.10

1.00

Normalized Icc

0.90
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

3

2.5

2

1.5

1

Delta Icc (mA)

0.5

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

17