Datasheet GAL16V8ZD-15QJ, GAL16V8ZD-12QP, GAL16V8ZD-12QJ, GAL16V8Z-15QS, GAL16V8Z-15QP Datasheet (Lattice Semiconductor Corporation)

GAL16V8Z

GAL16V8ZD

Zero Power E2CMOS PLD

Features

• ZERO POWER E2CMOS TECHNOLOGY

• HIGH PERFORMANCE E

•E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

µA Standby Current

— 100
— Input Transition Detection on GAL16V8Z
— Dedicated Power-down Pin on GAL16V8ZD
— Input and Output Latching During Power Down

2

CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS

2

CELL TECHNOLOGY

®

Advanced CMOS Technology

— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL16V8

— 100% Functional Testability

— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing

Functional Block Diagram

I/CLK

I

I

I/DPP

I

I

(64 X 32)

AND-ARRAY

I

I

I

PROGRAMMABLE

8

8

8

8

8

8

8

8

CLK

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I/OE

Description

The GAL16V8Z and GAL16V8ZD, at 100 µA standby current and
12ns propagation delay provides the highest speed and lowest

DESCRIPTION

Pin Configuration

DIP/SOIC

power combination PLD available in the market. The GAL16V8Z/
ZD is manufactured using Lattice Semiconductor's advanced zero
power E

2

CMOS process, which combines CMOS with Electrically

Erasable (E2) floating gate technology .
The GAL16V8Z uses Input Transition Detection (ITD) to put the

device in standby mode and is capable of emulating the full func­tionality of the standard GAL16V8. The GAL16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 15 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,

I/DPP

I
I
I
I

Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

16v8zzd_03

1

PLCC

I

3

4

GAL16V8Z

GAL16V8ZD

6

Top V iew

8

9

I

GND

11

I/CLK

120

I/CLKI

I/O/Q

Vcc

19

1

18

I/O/Q
I/O/Q

16

I/O/Q

I/O/Q
I/O/Q

14

13

I/OE

I/O/Q

I/O/Q

2

I

GAL

I

3

I/DPP

GND

16V8Z

4

16V8ZD

I

5

I

6

I

7

I

8

I

912
10 11

19
18

17
16

15
14
13

Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

I/O/Q
I/O/Q

I/O/Q
I/OE

Specifications GAL16V8Z

GAL16V8ZD

GAL16V8Z/ZD Ordering Information

GAL16V8Z: Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (µA) Ordering # Package

12 10 8 55 100 GAL16V8Z-12QP 20-Pin Plastic DIP

55 100 GAL16V8Z-12QJ 20-Lead PLCC
55 100 GAL16V8Z-12QS 20-Lead SOIC

15 15 10 55 100 GAL16V8Z-15QP 20-Pin Plastic DIP

55 100 GAL16V8Z-15QJ 20-Lead PLCC
55 100 GAL16V8Z-15QS 20-Lead SOIC

GAL16V8ZD: Commercial Grade Specifications

Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Isb (µA) Ordering # Package

12 10 8 55 100 GAL16V8ZD-12QP 20-Pin Plastic DIP

55 100 GAL16V8ZD-12QJ 20-Lead PLCC

15 15 10 55 100 GAL16V8ZD-15QP 20-Pin Plastic DIP

55 100 GAL16V8ZD-15QJ 20-Lead PLCC

Part Number Description

Device Name

GAL16V8Z (Zero Power ITD)

GAL16V8ZD (Zero Power DPP)

Speed (ns)

Active Power

Q = Quarter Power

XXXXXXXX XX X X X

_

Grade

Blank = Commercial

Package

P = Plastic DIP
J = PLCC
S = SOIC

2

Output Logic Macrocell (OLMC)

Specifications GAL16V8Z

GAL16V8ZD

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. T wo global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina­torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft­ware manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.

In registered mode pin 1 and pin 1 1 are permanently configured
as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in­put/output configuration. These two global and 16 individual archi­tecture bits define all possible configurations in a GAL16V8Z/ZD.
The information given on these architecture bits is only to give a
better understanding of the device. Compiler software will trans­parently set these architecture bits from the pin definitions, so the
user should not need to directly manipulate these architecture bits.

In complex mode pin 1 and pin 1 1 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively . Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

When using the standard GAL16V8 JEDEC fuse pattern generated
by the logic compilers for the GAL16V8ZD, special attention must
be given to pin 4 (DPP) to make sure that it is not used as one of
the functional inputs.

3

Registered Mode

Specifications GAL16V8Z

GAL16V8ZD

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/Os are possible in this
mode. Dedicated input or output functions can be implemented
as subsets of the I/O function.

CLK

DQ

XOR

Q

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It
cannot be used as functional input.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1 controls common CLK for the registered outputs.

- Pin 11 controls common OE for the registered outputs.

- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.

OE

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1=1 defines this output configuration.

- Pin 1 & Pin 11 are permanently configured as CLK & OE
for registered output configuration.

4

Registered Mode Logic Diagram

Specifications GAL16V8Z

GAL16V8ZD

DIP, SOIC & PLCC Package Pinouts

1

201612840

24

0000

0224

2

0256

0480

3

0512

0736

4

*

0768

0992

5

1024

1248

6

2128

28

PTD

OLMC

19

XOR-2048
AC1-2120

OLMC

18

XOR-2049
AC1-2121

OLMC

17

XOR-2050
AC1-2122

OLMC

16

XOR-2051
AC1-2123

OLMC

15

XOR-2052
AC1-2124

7

8

9

MSB LSB

1280

1504

1536

1760

1792

2016

2191

64-USER ELECTRONIC SIGNATURE FUSES

2056, 2057, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

OLMC

14

XOR-2053
AC1-2125

OLMC

13

XOR-2054
AC1-2126

OLMC

12

XOR-2055
AC1-2127

OE

11

SYN-2192
AC0-2193

* Note: Input not available on GAL16V8ZD

5

Complex Mode

Specifications GAL16V8Z

GAL16V8ZD

In the Complex mode, macrocells are configured as output only or
I/O functions.

Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 12 & 19) do not have input capability . De­signs requiring eight I/Os can be implemented in the Registered
mode.

XOR

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
1 1 are always available as data inputs into the AND array.

Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can­not be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1 has no effect on this mode.

- Pin 12 and Pin 19 are configured to this
function.

6

Complex Mode Logic Diagram

Specifications GAL16V8Z

GAL16V8ZD

DIP, SOIC & PLCC Package Pinouts

1

24

201612840

0000

0224

2

0256

0480

3

0512

0736

4

*

0768

0992

5

1024

1248

6

2128

PTD

28

OLMC

19

XOR-2048
AC1-2120

OLMC

18

XOR-2049
AC1-2121

OLMC

17

XOR-2050
AC1-2122

OLMC

16

XOR-2051
AC1-2123

OLMC

15

XOR-2052
AC1-2124

7

8

9

MSB LSB

1280

1504

1536

1760

1792

2016

2191

64-USER ELECTRONIC SIGNATURE FUSES

2056, 2057, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

OLMC

14

XOR-2053
AC1-2125

OLMC

13

XOR-2054
AC1-2126

OLMC

12

XOR-2055
AC1-2127

11

SYN-2192

AC0-2193

* Note: Input not available on GAL16V8ZD

7

Simple Mode

Specifications GAL16V8Z

GAL16V8ZD

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge­neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight porduct
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Pins 1 and 11 are always available as data inputs into the AND
array . The center two macrocells (pins 15 & 16) cannot be used
in the input configuration.

Pin 4 is used as dedicated power-down pin on GAL16V8ZD. It can­not be used as functional input.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

Vcc

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 15 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

8

Simple Mode Logic Diagram

Specifications GAL16V8Z

GAL16V8ZD

DIP, SOIC & PLCC Package Pinouts

1

24

201612840

0000

0224

2128

28

PTD

OLMC

XOR-2048
AC1-2120

19

2

0256

0480

OLMC

XOR-2049
AC1-2121

18

3

0512

0736

4

*

0768

0992

OLMC

XOR-2050
AC1-2122

OLMC

XOR-2051
AC1-2123

17

16

5

1024

1248

OLMC

XOR-2052
AC1-2124

15

6

7

8

9

64-USER ELECTRONIC SIGNA TURE FUSES

2056, 2057, .... .... 21 18, 2119

Byte7 Byte6 .... .... Byte1 Byte0

MSB LSB

1280

1504

1536

1760

1792

2016

2191

OLMC

XOR-2053
AC1-2125

14

OLMC

XOR-2054
AC1-2126

13

OLMC

XOR-2055
AC1-2127

SYN-2192

AC0-2193

* Note: Input not available on GAL16V8ZD

12

11

9

Specifications GAL16V8Z

GAL16V8ZD

Absolute Maximum Ratings

(1)

Supply voltage VCC........................................ –.5 to +7V

Input voltage applied .......................... –2.5 to VCC +1.0V

Off-state output voltage applied ......... –2.5 to VCC +1.0V

Storage Temperature ................................ –65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Ambient Temperature with

Power Applied ........................................... –55 to 125°C

1. Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.2MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –10 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10µA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

OH = -100 µA Vin = VIL or VIH Vcc-1 — — V

I

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

1

IOS

Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –150 mA

COMMERCIAL

ISB Stand-by Power VIL = GND VIH = Vcc Outputs Open Z-12/-15 — 50 100 µA

Supply Current ZD-12/-15

ICC Operating Power VIL = 0.5V VIH = 3.0V Z-12/-15 — — 55 mA

Supply Current f

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.

2) T ypical values are at Vcc = 5V and TA = 25 °C

toggle = 15 MHz Outputs Open ZD-12/-15

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

C

I

C

I/O

*Characterized but not 100% tested.

Input Capacitance 10 pF VCC = 5.0V , VI = 2.0V

I/O Capacitance 10 pF VCC = 5.0V , V

10

= 2.0V

I/O

Specifications GAL16V8Z
Specifications GAL16V8Z

AC Switching Characteristics

Over Recommended Operating Conditions

PARAMETER UNITS

TEST

COND1.

tpd A Input or I/O to Combinational Output 3 12 3 15 ns
tco A Clock to Output Delay 2 8 2 10 ns

2

tcf

— Clock to Feedback Delay — 6 — 7 ns

tsu — Setup T ime, Input or Feedback before Clock↑ 10 — 15 — ns

th — Hold Time, Input or Feedback after Clock↑ 0—0—ns

A Maximum Clock Frequency with 55 — 40 — MHz

3

fmax

A Maximum Clock Frequency with 62.5 — 45.5 — MHz

A Maximum Clock Frequency with 83.3 — 62.5 — MHz

DESCRIPTION

MIN. MAX.

External Feedback, 1/(tsu + tco)

Internal Feedback, 1/(tsu + tcf)

No Feedback

GAL16V8ZD

COM

-12

COM

-15

MIN. MAX.

twh — Clock Pulse Duration, High 6 — 8 — ns

twl — Clock Pulse Duration, Low 6 — 8 — ns

ten B Input or I/O to Output Enabled — 12 — 15 ns

B OE to Output Enabled — 12 — 15 ns

tdis C Input or I/O to Output Disabled — 15 — 15 ns

C OE to Output DIsabled — 12 — 15 ns

tas — Last Active Input to Standby 60 140 50 150 ns

4

tsa

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.

4) Add

— Standby to Active Output 6 13 5 15 ns

Standby Power Timing Waveforms

POWER

INPUT or
I/O FEEDBACK

Icc
Isb

tas tpd

tsa

ten,

t

dis

OE

CLK

OUTPUT

11

*

tsu

tco

* Note: Rising clock edges
are allowed during
outputs are not guaranteed.

t

sa but

AC Switching Characteristics

Specifications GAL16V8ZD

Over Recommended Operating Conditions

COM

PARAMETER UNITS

TEST

COND1.

DESCRIPTION

-12

MIN. MAX.

COM

-15

MIN. MAX.

tpd A Input or I/O to Combinational Output 3 12 3 15 ns
tco A Clock to Output Delay 2 8 2 10 ns

2

tcf

— Clock to Feedback Delay — 6 — 7ns

tsu — Setup T ime, Input or Feedback before Clock↑ 10 — 15 — ns

th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — ns

A Maximum Clock Frequency with 55 — 40 — MHz

External Feedback, 1/(tsu + tco)

3

fmax

A Maximum Clock Frequency with 62.5 — 45.5 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 83.3 — 62.5 — MHz

No Feedback

twh — Clock Pulse Duration, High 6 — 8 — ns

twl — Clock Pulse Duration, Low 6 — 8 — ns

ten B Input or I/O to Output Enabled — 12 — 15 ns

B OE to Output Enabled — 12 — 15 ns

tdis C Input or I/O to Output Disabled — 15 — 15 ns

C OE to Output Disabled — 12 — 15 ns

1) Refer to Switching T est Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Specification section.

3) Refer to fmax Specification section.

12

Dedicated Power-Down Pin Specifications

Over Recommended Operating Conditions

Specifications GAL16V8ZD

COM

PARAMETER UNITS

TEST

COND1.

DESCRIPTION

-12

MIN. MAX.

COM

-15

MIN. MAX.

twhd — DPP Pulse Duration High 12 — 15 — ns

twld — DPP Pulse Duration Low 25 — 30 — ns

ACTIVE TO STANDBY

tivdh — Valid Input before DPP High 5 — 8 — ns
tgvdh — Valid OE before DPP High 0 — 0 — ns
tcvdh — V alid Clock Before DPP High 0 — 0 — ns

tdhix — Input Don't Care after DPP High — 2 — 5ns
tdhgx — OE Don't Care after DPP High — 6 — 9ns
tdhcx — Clock Don't Care after DPP High — 8 — 11 ns

ST ANDBY T O ACTIVE

tdliv — DPP Low to V alid Input 12 — 15 — ns
tdlgv — DPP Low to Valid OE 16 — 20 — ns
tdlcv — DPP Low to V alid Clock 18 — 20 — ns
tdlov A DPP Low to Valid Output 5 24 5 30 ns

1) Refer to Switching T est Conditions section.

Dedicated Power-Down Pin Timing Waveforms

DPP

t

ivdh

INPUT or
I/O FEEDBACK

t

gvdh

OE

t

cvdh

CLK

co

t

OUTPUT

t

dhix

t

dhgx

t

dhcx

t

pd,ten,tdis

t

t

dlov

dlcv

t

dliv

t

dlgv

13

(

)

Switching Waveforms

Specifications GAL16V8Z

GAL16V8ZD

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

Input or I/O to Output Enable/Disable

VALID INPUT

t

pd

Combinatorial Output

dis

t

wh

t

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

su

t

t

t

1/

f

max

(external fdbk)

h

co

Registered Output

en

t

OE

en

t

REGISTERED
OUTPUT

dis

t

OE to Output Enable/Disable

wl

t

CLK

1/fmax

w/o fb

Clock Width

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

fmax with Feedback

su

t

14

fmax Descriptions

Specifications GAL16V8Z

GAL16V8ZD

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from

measured tsu and tco.

CLK

LOGIC
ARRAY

t

su + th

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh

+ twl). This is to allow for a clock duty cycle of other
than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting
tsu from the period of fmax w/internal feedback (tcf

= 1/fmax - tsu). The value of tcf is used primarily
when calculating the delay from clocking a register
to a combinatorial output (through registered feed­back), as shown above. For example, the timing
from clock to a combinatorial output is equal to tcf
+ tpd.

Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

Output Load Conditions (see figure)

Test Condition R1 R2 CL

A 300Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF

Active Low 300Ω 390Ω 50pF

C Active High ∞ 390Ω 5pF

Active Low 300Ω 390Ω 5pF

15

+5V

R

1

FROM OUTPUT (O/Q)
UNDER TEST

R

2

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

*C

L

C *

L

TEST POINT

Specifications GAL16V8Z

GAL16V8ZD

Electronic Signature

An electronic signature word is provided in every GAL16V8Z/ZD
device. It contains 64 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se­curity cell.

NOTE: The electronic signature is included in checksum calcu­lations. Changing the electronic signature will alter checksum.

Security Cell

A security cell is provided in the GAL16V8Z/ZD devices to pre­vent unauthorized copying of the array patterns. Once pro­grammed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-program­ming the device, so the original configuration can never be ex­amined once this cell is programmed. The electronic signature
data is always available to the user, regardless of the state of this
security cell.

Device Programming

GAL devices are programmed using a Lattice Semiconductor­approved Logic Programmer, available from a number of manu­facturers (see the Development T ools Section of the Data Book).
Complete programming of the device takes only a few seconds.
Erasing of the device is transparent to the user, and is done au­tomatically as part of the programming cycle.

Input Transition Detection (ITD)

The GAL16V8Z relies on its internal input detection circuitry to
put the device in to power down mode. If there is no input tran­sition for the specified period of time, the device will go into the
power down state. Any valid input transition will put the device
back into the active state. The first rising clock transition from
power-down state only acts as a wake up signal to the device and
will not clock the data input through to the output (refer to standby
power timing waveform for more detail). Any input pulse widths
greater than 5ns at input voltage level of 1.5V will be detected as
input transition. The device will not detect any input pulse widths
less than 1ns measured at input voltage level of 1.5V as an in­put transition.

Dedicated Power-Down Pin

The GAL16V8ZD uses pin 4 as the dedicated power-down signal
to put the device in to the power-down state. DPP is an active high
signal where a logic high driven on this signal puts the device into
power-down state. Input pin 4 cannot be used as a functional input
on this device.

Output Register Preload

When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi­tions.

The GAL16V8Z/ZD devices includes circuitry that allows each reg­istered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically .

Input Buffers

GAL16V8Z/ZD devices are designed with TTL level compatible

INPUT BUFFERS

input buffers. These buffers, with their characteristically high im­pedance, load driving logic much less than traditional bipolar de­vices. This allows for a greater fan out from the driving logic.

GAL16V8Z/ZD input buffers have latches within the buffers. As
a result, when the device goes into standby mode the inputs will
be latched to its values prior to standby . In order to overcome the
input latches, they will have to be driven by an external source.
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins for both devices be connected to another ac­tive input, VCC, or GND. Doing this will tend to improve noise im­munity and reduce ICC for the device.

Typical Input Characteristic

40
30
20

A)

µ

10

0

-10

-20

Input Current (

-30

-40
012345

Input Voltage (Volts)

16

Power-Up Reset

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

Vcc (min.)

Specifications GAL16V8Z

GAL16V8ZD

t

su

t

wl

t

pr

Internal Register
Reset to Logic "0"

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Circuitry within the GAL16V8Z/ZD provides a reset signal to all
registers during power-up. All internal registers will have their
Q outputs set low after a specified time (tpr , 1µs MAX). As a result,

the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the

Input/Output Equivalent Schematics

PIN

Vcc

ESD

Vcc

Protection
Circuit

Vcc

Device P in
Reset to Logic "1"

asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the GAL16V8Z/ZD.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of

tpr time. As in

normal system operation, avoid clocking the device until all in­put and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

PIN

Feedback

Tri-State

Vcc

Control

PIN

Data
Output

ESD
Protection
Circuit

T ypical Input Typical Output

17

PIN

Feedback
(To Input Buffer)

Typical AC and DC Characteristics

Specifications GAL16V8Z

GAL16V8ZD

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

-55

-25

PT H->L
PT L->H

0

25

50

75

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

Temperature (deg. C)

PT H->L
PT L->H

100

125

Normalized Tco vs Vcc

1.2

1.1

1

0.9

Normalized Tco

0.8

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Normalized Tco vs Temp

1.3

-25

RISE
FALL

0

25

50

75

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55

Temperature (deg. C)

RISE

FALL

100

125

Normalized Tsu vs Vcc

1.4

1.3

1.2

1.1

1

Normalized Tsu

0.9

0.8

4.50 4.75 5.00 5.25 5.50

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.4

1.3

1.2

1.1
1

0.9

Normalized Tsu

0.8

0.7

-55

-25

PT H->L
PT L->H

0

25

50

75

Temperature (deg. C)

100

125

Delta Tpd vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tpd (ns)

-2
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

10

8

6

4

2

Delta Tpd (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.5

-1

-1.5

Delta Tco (ns)

-2
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

10

8

6

4

2

Delta Tco (ns)

0

-2
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

18

Typical AC and DC Characteristics

Specifications GAL16V8Z

GAL16V8ZD

Vol vs Iol

1.5

1.25

1

0.75

Vol (V)

0.5

0.25

0

0.00 20.00 40.00 60.00

Iol (mA)

Normalized Icc vs Vcc

1.30

1.20

1.10

1.00

0.90

Normalized Icc

0.80

0.70

4.50 4.75 5.00 5.25 5.50

Supply Voltage (V)

Voh vs Ioh

5

4

3

2

Voh (V)

1

0

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 7 5 10 0 125

Temperature (deg. C)

Voh vs Ioh

5

4.5

4

3.5

Voh (V)

3

2.5

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq. (DPP

& ITD > 10MHz)

1.30

1.20

1.10

1.00

0.90

Normalized Icc

0.80
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

5

4

3

2

Delta Icc (mA)

1

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-1.00 -0.80 -0.60 -0.40 -0.20 0.00

Vik (V)

Normalized Icc vs Freq. (ITD)

1

0.8

0.6

0.4

Normalized Icc

0.2

0

1 10 100 1000 10000

Frequency (KHz)

19