Datasheet GAL16LV8D-5LJ, GAL16LV8D-3LJ, GAL16LV8C-7LJ, GAL16LV8C-15LJ, GAL16LV8C-10LJ Datasheet (Lattice Semiconductor Corporation)

New 5V

Tolerant

Inputs on
16LV8D

GAL16LV8

Low V oltage E2CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS

• 3.3V LOW VOL TAGE 16V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices

(GAL16LV8C)

• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)

2

CELL TECHNOLOGY

•E
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability

• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade

• ELECTRONIC SIGNA TURE FOR IDENTIFICATION

®

Advanced CMOS Technology

Functional Block Diagram

I/CLK

I

I

I

I

I

(64 X 32)

AND-ARRAY

I

I

I

PROGRAMMABLE

8

8

8

8

8

8

8

8

CLK

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

OE

I/OE

Description

The GAL16LV8D, at 3.5 ns maximum propagation delay time,

Pin Configuration

PLCC

provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E

2

CMOS process, which com-

bines CMOS with Electrically Erasable (E2) floating gate technology.

4

I

I/CLKII

Vcc

I/O/Q

2

20

18

I/O/Q

High speed erase times (<100ms) allow the devices to be repro­grammed quickly and efficiently .

The 3.3V GAL16LV8 uses the same industry standard 16V8 archi­tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.

I

6

I

GAL16LV8

T op View

I

16

I/O/Q

I/O/Q

I/O/Q

Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function­ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 1997
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com

16lv8_04

1

8

I

9

I GND

11 13

I/O/Q I/O/Q

I/OE

14

I/O/Q

GAL16LV8 Ordering Information

Commercial Grade Specifications

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.335.207JL3-D8VL61LAGCCLPdaeL-02

543 07JL5-D8VL61LAGCCLPdaeL-02

5.76556JL7-C8VL61LAGCCLPdaeL-02
017756JL01-C8VL61LAGCCLPdaeL-02
51210156JL51-C8VL61LAGCCLPdaeL-02

Part Number Description

XXXXXXXX XX X X X

_

Specifications GAL16LV8

GAL16LV8D
GAL16LV8C

Device Name

Speed (ns)

PowerL = Low Power

Grade

Package

Blank = Commercial

J = PLCC

2

Output Logic Macrocell (OLMC)

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom­plished by development software/hardware and is completely trans­parent to the user.

There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
are illustrated in the following pages. Two global bits, SYN and
AC0, control the mode configuration for all macrocells. The XOR
bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls
the input/output configuration. These two global and 16 individ­ual architecture bits define all possible configurations in a
GAL16LV8. The information given on these architecture bits is only
to give a better understanding of the device. Compiler software will
transparently set these architecture bits from the pin definitions, so
the user should not need to directly manipulate these architecture
bits.

The following is a list of the P AL architectures that the GAL16LV8
can emulate. It also shows the OLMC mode under which the
GAL16LV8 emulates the PAL architecture.

Specifications GAL16LV8

PAL Architectures GAL16LV8

Emulated by GAL16L V8 Global OLMC Mode

16R8 Registered
16R6 Registered

16R4 Registered
16RP8 Registered
16RP6 Registered
16RP4 Registered

16L8 Complex

16H8 Complex

16P8 Complex

10L8 Simple

12L6 Simple

14L4 Simple

16L2 Simple

10H8 Simple

12H6 Simple

14H4 Simple

16H2 Simple

10P8 Simple

12P6 Simple

14P4 Simple

16P2 Simple

Compiler Support for OLMC

Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft­ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.

When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 1 1 are permanently configured

Registered Complex Simple Auto Mode Select

ABEL P16V8R P16V8C P16V8AS P16V8
CUPL G16V8MS G16V8MA G16V8AS G16V8
LOG/iC GAL16V8_R GAL16V8_C7 GAL16V8_C8 GAL16V8
OrCAD-PLD "Registered"
PLDesigner P16V8R

1

2

"Complex"

P16V8C

TANGO-PLD G16V8R G16V8C G16V8AS

as clock and output enable, respectively . These pins cannot be con­figured as dedicated inputs in the registered mode.

In complex mode pin 1 and pin 1 1 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively . Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.

In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.

1

2

"Simple"
P16V8C

1

2

3

GAL16V8A

P16V8A

G16V8

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

3

Registered Mode

Specifications GAL16LV8

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.

Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity , I/O and register placement.

All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.

CLK

DQ

XOR

Q

Dedicated input or output functions can be implemented as sub­sets of the I/O function.

Registered outputs have eight product terms per output. I/Os have
seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product T erm Disable (PTD) fuses, are shown
on the logic diagram on the following page.

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1 controls common CLK for the registered outputs.

- Pin 1 1 controls common OE for the registered outputs.

- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.

OE

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- AC1=1 defines this output configuration.

- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.

4

Registered Mode Logic Diagram

1

0000

0224

2

0256

0480

3

0512

0736

4

0768

0992

5

PLCC Package Pinout

2128

28

201612840

24

PTD

Specifications GAL16LV8

OLMC

XOR-2048
AC1-2120

OLMC

XOR-2049
AC1-2121

OLMC

XOR-2050
AC1-2122

OLMC

XOR-2051
AC1-2123

19

18

17

16

1024

OLMC

1248

6

1280

XOR-2052
AC1-2124

OLMC

1504

7

1536

XOR-2053
AC1-2125

OLMC

1760

8

1792

XOR-2054
AC1-2126

OLMC

2016

9

2191

XOR-2055
AC1-2127

OE

15

14

13

12

11

SYN-2192
AC0-2193

5

Complex Mode

In the Complex mode, macrocells are configured as output only or
I/O functions.

Specifications GAL16LV8

signs requiring eight I/Os can be implemented in the Registered
mode.

Architecture configurations available in this mode are similar to the
common 16L8 and 16P8 devices with programmable polarity in
each macrocell.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 12 & 19) do not have input capability . De-

XOR

All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
1 1 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 13 through Pin 18 are configured to this function.

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 12 and Pin 19 are configured to this function.

6

Complex Mode Logic Diagram

1

0000

0224

2

0256

0480

3

0512

0736

4

0768

0992

5

PLCC Package Pinout

2128

24

201612840

PTD

28

Specifications GAL16LV8

OLMC

XOR-2048
AC1-2120

OLMC

XOR-2049
AC1-2121

OLMC

XOR-2050
AC1-2122

OLMC

XOR-2051
AC1-2123

19

18

17

16

1024

OLMC

1248

6

1280

XOR-2052
AC1-2124

OLMC

1504

7

1536

XOR-2053
AC1-2125

OLMC

1760

8

1792

XOR-2054
AC1-2126

OLMC

2016

9

XOR-2055
AC1-2127

15

14

13

12

11

2191

SYN-2192
AC0-2193

7

Simple Mode

Specifications GAL16LV8

In the Simple mode, macrocells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.

Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge­neric output polarity or input choices.

All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has pro­grammable polarity .

Vcc

XOR

Vcc

XOR

Pins 1 and 11 are always available as data inputs into the AND
array . The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.

The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.

Combinatorial Output with Feedback Configuration
for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

Combinatorial Output Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this configuration.

- Pins 15 & 16 are permanently configured to this
function.

Dedicated Input Configuration for Simple Mode

- SYN=1.

- AC0=0.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this configuration.

- All OLMC except pins 15 & 16 can be configured to
this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

8

Simple Mode Logic Diagram

1

0000

0224

2

PLCC Package Pinout

24

201612840

28

PTD

Specifications GAL16LV8

2128

OLMC

XOR-2048
AC1-2120

19

0256

0480

OLMC

XOR-2049
AC1-2121

18

3

0512

0736

OLMC

XOR-2050
AC1-2122

17

4

0768

0992

OLMC

XOR-2051
AC1-2123

16

5

1024

1248

OLMC

XOR-2052
AC1-2124

15

6

1280

1504

OLMC

XOR-2053
AC1-2125

14

7

1536

1760

OLMC

XOR-2054
AC1-2126

13

8

1792

2016

9

2191

OLMC

XOR-2055
AC1-2127

12

11

SYN-2192
AC0-2193

9

Specifications GAL16LV8D

Absolute Maximum Ratings

(1)

Supply voltage VCC................................... –0.5 to +4.6V

Input voltage applied ................................ –0.5 to +5.6V

I/O voltage applied ................................... –0.5 to +4.6V

Off-state output voltage applied ............... –0.5 to +4.6V

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ......................... +3.0 to +3.6V

Storage Temperature ................................–65 to 150°C

Ambient Temperature with

Power Applied........................................–55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

3

SYMBOL PARAMETER CONDITION MIN. TYP.

MAX. UNITS

VIL Input Low Voltage Vss – 0.3 — 0.8 V

VIH Input High Voltage 2.0 — 5.25 V

I/O High Voltage 2.0 — Vcc+0.5 V

1

IIL

Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA

IIH Input or I/O High Leakage Current (Vcc-0.2)V ≤ VIN ≤ VCC ——10µA

Input High Leakage Current Vcc ≤ VIN ≤ 5.25V — — 10 µA
I/O High Leakage Current Vcc ≤ VIN ≤ 4.6V — — 20 mA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V

IOL = 500µA Vin = VIL or VIH — — 0.2 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOH = -100µA Vin = VIL or VIH Vcc-0.2V — — V

IOL Low Level Output Current — — 8 mA

IOH High Level Output Current — — –8 mA

2

IOS

Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA= 25°C –15 — –80 mA

COMMERCIAL

ICC Operating Power VIL = 0V VIH = 3.0V Unused Inputs at VIL —4570mA

Supply Current f

toggle = 1MHz Outputs Open

1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.

2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.

3) T ypical values are at Vcc = 3.3V and TA = 25 °C

10

Specifications GAL16LV8D

AC Switching Characteristics

Over Recommended Operating Conditions

COMCOM

-3

MIN. MAX.

tpd
tco

tcf

TEST

COND

2

2

3

A Input or I/O to Combinational Output 1 3.5 1 5 ns
A Clock to Output Delay 1 2.5 1 3 ns

— Clock to Feedback Delay — 2 — 2 ns

DESCRIPTION

1

.

tsu — Setup Time, Input or Feedback before Clock↑ 3—4 — ns

th — Hold Time, Input or Feedback after Clock↑ 0—0 — ns

A Maximum Clock Frequency with 180 — 142.8 — MHz

External Feedback, 1/(tsu + tco)

4

fmax

twh

twl

4

4

A Maximum Clock Frequency with 200 — 166 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 250 — 166 — MHz

No Feedback

— Clock Pulse Duration, High 2 — 3 — ns
— Clock Pulse Duration, Low 2 — 3 — ns

-5

MIN. MAX.

UNITSPARAMETER

ten B Input or I/O to Output Enabled — 4.5 — 6 ns

B OE to Output Enabled — 3.5 — 5 ns

tdis C Input or I/O to Output Disabled — 4.5 — 6 ns

C OE to Output Disabled — 3.5 — 5 ns

1) Refer to Switching Test Conditions section.

2) Minimum values for tpd and tco are not 100% tested but established by characterization.

3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

4) Refer to fmax Descriptions section. Characterized but not 100% tested.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C

I

C

I/O

Input Capacitance 5 pF VCC = 3.3V , VI = 0V

I/O Capacitance 5 pF VCC = 3.3V , V

I/O

= 0V

11

Specifications GAL16LV8C

Absolute Maximum Ratings

(1)

Supply voltage VCC................................... –0.5 to +5.6V

Input voltage applied ................................ –0.5 to +5.6V

Off-state output voltage applied ............... –0.5 to +5.6V

Storage Temperature ................................–65 to 150°C

Recommended Operating Conditions

Commercial Devices:

Ambient T emperature (TA) ...............................0 to 75°C

Supply voltage (VCC)

with Respect to Ground ......................... +3.0 to +3.6V

Ambient Temperature with

Power Applied........................................–55 to 125°C

1.Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

SYMBOL PARAMETER CONDITION MIN. TYP.

2

MAX. UNITS

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — 5.25 V

IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA

IIH Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC ——10µA

VCC ≤ VIN ≤ 5.25V ——30mA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V

IOL = 500 µA Vin = VIL or VIH — — 0.2 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

OH = -500 µA Vin = VIL or VIH Vcc-0.45 — — V

I
IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V

IOL Low Level Output Current — — 8 mA

IOH High Level Output Current — — -4 mA

1

IOS

Output Short Circuit Current VCC = 3.3V VOUT = 0.5V TA = 25°C -10 — -60 mA

COMMERCIAL

ICC Operating Power VIL = 0.0V VIH = 3.0V — 45 65 mA

Supply Current f

1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.

2) Typical values are at Vcc = 3.3V and T

toggle = 1MHz Outputs Open

A = 25 °C

12

Specifications GAL16LV8C

AC Switching Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

COMCOMCOM

tpd
tco

tcf

2

3

2

TEST

COND1.

A Input or I/O to Combinational Output 1 7.5 1 10 1 15 ns
A Clock to Output Delay 1 5 1 7 1 10 ns

— Clock to Feedback Delay — 4 — 5 — 8 ns

DESCRIPTION

-7

MIN. MAX.

-10

MIN. MAX.

tsu — Setup Time, Input or Feedback before Clock↑ 6— 7—12—ns

th — Hold Time, Input or Feedback after Clock↑ 0— 0— 0 — ns

A Maximum Clock Frequency with 90.9 — 71.4 — 45.5 — MHz

External Feedback, 1/(tsu + tco)

4

fmax

A Maximum Clock Frequency with 100 — 83.3 — 50 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 100 — 83.3 — 62.5 — MHz

No Feedback

-15

MIN. MAX.

UNITSPARAMETER

twh — Clock Pulse Duration, High 5 — 6 — 8 — ns

twl — Clock Pulse Duration, Low 5 — 6 — 8 — ns

ten B Input or I/O to Output Enabled — 9 — 10 — 15 ns

B OE to Output Enabled — 6 — 8 — 15 ns

tdis C Input or I/O to Output Disabled — 9 — 10 — 15 ns

C OE to Output Disabled — 6 — 8 — 15 ns

1) Refer to Switching T est Conditions section.

2) Minimum values for tpd and tco are not 100% tested but established by characterization.

3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.

4) Refer to fmax Descriptions section. Characterized but not 100% tested.

Capacitance (TA = 25°C, f = 1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C

I

C

I/O

Input Capacitance 8 pF VCC = 3.3V , VI = 0V

I/O Capacitance 8 pF VCC = 3.3V , V

I/O

= 0V

13

(

)

Switching Waveforms

Specifications GAL16LV8

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

INPUT or
I/O FEEDBACK

COMBINATIONAL
OUTPUT

VALID INPUT

t

pd

INPUT or
I/O FEEDBACK

CLK

REGISTERED
OUTPUT

VALID INPUT

su

t

t

t

1/

f

max

(external fdbk)

h

co

Registered OutputCombinatorial Output

OE

dis

t

en

t

REGISTERED
OUTPUT

dis

t

en

t

OE to Output Enable/DisableInput or I/O to Output Enable/Disable

CLK

wh

t

1/fmax

w/o fb

wl

t

CLK

REGISTERED
FEEDBACK

1/fmax (internal fdbk)

cf

t

su

t

Clock Width

fmax with Feedback

14

fmax Descriptions

Specifications GAL16LV8

CLK

LOGIC
ARRAY

t

su

REGISTER

t

co

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is calculated from measured
tsu and tco.

LOGIC
ARRAY

t

su + th

CLK

REGISTER

fmax with No Feedback

Note: fmax with no feedback may be less than 1/(twh + twl). This

is to allow for a clock duty cycle of other than 50%.

CLK

LOGIC
ARRAY

REGISTER

t

cf

t

pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by subtracting tsu from

the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.

15

GAL16LV8D: Switching Test Conditions

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 1.5ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

GAL16LV8D Output Load Conditions (see figure)

Test Condition R

1 CL

A50Ω 35pF
B High Z to Active High at 1.9V 50Ω 35pF

High Z to Active Low at 1.0V 50Ω 35pF

C Active High to High Z at 1.9V 50Ω 35pF

Active Low to High Z at 1.0V 50Ω 35pF

GAL16LV8C: Switching Test Conditions

Specifications GAL16LV8

TEST POINT

FROM OUTPUT (O/Q)
UNDER TEST

*CL INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

0

= 50Ω, CL = 35pF*

Z

+1.45V

R

1

Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 1.5ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active
level.

GAL16LV8C Output Load Conditions (see figure)

T est Condition R

1 R2 CL

A 316Ω 348Ω 35pF
B Active High 316Ω 348Ω 35pF

Active Low 316Ω 348Ω 35pF

C Active High 316Ω 348Ω 5pF

Active Low 316Ω 348Ω 5pF

+3.3V

R 1

FROM OUTPUT (O/Q)
UNDER TEST

R 2

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

*C

L

C *

L

TEST POINT

16

Specifications GAL16LV8

Electronic Signature

An electronic signature is provided in every GAL16L V8 device. It
contains 64 bits of reprogrammable memory that can contain user
defined data. Some uses include user ID codes, revision numbers,
or inventory control. The signature data is always available to the
user independent of the state of the security cell.

NOTE: The electronic signature is included in checksum calcula­tions. Changing the electronic signature will alter the checksum.

Security Cell

A security cell is provided in the GAL16LV8 devices to prevent un­authorized copying of the array patterns. Once programmed, this
cell prevents further read access to the functional bits in the device.
This cell can only be erased by re-programming the device, so the
original configuration can never be examined once this cell is pro­grammed. The Electronic Signature is always available to the user ,
regardless of the state of this control cell.

Latch-Up Protection

GAL16L V8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the

potential of latch-up caused by negative input undershoots.

Device Programming

GAL devices are programmed using a Lattice Semiconductor-ap­proved Logic Programmer, available from a number of manufac­turers. Complete programming of the device takes only a few sec­onds. Erasing of the device is transparent to the user, and is done

automatically as part of the programming cycle.

Output Register Preload

When testing state machine designs, all possible states and state

transitions must be verified in the design, not just those required

in the normal machine operations. This is because, in system

operation, certain events occur that may throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired (i.e.,

illegal) state into the registers. Then the machine can be sequenced

and the outputs tested for correct next state conditions.

GAL16LV8 devices include circuitry that allows each registered

output to be synchronously set either high or low. Thus, any present

state condition can be forced for test sequencing. If necessary,

approved GAL programmers capable of executing text vectors

perform output register preload automatically .

Input Buffers

GAL16LV8 devices are designed with TTL level compatible input

buffers. These buffers have a characteristically high impedance,

and present a much lighter load to the driving logic than bipolar TTL

devices.

The GAL16L V8D input and I/O pins have built-in active pull-ups.

As a result, unused inputs and I/O's will float to a TTL "high" (logical

"1"). Lattice Semiconductor recommends that all unused inputs

and tri-stated I/O pins be connected to another active input, VCC,

or Ground. Doing this will tend to improve noise immunity and re-

duce ICC for the device.

Typical Input Pull-up Characteristic (GAL16LV8D)

17

0

-10

-20

-30

-40

-50

-60

Input Current (µA)

-70

-80
0

1

0.5
Input Voltage (V)

2

1.5

3

2.5

4

3.5

Power-Up Reset

Specifications GAL16LV8

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

FEEDBACK/EXTERNAL

OUTPUT REGISTER

Vcc (min.)

Circuitry within the GAL16LV8 provides a reset signal to all reg­isters during power-up. All internal registers will have their Q

outputs set low after a specified time (

tpr, 1µs MAX). As a result,

the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be­cause of the asynchronous nature of system power-up, some

Input/Output Equivalent Schematics

t

su

t

wl

t

pr

Internal Register
Reset to Logic "0"

Device P in
Reset to Logic "1"

conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during

power up. The registers will reset within a maximum of

tpr time.

As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.

PIN

ESD
Protection
Circuit

PIN

ESD
Protection
Circuit

Typ. V ref = Vcc

Active Pull-up Circuit

(GAL16LV8D Only)

Vcc

Vref

Vcc

T ypical Input

Vcc

Feedback

Tri-State
Control

Data
Output

Typ. V ref = Vcc

Active Pull-up Circuit

(GAL16LV8D Only)

Vcc

Vref

Feedback
(To Input Buffer)

Typical Output

PIN

PIN

18

Specifications GAL16LV8

GAL16LV8D: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.1

1.05

1

0.95

Normalized Tpd

0.9

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

PT H->L
PT L->H

Normalized Tco vs Vcc

1.05

1.025

1

0.975

Normalized Tco

0.95

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tco vs Temp

1.2

1.15

1.1

1.05

1

Normalized Tco

0.95

0.9

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

3.00 3.15 3.30 3.45 3.60

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.25

1.2

1.15

1.1

1.05
1

Normalized Tsu

0.95

0.9

-55 -25 0 25 50 7 5 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0

-0.1

-0.2

-0.3

Delta Tpd (ns)

-0.4
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

22
18
14
10

6
2

Delta Tpd (ns)

-2

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.05

-0.1

-0.15

-0.2

Delta Tco (ns)

-0.25

-0.3
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

22
18
14
10

6
2

Delta Tco (ns)

-2

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

19

Specifications GAL16LV8

GAL16LV8D: Typical AC and DC Characteristic Diagrams

Vol vs Iol

2.25
2

1.75

1.5

1.25
1

Vol (V)

0.75

0.5

0.25
0

0.00 10.00 20.00 30.00 40.00

Iol (mA)

Normalized Icc vs Vcc

1.10

1.05

1.00

0.95

0.90

Normalized Icc

0.85

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Voh vs Ioh

3

2.5

2

1.5

Voh (V)

1

0.5

0

0.00 5.00 10.00 15.00 20.00 25.00

Ioh(mA)

Normalized Icc vs Temp

1.2

1.1

1

0.9

Normalized Icc

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

3

2.95

2.9

Voh (V)

2.85

2.8

0.00 1.00 2.00 3.00 4.00

Ioh(mA)

Normalized Icc vs Freq.

1.05

1.03

1.00

0.98

Normalized Icc

0.95
0 25 50 75 100

Frequency (MHz)

Delta Icc vs Vin (1 input)

10

8

6

4

Delta Icc (mA)

2

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50

Vin (V)

Input Clamp (Vik)

0

5
10
15
20

Iik (mA)

25
30
35

-2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

20

Specifications GAL16LV8

GAL16LV8C: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

1.2

1.1

1

0.9

Normalized Tpd

0.8

3.00 3.15 3.30 3.45 3.60

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tpd vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tpd

0.8

0.7

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Normalized Tco vs Vcc

1.1

1.05

1

0.95

Normalized Tco

0.9

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Normalized Tco vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tco

0.8

0.7

-55 -25 0 25 50 75 100 125

RISE
FALL

Temperature (deg. C)

RISE
FALL

Normalized Tsu vs Vcc

1.2

1.1

1

0.9

Normalized Tsu

0.8

3.00 3.15 3.30 3.45 3.60

PT H->L
PT L->H

Supply Voltage (V)

Normalized Tsu vs Temp

1.3

1.2

1.1

1

0.9

Normalized Tsu

0.8

-55 -25 0 25 50 75 100 125

PT H->L
PT L->H

Temperature (deg. C)

Delta Tpd vs # of Outputs

Switching

0.05
0

-0.05

-0.1

-0.15

-0.2

Delta Tpd (ns)

-0.25

-0.3
12345678

Number of Outputs Switching

Delta Tpd vs Output Loading

34
30
26
22
18
14
10

6

Delta Tpd (ns)

2

-2

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

Delta Tco vs # of Outputs

Switching

0

-0.05

-0.1

-0.15

-0.2

Delta Tco (ns)

-0.25

-0.3
12345678

Number of Outputs Switching

Delta Tco vs Output Loading

34
30
26
22
18
14
10

6

Delta Tco (ns)

2

-2

-6
0 50 100 150 200 250 300

RISE
FALL

Output Loading (pF)

RISE
FALL

21

Specifications GAL16LV8

GAL16LV8C: Typical AC and DC Characteristic Diagrams

Vol vs Iol

1

0.8

0.6

0.4

Vol (V)

0.2

0

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00

Iol (mA)

Normalized Icc vs Vcc

1.20

1.10

1.00

0.90

Normalized Icc

0.80

3.00 3.15 3.30 3.45 3.60

Supply Voltage (V)

Voh vs Ioh

4

3

2

Voh (V)

1

0

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00

Ioh (mA)

Normalized Icc vs Temp

1.3

1.2

1.1

1

Normalized Icc

0.9

0.8

-55 -25 0 25 50 75 100 125

Temperature (deg. C)

Voh vs Ioh

3

2.9

2.8

Voh (V)

2.7

2.6

0.00 1.00 2.00 3.00 4.00

Ioh (mA)

Normalized Icc vs Freq.

1.80

1.60

1.40

1.20

Normalized Icc

1.00
0 255075100

Frequency (MHz)

Delta Icc vs Vin (1 input)

12

10

8

6

4

Delta Icc (mA)

2

0

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50

Vin (V)

Input Clamp (Vik)

0
10
20
30
40
50

Iik (mA)

60
70
80
90

-3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0.00

Vik (V)

22