Datasheet FST3345WMX, FST3345WM, FST3345QSCX, FST3345QSC, FST3345MTCX Datasheet (Fairchild Semiconductor)
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© 1999 Fairchild Semiconductor Corporation DS500019 www.fairchildsemi.com
June 1997
Revised December 1999
FST3345 8-Bit Bus Switch
FST3345
8-Bit Bus Switch
General Description
The Fairchild Switch FST3345 provides 8-bits of highspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as an 8-bit switch bank w ith dual
output enable inpu ts (OE and OE
). When OE is LOW or
OE is HIGH, the switch is ON a nd Port A is connected to
Port B. W hen OE
is HIGH and OE is LOW, the swit ch is
OPEN and a high-impedance sta te exist s between the two
ports.
Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
CC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Diagram
Pin Descriptions
Connection Diagram
Truth T able
Order Number Package Number Package Description
FST3345WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
FST3345QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
FST3345MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name Description
OE, OE
Bus Switch Enables
ABus A
BBus B
Inputs Function
OE OE
X L Connect
H X Connect
L H Disconnect
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FST3345
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 4: Typi c al values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the volta ge drop between A and B pi ns at th e indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
S
) −0.5V to +7.0V
DC Input Voltage (V
IN
) (Note 2) −0.5V to +7.0V
DC Input Diode Current (l
IK
) VIN<0V −50mA
DC Output (I
OUT
) Sink Current 128mA
DC V
CC
/GND Current (ICC/I
GND
) +/− 100mA
Storage Temperature Range (T
STG
) −65°C to +150 °C
Power Supply Operating (V
CC
) 4.0V to 5.5V
Input Voltage (V
IN
)0V to 5.5V
Output Voltage (V
OUT
)0V to 5.5V
Input Rise and Fall Time (t
r
, tf)
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
A
) −40 °C to +85 °C
Symbol Parameter
V
CC
(V)
T
A
= −40 °C to +85 °C
Units Conditions
Min
Typ
(Note 4)
Max
V
IK
Clamp Diode Voltage 4.5 −1.2 V IIN = -18mA
V
IH
HIGH Level Input Voltage 4.0–5.5 2.0 V
V
IL
LOW Level Input Voltage 4.0–5.5 0.8 V
I
I
Input Leakage Current 5.5 ±1.0 µA0≤ VIN ≤5.5V
I
OZ
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V
CC
R
ON
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 5) 4.5 4 7 Ω V
IN
= 0V, IIN = 30mA
4.5 8 15 Ω V
IN
= 2.4V, IIN = 15mA
4.0 11 20 Ω VIN = 2.4V, IIN = 15mA
I
CC
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
OUT
= 0
∆ I
CC
Increase in I
CC
per Input 5.5 2.5 mA One input at 3.4V
Other inputs at VCC or GND
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FST3345
AC Electrical Characteristics
Note 6: This par ameter is guaranteed by desi gn but is not tes t ed. The bus switch contribut es no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 7)
Note 7: TA = +25°C, f = 1 MHz, Ca pacitance is characteriz ed but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR = 1.0 MHz t
W
= 500 nS
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
T
A
= −40 °C to +85 °C,
C
L
= 50 pF, RU = RD = 500Ω
Units Conditions Figure No.
V
CC
= 4.5 − 5.5V VCC = 4.0V
Min Max Min Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6) 0.25 0.25 ns VI = OPEN Figure 1
Figure 2
t
PZH
, t
PZL
Output Enable Time 1.5 6.5 7.0 ns VI = 7V for t
PZL Figure 1
Figure 2
V
I
= OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time 1.0 8.0 8.2 ns VI = 7V for t
PLZ Figure 1
Figure 2
VI = OPEN for t
PHZ
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 4 pF VCC = 5.0V
C
I/O
Input/Output Capacitance 5 pF VCC, OE = 5.0V, OE = 0V
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FST3345
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA20
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FST3345
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide
Package Number MTC20
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
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FST3345 8-Bit Bus Switch
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failure t o perform can be reasonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.
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