Datasheet FST3257QSCX, FST3257QSC, FST3257MX, FST3257MTCX, FST3257MTC Datasheet (Fairchild Semiconductor)

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© 1999 Fairchild Semiconductor Corporation DS500057 www.fairchildsemi.com
September 1997 Revised December 1999
FST3257 Quad 2:1 Multiplexer/Demultiplexer Bus Switch
FST3257 Quad 2:1 Multiplexer/Demultiplexer Bus Switch
General Description
The Fairchild Swi tch FST3257 is a quad 2:1 high-speed CMOS TTL-compatible multiplexer/demultiplexer bus switch. The low on resistance of the switch allows inputs to be connected to outputs wi thout a dding pr opagation delay or generating additional ground bounce noise.
When OE
is LOW, the select pin connects the A Port to the
selected B Port output. When OE
is HIGH, the switch is OPEN and a high-impedance sta te exist s between the two ports.
Features
4 switch connection between two ports.
Minimal propagation delay through the switch.
Low l
CC
.
Zero bounce in flow-through mode.
Control inputs compatible with TTL level.
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Logic Diagram
Pin Descriptions
Connection Diagram
Truth Table
Order Number Package Number Package Description
FST3257M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow FST3257QSC MQA16 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide FST3257MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name Description
OE
Bus Switch Enable S Select Input ABus A
B
1–B2
Bus B
SOE Function
X H Disconnect LL A = B
1
HL A = B
2
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FST3257
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the dev ice cannot be guaranteed. T he device sh ould not be operated at these limit s. The parametric values defin ed in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The Recommende d Opera ting Condit ions table s will de fine the co nditions for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Note 4: Typi c al values are at VCC = 5.0V and TA = +25°C Note 5: Measured by the volta ge drop between A and B pi ns at th e indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (VCC) 0.5V to +7.0V DC Switch Voltage (V
S
) 0.5V to +7.0V
DC Input Voltage (V
IN
)(Note 2) 0.5V to +7.0V
DC Input Diode Current (l
IK
) VIN<0V −50mA
DC Output (I
OUT
) Sink Current 128mA
DC V
CC
/GND Current (ICC/I
GND
) +/ 100mA
Storage Temperature Range (T
STG
) 65°C to +150 °C
Power Supply Operating (V
CC
) 4.0V to 5.5V
Input Voltage (V
IN
)0V to 5.5V
Output Voltage (V
OUT
)0V to 5.5V
Input Rise and Fall Time (t
r
, tf) Switch Control Input 0nS/V to 5nS/V Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
A
) 40 °C to +85 °C
Symbol Parameter
V
CC
(V)
T
A
= 40 °C to +85 °C
Units Conditions
Min
Typ
(Note 4)
Max
V
IK
Clamp Diode Voltage 4.5 −1.2 V IIN = 18mA
V
IH
HIGH Level Input Voltage 4.0–5.5 2.0 V
V
IL
LOW Level Input Voltage 4.0–5.5 0.8 V
I
I
Input Leakage Current 5.5 ±1.0 µA0≤ VIN 5.5V
I
OZ
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V
CC
R
ON
Switch On Resistance 4.5 4 7 VIN = 0V, IIN = 64mA (Note 5) 4.5 4 7 V
IN
= 0V, IIN = 30mA
4.5 8 15 V
IN
= 2.4V, IIN = 15mA
4.0 11 2 0 VIN = 2.4V, IIN = 15mA
I
CC
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
OUT
= 0
I
CC
Increase in I
CC
per Input 5.5 2.5 mA One input at 3.4V
Other inputs at VCC or GND
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FST3257
AC Electrical Characteristics
Note 6: This par ameter is guaranteed by design but is not test e d. T he bus switch con t ributes no pro pagation delay other than the R C delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 7)
Note 7: TA = +25°C, f = 1 MHz, Ca pacitance is characteriz ed but not tested.
AC Loading and Waveforms
Note: Input driven by 50 source terminated in 50 Note: C
L
includes load and stray capacitance
Note: Input PRR = 1.0 MHz, t
W
= 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
T
A
= 40 °C to +85°C,
Units Conditions Figure No.
C
L
= 50 pF, RU = RD = 500
V
CC
= 4.5 – 5.5V VCC = 4.0V
MinMaxMinMax
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6) 0.25 0.25
ns VI = OPEN
Figure 1 Figure 2
Prop Delay, Select to Bus A 1.0 4.7 5.2
t
PZH
, t
PZL
Output Enable Time, Select to Bus B 1.0 5.2 5.7
ns
VI = 7V for t
PZL
Figure 1 Figure 2
Output Enable Time, OE to Bus A, B 1.0 5.1 5.6
V
I
= OPEN for t
PZH
t
PHZ
, t
PLZ
Output Disable Time, Select to Bus B 1.0 5.2 5.5
ns
VI = 7V for t
PLZ
Figure 1 Figure 2
Output Disable Time, Output Enable Time, 1.5 5.5 5.5
VI = OPEN for t
PHZ
OE to Bus A, B
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 3 pF VCC = 5.0V
C
I/O
A Port Input/Output Capacitance 7 pF
VCC, OE = 5.0V
B Port 5 pF
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FST3257
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA16
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FST3257 Quad 2:1 Multiplexer/Demultiplexer Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide
Package Number MTC16
Technology Description
The Fairchild Switch family derives from and embodies Fairchilds proven switch t echnology used for several years in it s 74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the user.
2. A critical componen t in any com ponen t of a life s uppor t device or system whose failure to perform can be rea­sonably expected to cause the failure of the l ife support device or system, or to affect its safety or effectiveness.
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