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FST16861
20-Bit Bus Switch
FST16861 20-Bit Bus Switch
March 2000
Revised March 2000
General Description
The Fairchild Switch FST16861 provides 20-Bits of highspeed CMOS TTL-compatible bus switching. The low ON
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organ ized as a 10-bit or 20-Bit bus switch.
When OE
nected to Port 1B. When OE
to Port 2B. When OE
exists between the A and B Ports.
is LOW, the switch is ON and Port 1A i s con-
1
is LOW, Port 2A is connected
2
is HIGH, a high impedan ce state
X
Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
.
CC
Ordering Code:
Order Number Package Number Package Description
FST16861MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Logic Diagram
Truth Table
Pin Descriptions
Pin Name Description
, OE
OE
1
1A, 2A Bus A
1B, 2B Bus B
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2
Bus Switch Enables
Inputs Inputs/Outputs
OE
LL1A = 1B 2A = 2B
LH1A = 1B Z
HL Z 2A = 2B
HH Z Z
OE
1
2
1A, 1B 2A, 2B
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC)0.5V to +7.0V
DC Switch Voltage (V
FST16861
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) (Note 2) −0.5V to +7.0V
S
) (Note 3) −0.5V to +7.0V
IN
) VIN<0V −50mA
IK
) Current 128mA
) ±100mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the c ondit ions
for actual device operation.
is the voltage observed/applied at either the A or B Ports across
Note 2: V
S
the switch.
Note 3: The input and output negative volt age ratin gs may be exceede d if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held high or low. They may not float.
(Note 4)
CC)
)0V to 5.5V
IN
)0V to 5.5V
OUT
, tf)
r
)-40 °C to +85 °C
A
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
I
CC
∆ I
CC
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by th e v olt age drop between A and B pins at the indicate d c urrent through the switch. On resistance is det erm ined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 6) 4.5 4 7 Ω VIN = 0V, IIN = 30mA
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
per Input 5.5 2.5 mA One input at 3.4V
CC
CC
(V)
0 ±1.0 µAVIN = 5.5V
4.5 7 12 Ω VIN = 2.4V, IIN = 15mA
4.0 11 20 Ω VIN = 2.4V, IIN = 15mA
TA = −40 °C to +85 °C
Min
Typ
(Note 5)
Units Conditions
Max
CC
Other inputs at VCC or GND
4.0V to 5.5V
= 0
OUT
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AC Electrical Characteristics
TA = −40 °C to +85 °C,
Symbol Parameter
t
PHL,tPLH
t
PZH
t
PHZ
Note 7: This parameter is guaranteed by design but is not test ed. The bus switch contrib ut es no propagation delay oth er th an the RC delay of the typical On
resistance of the switc h and the 50pF load cap ac it ance, when driven by a n ideal voltage source (zero output impedance).
Prop Delay Bus-to-Bus (Note 7) 0.25 0.25 ns VI = OPEN Figure 1,
, t
Output Enable Time 1.0 5.0 5.3 ns VI = 7V for t
PZL
, t
Output Disable Time 1.0 6.0 6.3 ns VI = 7V for t
PLZ
CL = 50pF, RU = RD = 500Ω
VCC = 4.5 – 5.5V VCC = 4.0V
Min Max Min Max
Units Conditions Figure No.
Figure 2
PZL Figure 1,
VI = OPEN for t
VI = OPEN for t
Figure 2
PZH
PLZ Figure 1,
Figure 2
PHZ
Capacitance (Note 8)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 8: TA = +25°C, f = 1 Mhz, Capacitance is characterized but not tested.
Control Pin Input Capacitance 3 pF VCC = 5.0V, VIN = 0V
Input/Output Capacitance “OFF State” 6 pF VCC, OE = 5.0V, VIN = 0V
AC Loading and Waveforms
FST16861
Note: Input driven by 50 Ω source terminated in 50Ω
includes load and stray capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, T
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3 www.fairchildsemi.com
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Physical Dimensions inches (millimeters) unless otherwise noted
FST16861 20-Bit Bus Switch
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technolog y used for several years in its
74LVX3L384( FST3384) bus switch product.
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
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2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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