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FST16292
12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch
FST16292 12-Bit to 24-Bit Multiplexer/Demult iplexer Bus Switch
July 1997
Revised December 1999
General Description
The Fairchild Switch FST16 292 provides twelve 2:1 highspeed CMOS TTL-compatible multiplexer/demultiplexer
bus switches. The low on resistance of the switch allows
inputs to be connect ed to out puts wit hout adding prop agation delay or generating additional ground bounce noise.
The select pin connects the A Port to the selected B Port
output. The A
have a 500Ω pull-down resistor to ground.
Ports are not externally connected, thus
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Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
■ Internal 500Ω pull-down resistor on A
.
CC
port.
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Ordering Code:
Order Number Package Number Package Description
FST16292MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16292MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Name Description
SO Data-select input
A
1
B
, B
1
2
© 1999 Fairchild Semiconductor Corporation DS500104 www.fairchildsemi.com
Bus A
Bus B
Truth T able
S0 A1A
LB
HB2B
1B2
2
1
Function
A1 = B1, A2 = B
A1 = B2, A2 = B
2
1
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
FST16292
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) −0.5V to +7.0V
S
) (Note 2) −0.5V to +7.0V
IN
) VIN<0V −50mA
IK
) Sink Current 128mA
) +/− 100mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
IN
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0ns/V to 5ns/V
Switch I/O 0ns/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratings” are those values bey ond which
the safety of the d evice cannot be guaranteed. The device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
CC)
)0V to 5.5V
)0V to 5.5V
OUT
, tf)
r
) −40 °C to +85 °C
A
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
I
CC
∆ I
Note 3: Typi c al values are at VCC = 5.0V and TA =+25°C
Note 4: Measured by the volta ge drop between A an d B pins at the indicated c urrent through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0≤ VIN ≤5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 4) 4.5 4 7 Ω VIN = 0V, IIN = 30mA
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
CC
per Input 5.5 2.5 mA One input at 3.4V
CC
CC
(V)
010µAVIN = 5.5V
4.5 8 12 Ω VIN = 2.4V, IIN = 15mA
4.0 14 20 Ω VIN = 2.4V, IIN = 15mA
TA = −40 °C to +85 °C
Min
Typ
(Note 3)
Max
Units Conditions
CC
Other inputs at VCC or GND
4.0V to 5.5V
= 0
OUT
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AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50pF, RU = RD = 500Ω
Symbol Parameter
L
= 4.5 – 5.5V VCC = 4.0V
V
CC
Units Conditions Figure No.
Min Max Min Max
t
PHL,tPLH
t
PHL,tPLH
t
PZL
t
PLZ
Note 5: This par ameter is guar anteed by design but is not tes t ed. The bus swit c h c ontributes no propagatio n delay other t han the RC delay of the typical On
resistance of the switch and the 50pF load c apacitance, when driven by an ideal voltage source (zero outp ut im pedance).
Prop Delay Bus to Bus (Note 5) 0.25 0.25 ns VI = OPEN Figure 1
Prop Delay S0 to A
, t
Output Enable Time
PZH
S0 to B1 or B
, t
Output Disable Time 1.0 7.5 7.8 ns VI = 7V for t
PHZ
S0 to B
1
or B
1
2
2
1.5 7.0 7.4 ns VI = OPEN Figure 1
1.0 6.7 7.0 ns
VI = 7V for t
VI = OPEN for t
PZL
PLZ
VI = OPEN for t
PZH
PHZ
Figure 2
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Capacitance (Note 6)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 6: TA = +25°C, f = 1 MHz, Ca pacitance is charac te riz ed but not tested.
Control pin Input Capacitance 3 pF VCC = 5.0V
Input/Output Capacitance 10 pF VCC = 5.0V, S0 =GND
AC Loading and Waveforms
FST16292
Note: Input driven by 50 Ω source terminated in 50 Ω
includes load and stray capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
FST16292
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
FST16292 12-Bit to 24-Bit Multiplexer/Demult iplexer Bus Switch
56-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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