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© 2000 Fairchild Semiconductor Corporation DS500319 www.fairchildsemi.com
March 2000
Revised March 2000
FST162861 20-Bit Bus Switch with 25Ω Series Resistors in Outputs
FST162861
20-Bit Bus Switch with 25Ω Series Resistors in Outputs
General Description
The Fairchild Switch FST162861 p rovides 20- Bits of hig hspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organ ized as a 10-bit or 20-Bit bus switch.
When OE
1
is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE
2
is LOW, Port 2A is connected
to Port 2B. When OE
X
is HIGH, a high impedan ce state
exists between the A and B p orts. T he FS T16 2861 h as an
equivalent 25Ω series r esistors to reduce signal-r eflection
noise, eliminating the need for external terminating resistors.
Features
■ 25Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
CC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Descriptions
Logic Diagram
Truth Table
Order Number Package Number Package Description
FST162861MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-1 53, 6.1mm Wide
Pin Name Description
OE
1
, OE
2
Bus Switch Enables
1A, 2A Bus A
1B, 2B Bus B
Inputs Inputs/Outputs
OE
1
OE
2
1A, 1B 2A, 2B
LL1A = 1B 2A = 2B
LH1A = 1B Z
HL Z 2A = 2B
HH Z Z
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FST162861
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 4)
Note 1: The “Absolute Maximum Ratin gs” are those v alues beyon d which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the co ndition s
for actual device operation.
Note 2: V
S
is the voltage observe d/ap plied at eithe r the A or B Port acro ss
the switch.
Note 3: The input and output negative volt age ratin gs may be exceede d if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by th e v olt age drop between A and B pins at the indicated c urrent through the switc h. On resistance is det erm ined by the lower of the
voltages on the two (A or B) pins.
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
S
) (Note 2) −0.5V to +7.0V
DC Input Voltage (V
IN
) (Note 3) −0.5V to +7.0V
DC Input Diode Current (l
IK
) VIN<0V −50mA
DC Output (I
OUT
) Current 128mA
DC V
CC
/GND Current (ICC/I
GND
) ±100mA
Storage Temperature Range (T
STG
) −65°C to +150 °C
Power Supply Operating (V
CC)
4.0V to 5.5V
Input Voltage (V
IN
)0V to 5.5V
Output Voltage (V
OUT
)0V to 5.5V
Input Rise and Fall Time (t
r
, tf)
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
A
)-40 °C to +85 °C
Symbol Parameter
V
CC
(V)
TA = −40 °C to +85 °C
Units Conditions
Min
Typ
(Note 5)
Max
V
IK
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
V
IH
HIGH Level Input Voltage 4.0–5.5 2.0 V
V
IL
LOW Level Input Voltage 4.0–5.5 0.8 V
I
I
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
0 ±1.0 µAVIN = 5.5V
I
OZ
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
CC
R
ON
Switch ON Resistance 4.5 20 26 38 Ω VIN = 0V, IIN = 64mA
(Note 6) 4.5 20 27 40 Ω VIN = 0V, IIN = 30mA
4.5 202848Ω VIN = 2.4V, IIN = 15mA
4.0 203048Ω VIN = 2.4V, IIN = 15mA
I
CC
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
OUT
= 0
∆ I
CC
Increase in I
CC
per Input 5.5 2.5 mA One input at 3.4V
Other inputs at VCC or GND
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FST162861
AC Electrical Characteristics
Note 7: This parameter is guaranteed by design but is not test ed. The bus switch contrib ut es no propagation delay other th an the RC delay of the typical On
resistance of the switc h and the 50pF load cap ac it ance, when driven by an ideal voltage source (z ero output impedance).
Capacitance (Note 8)
Note 8: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50Ω
Note: C
L
includes load and stray capacitance
Note: Input PRR = 1.0 MHz, t
W
= 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
TA = −40 °C to +85 °C,
CL = 50 pF, RU = RD = 500Ω
Units Conditions Figure No.
VCC = 4.5 – 5.5V VCC = 4.0V
Min Max Min Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 7) 1.25 1.25 ns VI = OPEN Figure 1,
Figure 2
t
PZH
, t
PZL
Output Enable Time 1.0 5.3 5.5 ns VI = 7V for t
PZL
Figure 1,
VI = OPEN for t
PZH
Figure 2
t
PHZ
, t
PLZ
Output Disable Time 1.0 6.0 6.3 ns VI = 7V for t
PLZ
Figure 1,
VI = OPEN for t
PHZ
Figure 2
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 3.5 pF VCC = 5.0V, VIN = 0V
C
I/O
Input/Output Capacitance “OFF State” 6.0 pF VCC, OE = 5.0V, VIN = 0V
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FST162861 20-Bit Bus Switch with 25Ω Series Resistors in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology us ed for several years in its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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