Datasheet FST16213MTDX, FST16213MTD, FST16213MEAX, FST16213MEA, FST16213CW Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS500039 www.fairchildsemi.com

July 1997
Revised December 1999

FST16213 24-Bit Bus Exchange Switch

FST16213
24-Bit Bus Exchange Switch

General Description

The Fairchild Switc h FST16213 provides 24-bits of high­speed CMOS TTL-compatible bus switching or exchang­ing. The low on resistance of the swi tch allows inputs to be
connected to outputs without add ing propagation delay or
generating additional ground bounce noise.

The device operate s as a 24-bi t bu s switc h or a 12- bit bus
exchanger, which allows data exchang e between the four
signal ports via the data-select terminals.

Features

■ 4Ω switch connection between two ports.

■ Minimal propagation delay through the switch.

■ Low l

CC

.

■ Zero bounce in flow-through mode.

■ Control inputs compatible with TTL level.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Diagram

Order Number Package Number Package Description

FST16213MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16213MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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FST16213

Connection Diagram Pin Descriptions

Tr uth Table

Pin Name Description

S2, S1, S0 Data-select inputs

A

1

, A

2

Bus A

B

1

, B

2

Bus B

S2 S1 S0 A

1

A

2

Function

L L L Z Z Disconnect
LLH B

1

ZA

1

= B

1

LHL B

2

ZA

1

= B

2

LHH Z B

1

A2 = B

1

HLL Z B

2

A2 = B

2

HLHA2 and B2A1 and B2A1 = A2 = B

2

HHL B

1

B2A1 = B1, A2 = B

2

HHH B

2

B1A1 = B2, A2 = B

1

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FST16213

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

(Note 3)

Note 1: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the dev ice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.

Note 2: The input and output negative voltage ratings may be exceeded if
the input and ou t put diode current ratings ar e observed.

Note 3: Unused contr ol inputs m ust be held high or low. They may not float.

DC Electrical Characteristics

Note 4: Typical values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the

voltages on the two (A or B) pins.

Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V

S

) −0.5V to +7.0V

DC Input Voltage (V

IN

) (Note 2) −0.5V to +7.0V

DC Input Diode Current (l

IK

) VIN<0V −50mA

DC Output (I

OUT

) Sink Current 128mA

DC V

CC

/GND Current (ICC/I

GND

) +/− 100mA

Storage Temperature Range (T

STG

) −65°C to +150 °C

Power Supply Operating (V

CC

) 4.0V to 5.5V

Input Voltage (V

IN

) 0V to 5.5V

Output Voltage (V

OUT

) 0V to 5.5V

Input Rise and Fall Time (t

r

, tf)
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC

Free Air Operating Temperature (T

A

) −40 °C to +85 °C

Symbol Parameter

V

CC

(V)

TA = −40 °C to +85 °C

Units Conditions

Min

Typ

(Note 4)

Max

V

IK

Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA

V

IH

HIGH Level Input Voltage 4.0–5.5 2.0 V

V

IL

LOW Level Input Voltage 4.0–5.5 0.8 V

I

I

Input Leakage Current 5.5 ±1.0 µA0≤ VIN ≤5.5V

010µAV

IN

= 5.5V

I

OZ

OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V

CC

R

ON

Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
A to B or B to A 4.5 4 7 Ω V

IN

= 0V, IIN = 30mA

(Note 5) 4.5 8 12 Ω V

IN

= 2.4V, IIN = 15mA

4.0 11 20 Ω VIN = 2.4V, IIN = 15mA

Switch On Resistance 4.5 10 14 Ω V

IN

= 0V, IIN = 64mA

A1 to A2 4.5 10 14 Ω V

IN

= 0V, IIN = 30mA

(Note 5) 4.5 16 22 Ω VIN = 2.4V, IIN = 15mA

4.0 22 30 Ω V

IN

= 2.4V, IIN = 15mA

I

CC

Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I

OUT

= 0

∆ I

CC

Increase in I

CC

per Input 5.5 2.5 mA One input at 3.4V

Other inputs at VCC or GND

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FST16213

AC Electrical Characteristics

Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On

resistance of the sw it c h and the 50pF load capac i t ance, when driven by an ideal voltage source (zero output impedance) .

Capacitance (Note 7)

Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

AC Loading and Waveforms

Note: Input driven by 50 Ω source terminated in 50 Ω
Note: C

L

includes load and stra y capacitance

Note: Input PRR = 1.0 MHz, t

W

= 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

Symbol Parameter

T

A

= −40 °C to +85 °C,

Units Conditions Figure No.

C

L

= 50pF, RU = RD = 500Ω

V

CC

= 4.5 − 5.5V VCC = 4.0V

Min Max Min Max

t

PHL,tPLH

Prop Delay Bus to Bus (Note 6) 0.25 0.25 ns VI = OPEN Figure 1

Figure 2

t

PHL,tPLH

Prop Delay A1 to A2 0.5 0.5 ns VI = OPEN Figure 1

Figure 2

t

PZH

, t

PZL

Output Enable Time, S to A or B 1.5 7.5 8.0 ns VI = 7V for t

PZL

Figure 1
Figure 2

VI = OPEN for t

PZH

t

PHZ

, t

PLZ

Output Disable Time S to A or B 1.0 8.5 9.0 ns VI = 7V for t

PLZ

Figure 1
Figure 2

V

I

= OPEN for t

PHZ

t

PZH

, t

PZL

Output Enable Time, S0 to A2 and B2 1.5 9.5 10.0 ns VI = 7V for t

PZL

Figure 1
Figure 2

V

I

= OPEN for t

PZH

t

PHZ

, t

PLZ

Output Disable Time, S0 to A2 and B2 1.5 9.0 10.0 ns VI = 7V for t

PLZ

Figure 1
Figure 2

V

I

= OPEN for t

PHZ

Symbol Parameter Typ Max Units Conditions

C

IN

Control pin Input Capacitance 3 pF VCC = 5.0V

C

I/O

Input/Output Capacitance 10 pF VCC = 5.0V

S0, S1, or S2 = GND

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FST16213

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Package Num b er MS56A

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FST16213 24-Bit Bus Exchange Switch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD56

Technology Description

The Fairchild Switch family derives from and embodies Fairchild’s proven s witch technolog y used for several years in i ts
74LVX3L384 (FST3384) bus switch product.

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component in any com ponen t of a life su pport
device or system whose failure t o perform can be rea­sonably expected to ca use the failure of the life supp ort
device or system, or to affect its safety or effectiveness.

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