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查询FST16211供应商
FST16211
24-Bit Bus Switch
FST16211 24-Bit Bus Switch
July 1997
Revised August 2000
General Description
The Fairchild Sw itch FST16211 provides 24-bits of highspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organ ized as a 12-bit or 24-bit b us switch.
When OE
nected to Port 1B. When OE
to Port 2B. Whe n OE
exists between the A and B Ports.
is LOW, the switch is ON and Port 1A is con-
1
is LOW, Port 2A is connected
2
is HIGH, a high impedance state
1/2
Features
■ 4Ω switch connection between two ports
■ Minimal propagation delay through the switch
■ Low l
CC
■ Zero bounce in flow-through mode
■ Control inputs compatible with TTL level
■ Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number Package Number Package Description
FST16211GX
(Note 1)
FST16211MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16211MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Note 1: BGA package available in Tape and Reel only.
BGA54A
Preliminary
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
[TAPE and REEL]
Logic Diagram
© 2000 Fairchild Semiconductor Corporation DS500037 www.fairchildsemi.com
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Connection Diagrams
Pin Assignment for SSOP and TSSOP
FST16211
Pin Assignment for FBGA
Pin Descriptions
Pin Name Description
OE
, OE
1
2
Bus Switch Enables
1A, 2A Bus A
1B, 2B Bus B
FBGA Pin Assignments
123456
A 1A
1A1NC OE21B11B
2
B 1A41A31A7OE11B31B
C 1A61A5GND 1B71B51B
D 1A101A91A81B81B91B
E 1A121A112A12B11B111B
F 2A42A32A22B22B32B
G 2A62A5VCCGND 2B52B
H 2A82A72A112B112B72B
J 2A102A92A122B122B92B
Truth Table
Inputs Inputs/Outputs
OE
1
LL1A
LH1A
HLZ2A
HHZZ
OE
2
1A, 1B 2A, 2B
= 1B 2A = 2B
= 1B Z
2
4
6
10
12
4
6
8
10
= 2B
TOP VIEW
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Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) (Note 3) −0.5V to +7.0V
S
) (Note 4) −0.5V to +7.0V
IN
) V
<0V −50mA
IK
IN
) Sink Current 128mA
) +/− 100mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
Note 2: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the d evice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
is the voltage observed/applied at either A or B Ports across the
Note 3: V
S
switch.
Note 4: The input and output negative voltage ratings may be exceeded if
the input and ou t put diode current ratings ar e observed.
Note 5: Unused control inputs must be held HIGH or LOW. They may not
float.
(Note 5)
CC)
) 0V to 5.5V
IN
) 0V to 5.5V
OUT
, tf)
r
)-40 °C to +85 °C
A
4.0V to 5.5V
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
I
CC
∆ I
CC
Note 6: Typical values are at VCC = 5.0V and TA = +25°C
Note 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 7) 4.5 4 7 Ω V
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
per Input 5.5 2.5 mA One input at 3.4V
CC
CC
(V)
010µAV
4.5 8 12 Ω V
4.0 11 20 Ω VIN = 2.4V, IIN = 15mA
TA = −40 °C to +85 °C
Min T yp
(Note 6)
Units Conditions
Max
= 5.5V
IN
CC
= 0V, IIN = 30mA
IN
= 2.4V, IIN = 15mA
IN
OUT
Other inputs at VCC or GND
FST16211
= 0
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AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50pF, RU = RD = 500Ω
Symbol Parameter
FST16211
L
= 4.5 – 5.5V VCC = 4.0V
V
CC
Units Conditions
Min Max Min Max
t
PHL,tPLH
t
PZH
t
PHZ
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the s w it c h and the 50pF load capa citance, when drive n by an ideal voltage sourc e (zero output impe dance).
Prop Delay Bus to Bus (Note 8) 0.25 0.25 ns VI = OPEN Figures
, t
Output Enable Time 1.5 6.0 6.5 ns VI = 7V for t
PZL
PZL
VI = OPEN for t
, t
Output Disable Time 1.5 7.0 7.2 ns VI = 7V for t
PLZ
PLZ
VI = OPEN for t
PZH
PHZ
Capacitance (Note 9)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Control Pin Input Capacitance 3 pF VCC = 5.0V
Input/Output Capacitance 6 pF VCC, OE = 5.0V
AC Loading and Waveforms
Figure
No.
1, 2
Figures
1, 2
Figures
1, 2
Note: Input driven by 50 Ω source terminated in 50 Ω
includes load and stra y capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
FST16211
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
Package Number BGA54A
Preliminary
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
FST16211
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS56A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
FST16211
56-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
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FST16211 24-Bit Bus Switch
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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