Page 1
查询FST16210供应商
FST16210
20-Bit Bus Switch
FST16210 20-Bit Bus Switch
November 1998
Revised December 1999
General Description
The Fairchild Switch FST16210 provides 20-Bits of highspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organ ized as a 10-bit or 20-Bit bus switch.
When OE
nected to Port 1B. When OE
to Port 2B.
is LOW, the switch is ON and Port 1A is con-
1
is LOW, Port 2A is connected
2
Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
.
CC
Ordering Code:
Order Number Package Number Package Description
FST16210MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Connection Diagram
Logic Diagram
Truth T able
Pin Descriptions
Pin Name Description
, OE
OE
1
1A, 2A Bus A
1B, 2B Bus B
© 1999 Fairchild Semiconductor Corporation DS500193 www.fairchildsemi.com
2
Bus Switch Enables
Inputs Inputs/Outputs
OE
LL1A = 1B 2A = 2B
LH1A = 1B Z
HL Z 2A = 2B
HH Z Z
OE
1
2
1A, 1B 2A, 2B
Page 2
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
FST16210
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) −0.5V to +7.0V
S
) (Note 2) −0.5V to +7.0V
IN
) VIN<0V −50mA
IK
) Sink Current 128mA
) +/− 100mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratings” are those values bey ond which
the safety of the d evice cannot be guaranteed. The device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held high or low. They may not float.
(Note 3)
CC)
)0V to 5.5V
IN
)0V to 5.5V
OUT
, tf)
r
)-40 °C to +85 °C
A
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
I
CC
∆ I
CC
Note 4: Typi c al values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the volta ge drop between A an d B pins at the indicated c urrent through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0≤ VIN ≤5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤A, B ≤V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 5) 4.5 4 7 Ω V
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
per Input 5.5 2.5 mA One input at 3.4V
CC
CC
(V)
010µAV
4.5 8 12 Ω V
4.0 11 20 Ω VIN = 2.4V, IIN = 15mA
TA = −40 °C to +85 °C
Min
Typ
(Note 4)
Units Conditions
Max
= 5.5V
IN
CC
= 0V, IIN = 30mA
IN
= 2.4V, IIN = 15mA
IN
Other inputs at VCC or GND
4.0V to 5.5V
= 0
OUT
www.fairchildsemi.com 2
Page 3
AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50pF, RU = RD = 500Ω
Symbol Parameter
L
= 4.5 – 5.5V VCC = 4.0V
V
CC
Units Conditions Figure No.
Min Max Min Max
t
PHL,tPLH
t
PZH
t
PHZ
Note 6: This par ameter is guaranteed by design but is not te s t ed. The bus swit c h c ontributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load c apacitance, when driven by an ideal voltage source (zero outp ut im pedance).
Prop Delay Bus to Bus
(Note 6)
, t
Output Enable Time 1.5 6.0 6.5 ns VI = 7V for t
PZL
, t
Output Disable Time 1.5 7.0 7.2 n s VI = 7V for t
PLZ
0.25 0.25 ns VI = OPEN Figure 1,
PZL Figure 1,
= OPEN for t
V
I
PLZ Figure 1,
VI = OPEN for t
PZH
PHZ
Figure 2
Figure 2
Figure 2
Capacitance (Note 7)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 7: TA = +25°C, f = 1 MHz, Ca pacitance is charac te riz ed but not tested.
Control pin Input Capacitance 3 pF VCC = 5.0V
Input/Output Capacitance 6 pF VCC, OE = 5.0V
AC Loading and Waveforms
FST16210
Note: Input driven by 50 Ω source terminated in 50 Ω
includes load and stray capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3 www.fairchildsemi.com
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted
FST16210 20-Bit Bus Switch
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven s witch technol ogy used for several years i n its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
www.fairchildsemi.com 4
2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Loading...