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FST16209
18-Bit Bus Exchange Switch
FST16209 18-Bit Bus Exchange Switch
September 1997
Revised December 1999
General Description
The Fairchild Switc h FST16209 provides 18-bits of highspeed CMOS TTL-compatib le bus switching or exchanging. The low on resistance of the sw itch all ow s in put s to be
connected to outputs withou t adding propagation delay or
generating additional ground bounce noise.
The device operates as a 18-bit bus switch or a 9- bit bus
exchanger, which allows data exchang e between the four
signal ports via the data-select terminals.
Features
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low l
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
.
CC
Ordering Code:
Order Number Package Number Package Description
FST16209MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16209MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Logic Diagram
Connection Diagram
Truth Table
S2 S1 S0 A1A
L L L Z Z Disconnect
LLHB
LHLB2ZA
LHHZB1A2 = B
HLLZB2A2 = B
H L H Z Z Disconnect
HHLB
HHHB2B
© 1999 Fairchild Semiconductor Corporation DS500056 www.fairchildsemi.com
2
ZA
1
1B2
1
Function
= B
1
1
= B
1
2
1
2
A1 = B1, A2 = B
A1 = B2, A2 = B
Pin Descriptions
Pin Name Description
S2, S1, S0 Data-select inputs
2
1
, A
A
1
2
B
, B
1
2
Bus A
Bus B
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
FST16209
DC Input Voltage (V
DC Input Diode Current (l
DC Output (I
DC V
OUT
/GND Current (ICC/I
CC
Storage Temperature Range (T
) −0.5V to +7.0V
S
)(Note 2) −0.5V to +7.0V
IN
) VIN<0V −50mA
IK
) Sink Current 128mA
) +/− 100mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0nS/V to 5nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratings” are those values bey ond which
the safety of the d evice cannot be guaranteed. The device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomme nded O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not
float.
(Note 3)
) 4.0V to 5.5V
CC
)0V to 5.5V
IN
)0V to 5.5V
OUT
, tf)
r
) −40 °C to +85 °C
A
DC Electrical Characteristics
= −40 °C to +85 °C
T
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OFF
R
ON
I
CC
∆ I
CC
Note 4: Typi c al values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the volta ge drop between A an d B pins at the indicated c urrent through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64mA
(Note 5) 4.5 4 7 Ω V
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
per Input 5.5 2.5 mA One input at 3.4V
CC
CC
(V)
010µAV
4.5 8 12 Ω VIN = 2.4V, IIN = 15mA
4.0 14 20 Ω V
Min
A
Typ
(Note 4)
Max
Units Conditions
= 5.5V
IN
= 0V, IIN = 30mA
IN
= 2.4V, IIN = 15mA
IN
Other inputs at V
CC
= 0
OUT
or GND
CC
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AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50pF, RU = RD = 500Ω
Symbol Parameter
L
= 4.5 − 5.5V VCC = 4.0V
V
CC
Units Conditions Figure No.
Min Max Min Max
t
, t
PHL
t
PHL
t
PZH
t
PHZ
Note 6: This par ameter is guaranteed by design but is not test ed. The bus swit c h c ontributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load c apacitance, when driven by an ideal voltage source (zero outp ut im pedance).
Prop Delay Bus to Bus (Note 6) 0.25 0.25 ns VI = OPEN Figure 1
PLH
, t
Prop Delay S to Bus 1.5 7.0 7.0 ns VI = OPEN Figure 1
PLH
, t
Output Enable Time, S to A or B 1.5 7.5 8.0 ns VI = 7V for t
PZL
VI = OPEN for t
, t
Output Disable Time S to A or B 1.0 8.5 9.0 ns VI = 7V for t
PLZ
V
= OPEN for t
I
PZL
PLZ
PZH
PHZ
Figure 2
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Capacitance (Note 7)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Control pin Input Capacitance 3 pF VCC = 5.0V
Input/Output Capacitance 10 pF VCC = 5.0V,
S0, S1, and S2 = GND
Note 7: TA = +25°C, f = 1 MHz, Ca pacitance is charac te riz ed but not tested.
AC Loading and Waveforms
FST16209
Note: Input driven by 50 Ω source terminated in 50 Ω
includes load and stray capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
FST16209
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
FST16209 18-Bit Bus Exchange Switch
48-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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