Datasheet FSD176MRT Datasheet (Fairchild)

Page 1
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
FSD176MRT Green-Mode Fairchild Power Switch (FPS™)
Advanced Soft Burst-Mode Operation for
Low Standby Power and Low Audible Noise
Random Frequency Fluctuation for Low EMI Pulse-by-Pulse Current Limit Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis, Output-Short Protection (OSP), and Under-Voltage Lockout (UVLO) with Hysteresis
Low Operating Current (0.4mA) in Burst Mode Internal Startup Circuit Internal High-Voltage SenseFET: 650V Built-in Soft-Start: 15ms Auto-Restart Mode
Description
The FSD176MRT is an integrated Pulse Width Modulation (PWM) controller and SenseFET specifically designed for offline Switch-Mode Power Supplies (SMPS) with minimal external components. The PWM controller includes an integrated fixed-frequency oscillator, Under-Voltage Lockout (UVLO), Leading­Edge Blanking (LEB), optimized gate driver, internal soft-start, temperature-compensated precise current sources for loop compensation, and self-protection circuitry. Compared with a discrete MOSFET and PWM controller solution, the FSD176MRT can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective design of a flyback converter.
September 2011
Applications
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
(2)
(4)
Frame
Open
(5)
Output Power Table
Operating
Part Number Package
FSD176MRTUDTU
FSD176MRTLDTU
Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230V
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
AC
TO-220
6-Lead
U-Forming
TO-220
6-Lead
L-Forming
or 100/115VAC with voltage doubler.
Junction
Temperature
-40°C ~
(1)
+125°C
-40°C ~
(1)
+125°C
Current
R
DS(ON)
Limit
3.50A 1.6 80W 90W 48W 70W FSGM0765R
3.50A 1.6 80W 90W 48W 70W FSGM0765R
(Max.)
230VAC ±15%
Adapter
(4)
(3)
85~265VAC
Open
Frame
(5)
Adapter
Replaces
Device
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0
Page 2
Application Circuit
AC
IN
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
V
O
V
STR
Drain
GND
Internal Block Diagram
V
burst
0.30V / 0.45V
FB
N.C. 5
V
4
CC
2.0uA I
DELAY
tON<t
OSP
V
ref
(1.0μs)
90uA
I
FB
FB
V
CC
Figure 1. Typical Application Circuit
V
STR
6 3
Soft Burst
Random
OSC
Soft Start
PWM
3R
R
SQ
R
LEB(300ns)
V
CC
I
CH
V
ref
VCCgood
Q
Gate
Driver
7.5V / 12V
Drain
1
V
SD
7.0V
V
CC
V
OVP
24.5V
LPF
V
OSP
TSD
VCCgood
SQ
R
Q
V
AOCP
GND
2
Figure 2. Internal Block Diagram
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 2
Page 3
Pin Configuration
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 Drain
2 GND
3 VCC
4 FB
5 NC No Connection
6 V
SenseFET Drain. High-voltage power SenseFET drain connection.
Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, which provides the internal operating
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7V, the overload protection triggers, which shuts down the FPS.
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At startup, the internal high-voltage current source supplies internal bias and charges the
STR
external capacitor connected to the V source (I
) is disabled.
CH
pin. Once VCC reaches 12V, the internal current
CC
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 3
Page 4
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
V
V
STR
V
Drain Pin Voltage 650 V
DS
V
V
CC
V
Feedback Pin Voltage
FB
I
Drain Current Pulsed 12.8 A
DM
I
Continuous Switching Drain Current
DS
EAS Single Pulsed Avalanche Energy
PD
T
J
T
Storage Temperature
STG
ESD
Notes:
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D and junction temperature (see Figure 4. ).
7. L=45mH, starting TJ=25C.
8. Infinite cooling condition (refer to the SEMI G30-88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Pin Voltage 650 V
STR
Pin Voltage 26 V
CC
12.0 V
Total Power Dissipation (TC=25C)
-0.3
T
=25C
(6)
C
TC=100C
(7)
390 mJ
(8)
6.4 A
4.0 A
50 W
Maximum Junction Temperature 150
Operating Junction Temperature
Electrostatic Discharge Capability
Human Body Model, JESD22-A114 4.5
Charged Device Model, JESD22-C101 2.0
(9)
-40
-55
+125
+150
MAX
C
C
C
kV
=0.74)
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol Parameter Value Unit
JA Junction-to-Ambient Thermal Impedance
JC Junction-to-Case Thermal Impedance
Notes:
10. Free standing without heat sink under natural convection condition, per JEDEC 51-2 and 1-10.
11. Infinite cooling condition per Mil Std. 883C method 1012.1.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 4
(10)
63.5 °C/W
(11)
2.5 °C/W
Page 5
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics
TJ = 25C unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Unit
SenseFET Section
BV
Drain-Source Breakdown Voltage
DSS
I
Zero-Gate-Voltage Drain Current
DSS
R
Drain-Source On-State Resistance VGS=10V, ID =1A 1.3 1.6
DS(ON)
C
Input Capacitance
ISS
C
Output Capacitance
OSS
(12)
V
(12)
V
tr Rise Time V
tf Fall Time V
t
Turn-On Delay V
d(on)
t
Turn-Off Delay V
d(off)
= 0V, ID = 250A
V
CC
V
= 650V, TA = 25C
DS
= 25V, V
DS
= 25V, V
DS
= 325V, ID = 4A, RG=25 30 ns
DS
= 325V, ID = 4A, RG=25 26 ns
DS
= 325V, ID = 4A, RG=25 16 ns
DS
= 325V, ID= 4A, RG=25 39 ns
DS
= 0V, f=1MHz 674 pF
GS
= 0V, f=1MHz 93 pF
GS
Control Section
f
Switching Frequency
S
f
D
MAX
D
MIN
Switching Frequency Variation
S
Maximum Duty Ratio V
Minimum Duty Ratio V
(12)
V
(12)
= 14V, V
CC
-25C < T
= 14V, V
CC
= 14V, V
CC
= 4V 61 67 73 kHz
FB
< 125C
J
= 4V 61 67 73 %
FB
= 0V %
FB
IFB Feedback Source Current VFB=0V 65 90 115
V
START
V
STOP
t
S/S
UVLO Threshold Voltage
After Turn-on, V
Internal Soft-Start Time V
V
= 0V, V
FB
STR
CC
= 40V, V
Sweep 11 12 13 V
= 0V 7.0 7.5 8.0 V
FB
Sweep 15 ms
CC
Burst-Mode Section
V
BURH
V
V
BURL
HYS
Burst-Mode Voltage V
0.26 0.30 0.34 V
150 mV
= 14V, VFB Sweep
CC
Protection Section
I
Peak Drain Current Limit
LIM
V
Shutdown Feedback Voltage V
SD
I
Shutdown Delay Current V
DELAY
t
Leading-Edge Blanking Time
LEB
V
Over-Voltage Protection VCC Sweep 23.0 24.5 26.0 V
OVP
t
OSP
V
OSP
t
OSP_FB
TSD
T
HYS
Output-Short
Threshold VFB 1.8 2.0 2.2 V
Protection
V
Thermal Shutdown Temperature
Hysteresis 60
Threshold Time
(12)
FB
Blanking Time 2.0 2.5 3.0
(12)(14)
di/dt = 300mA/s
= 14V, V
CC
= 14V, V
CC
Sweep 6.45 7.00 7.55 V
FB
= 4V 1.2 2.0 2.8
FB
300 ns
OSP Triggered when t (Lasts Longer than t
Shutdown Temperature 130 140 150
(12)
ON<tOSP
& VFB>V
OSP
OSP_FB
650 V
250
±5 ±10 %
0.39 0.45 0.51 V
3.15 3.50 3.85 A
0.7 1.0 1.3
)
Continued on the following page…
A
A
A
s
s
C
C
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 5
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FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Electrical Characteristics (Continued)
TJ = 25C unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Unit
Total Device Section
I
OP
I
OPS
I
START
I
CH
V
STR
Operating Supply Current, (Control Part in Burst Mode)
Operating Switching Current, (Control Part and SenseFET Part)
Start Current
Startup Charging Current V
Minimum V
Supply Voltage VCC = V
STR
Notes:
12. Although these parameters are guaranteed, they are not 100% tested in production.
13. Average value.
14. t
includes gate turn-on time.
LEB
V
= 14V, V
CC
VCC = 14V, V
=11V (Before VCC
V
CC
Reaches V
= V
CC
= 0V, V
FB
= 0V, V
FB
FB
FB
START
= 0V 0.3 0.4 0.5 mA
= 2V 1.1 1.5 1.9 mA
)
= 40V 0.7 1.0 1.3 mA
STR
Sweep 26 V
STR
85 120 155
A
Comparison of FSGM0765R and FSD176MRT
Function FSGM0765R FSD176MRT Advantages of FSD176MRT
Random Frequency Fluctuation
Operating Current 1.6mA 0.4mA Very low standby power
Built-in
Low EMI
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 6
Page 7
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Figure 5. Operating Supply Current (IOP) vs. TA Figure 6. Operating Switching Current (I
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
OPS
) vs. TA
Figure 7. Startup Charging Current (ICH) vs. TA Figure 8. Peak Drain Current Limit (I
1.40
1.30
1.20
1.10
1.00
0.90
Normalized
0.80
0.70
0.60 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
) vs. TA
LIM
Figure 9. Feedback Source Current (IFB) vs. TA Figure 10. Shutdown Delay Current (I
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 7
DELAY
) vs. TA
Page 8
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Figure 11. UVLO Threshold Voltage (V
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
) vs. TA Figure 12. UVLO Threshold Voltage (V
START
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
STOP
) vs. TA
Figure 13. Shutdown Feedback Voltage (VSD) vs. TA Figure 14. Over-Voltage Protection (V
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110' C 120'C 125'C
Temperature [ °C]
1.20
1.15
1.10
1.05
1.00
0.95
Normalized
0.90
0.85
0.80 ‐40'C ‐20'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C
Temperature [ °C]
Figure 15. Switching Frequency (fS) vs. TA Figure 16. Maximim Duty Ratio (D
OVP
MAX
) vs. TA
) vs. TA
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 8
Page 9
Functional Description
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the external capacitor (C illustrated in Figure 17. When V
) connected to the VCC pin, as
Vcc
reaches 12V, the
CC
FSD176MRT begins switching and the internal high­voltage current source is disabled. The FSD176MRT continues normal switching operation and the power is supplied from the auxiliary transformer winding unless V
goes below the stop voltage of 7.5V.
CC
Figure 17. Startup Block
2. Soft-Start: The internal soft-start circuit increases the
PWM comparator inverting input voltage, together with the SenseFET current, slowly after startup. The typical soft-start time is 15ms. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This helps prevent transformer saturation and reduces stress on the secondary diode during startup.
3. Feedback Control: This device employs current­mode control, as shown in Figure 18. An opto-coupler (such as the FOD817) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the R
resistor makes it possible to
SENSE
control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing drain current. This typically occurs when the input voltage is increased or the output load is decreased.
3.1 Pulse-by-Pulse Current Limit: Because current­mode control is employed, the peak current through the SenseFET is limited by the inverting input of the PWM comparator (V
*), as shown in Figure 18.
FB
Assuming that the 90A current source flows only through the internal resistor (3R + R = 27k), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (V
) exceeds
FB
2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current through the SenseFET is limited.
3.2 Leading-Edge Blanking (LEB): At the instant the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the R
SENSE
resistor leads to incorrect feedback operation in the current-mode PWM control. To counter this effect, the FSD176MRT employs a leading-edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for t
(300ns) after the SenseFET is turned on.
LEB
Figure 18. Pulse Width Modulation Circuit
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 9
Page 10
4. Protection Circuits: The FSD176MRT has several self-protective functions, such as Overload Protection (OLP), Abnormal Over-Current Protection (AOCP), Output-Short Protection (OSP), Over-Voltage Protection (OVP), and Thermal Shutdown (TSD). All the protections are implemented as auto-restart. Once a
increasing until it reaches 7.0V, when the switching operation is terminated, as shown in Figure 20. The delay for shutdown is the time required to charge C
FB
from 2.5V to 7.0V with 2.0µA. A 25 ~ 50ms delay is typical for most applications. This protection is
implemented in auto-restart mode. fault condition is detected, switching is terminated and the SenseFET remains off. This causes V When V
B
B falls to the Under-Voltage Lockout (UVLO)
CC
to fall.
CC
stop voltage of 7.5V, the protection is reset and the startup circuit charges the V
capacitor. When VCC
CC
reaches the start voltage of 12.0V, the FSD176MRT resumes normal operation. If the fault condition is not removed, the SenseFET remains off and V
drops to
CC
stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. Because these protection circuits are fully integrated into the IC without external components, the reliability is improved without increasing cost.
Figure 20. Overload Protection
4.2 Abnormal Over-Current Protection (AOCP):
When the secondary rectifier diodes or the
transformer pins are shorted, a steep current with
extremely high di/dt can flow through the SenseFET
during the minimum turn-on time. Overload protection
is not enough to protect the FSD176MRT in that
abnormal case; since severe current stress is
imposed on the SenseFET until OLP is triggered. The
FSD176MRT internal AOCP circuit is shown in Figure
21. When the gate turn-on signal is applied to the
power SenseFET, the AOCP block is enabled and
monitors the current through the sensing resistor. The
voltage across the resistor is compared with a preset
AOCP level. If the sensing resistor voltage is greater
than the AOCP level, the set signal is applied to the
Figure 19. Auto-Restart Protection Waveforms
4.1 Overload Protection (OLP): Overload is defined
as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in normal operation, the overload protection circuit can be triggered during load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the SenseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (V below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (V
). If VFB exceeds 2.5V, D1 is
FB
blocked and the 2.0µA current source starts to charge C
slowly up. In this condition, VFB continues
FB
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 10
) decreases
OUT
S-R latch, resulting in the shutdown of the SMPS.
Figure 21. Abnormal Over-Current Protection
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Page 11
4.3. Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can flow through the SenseFET during the minimum turn­on time. Such a steep current brings high-voltage stress on the drain of the SenseFET when turned off. To protect the device from this abnormal condition, OSP is included. It is comprised of detecting V SenseFET turn-on time. When the V
is higher than
FB
FB
2.0V and the SenseFET turn-on time is lower than
1.0s, the FSD176MRT recognizes this condition as an abnormal error and shuts down PWM switching until V
reaches V
CC
again. An abnormal condition
START
output short is shown in Figure 22.
and
5. Soft Burst-Mode Operation: To minimize power dissipation in Standby Mode, the FSD176MRT enters Burst-Mode operation. As the load decreases, the feedback voltage decreases. The device automatically enters Burst Mode when the feedback voltage drops below V
(300mV), as shown in Figure 23. At this
BURL
point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes V
(450mV), switching resumes. The feedback
BURH
voltage then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET, reducing switching loss in Standby Mode.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 11
Figure 22. Output-Short Protection
4.4 Over-Voltage Protection (OVP): If the
secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then V
climbs up in a similar
FB
manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is triggered. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. In general, the V and the FSD176MRT uses V monitoring the output voltage. If V
is proportional to the output voltage
CC
instead of directly
CC
exceeds 24.5V,
CC
an OVP circuit is triggered, resulting in the termination of the switching operation. To avoid undesired activation of OVP during normal operation, V
should
CC
be designed to be below 24.5V.
4.5 Thermal Shutdown (TSD): The SenseFET and the control IC on a die in one package makes it easier for the control IC to detect the over temperature of the SenseFET. If the temperature exceeds ~140C, the thermal shutdown is triggered and stops operation. The FSD176MRT operates in auto-restart mode until the temperature decreases to around 75C, when normal operation resumes.
Figure 23. Burst-Mode Operation
6. Random Frequency Fluctuation (RFF): Fluctuating
switching frequency of an SMPS can reduce EMI by spreading the energy over a wide frequency range. The amount of EMI reduction is directly related to the switching frequency variation, which is limited internally. The switching frequency is determined randomly by external feedback voltage and an internal free-running oscillator at every switching instant. This random frequency fluctuation scatters the EMI noise around typical switching frequency (67kHz) effectively and can reduce the cost of the input filter included to meet the EMI requirements (e.g. EN55022).
Figure 24. Random Frequency Fluctuation
Page 12
Typical Application Circuit
Application Input Voltage Rated Output Rated Power
LCD Monitor
Power Supply 14.0V (3.5A)
85 ~ 265V
AC
Key Design Notes:
1. The delay for overload protection is designed to be about 30ms with C105 (8.2nF). OLP time between 39ms
(12nF) and 46ms (15nF) is recommended.
2. The SMD-type capacitor (C106) must be placed as close as possible to the V
abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100nF and 220nF is recommended.
5.0V (3A) 64W
pin to avoid malfunction by
CC
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Figure 25. Schematic
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 12
Page 13
Transformer Specification
Core: EER3019 (Ae=134 mm2)
Bobbin: EER3019
Table 1. Winding specification
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Figure 26. Transformer Specification
Pin(S → F) Wire Turns Winding Method
Barrier Tape
TOP BOT Ts
Np /2(BOT) 3  2 0.4×1 18 Solenoid Winding 2.0mm 1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N
7  6 0.4×3 (TIW) 3 Solenoid Winding 3.0mm 1
5V
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Na 4  5 0.20×1 8 Solenoid Winding 4.0mm 3.0mm 1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N5V 8  6 0.4×3 (TIW) 3 Solenoid Winding 3.0mm 1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N
10  8 0.4×3 (TIW) 5 Solenoid Winding 1
14V
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2(TOP) 2  1 0.4×1 18 Solenoid Winding 2.0mm 1
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Table 2. Electrical Characteristics
Pin Specification Remark
Inductance
Leakage
1-3
1-3
465H ±6%
10H Maximum
67kHz, 1V
Short all other pins
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 13
Page 14
Table 3. Bill of Materials
Part # Value Note Part # Value Note
Fuse Capacitor
F101 250V 3.15A C101 220nF/275V Box (Pilkor)
NTC
NTC101 5D-11 DSC C103 120µF/400V Electrolytic (SamYoung)
Resistor
R101 1.5M, J 1W C105 12nF/100V Film (Sehwa)
R103 43k, J 1W C106 220nF SMD (2012)
R201 1k, F 1/4W, 1% C107 47µF/50V Electrolytic (SamYoung)
R202 1.2k, F 1/4W, 1% C201 1000µF/25V Electrolytic (SamYoung)
R203 18k, F 1/4W, 1% C202 1000µF/25V Electrolytic (SamYoung)
R204 8k, F 1/4W, 1% C203 1000µF/25V Electrolytic (SamYoung)
R205 8k, F 1/4W, 1% C204 2200µF/10V Electrolytic (SamYoung)
IC
SMPS FSD176MRT Fairchild Semiconductor C301 4.7nF/Y2 Y-cap (Samhwa)
IC201 KA431LZ Fairchild Semiconductor
IC301 FOD817B Fairchild Semiconductor LF101 20mH Line Filter 0.5Ø
Diode L201 5µH 5A Rating
D101 1N4007 Vishay L202 5µH 5A Rating
D102 UF4004 Vishay
ZD101 1N4750 Vishay T101 465µH
D201 MBR20150CT Fairchild Semiconductor
D202 FYPF2006DN Fairchild Semiconductor
BD101 G3SBA60 Vishay
C102 150nF/275V Box (Pilkor)
C104 3.3nF/630V Film (Sehwa)
C205 1000µF/16V Electrolytic (SamYoung)
C206 1000µF/16V Electrolytic (SamYoung)
C207 100nF SMD (2012)
C208 100nF SMD (2012)
Inductor
Transformer
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 14
Page 15
Physical Dimensions
A
3.40
3.20
16.08
15.68
10.36
9.96
5.18
4.98
Ø
B
3.28
3.08
(21.01)
(17.83)
6.88
6.48
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
2.74
2.34 (0.70)
C
(1.13)
1.30
1.05
#1 #6
2.19
1.27
5°
0.85
0.75
0.65
0.55
1.75
3.81
4.80
4.40
5PLCS
6PLCS
3.18
0.20 AB
5°
NOTES: A) NO PACKAGE STANDARD APPLIES. B) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. C) DIMENSIONS ARE IN MILLIMETERS. D) DRAWING FILENAME : MKT-TO220E06REV2
0.61
0.46
R1.00
R1.00
#2,4,6
#1,3,5
0.05
4.90 6PLCS
4.70
C
Figure 27. 6-Lead, TO220, Fullpack, Formed
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 15
Page 16
Physical Dimensions
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
A
16.07
15.67
8.13
7.13
3.40
3.20
(0.88)
10.36
9.96
(7.00)
1.40
1.20
#1 #6
5.18
4.98
0.80
0.70
0.70
0.50
B
Ø
(5.40)
5PLCS
5PLCS
3.28
3.08
R0.55
19.97
18.97
R0.55
#1,6
18.94
17.94
R0.55
6.88
6.48
#2,4 #3,5
2.74
2.34
(0.70)
(0.48)
3.06
2.46
13.05
24.00
23.00
7.15
2.19
5°
1.27
3.81
1.75
5°
4.80
4.40
0.20 AB
(3.81)
7.29
6.69
NOTES: A) NO PACKAGE STANDARD APPLIES. B) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. C) DIMENSIONS ARE IN MILLIMETERS. D) DRAWING FILENAME : MKT-TO220F06REV2
0.60
0.45
3.48
2.88
Figure 28. 6-Lead, TO220, Fullpack, U-Forming, 2 DAP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 16
Page 17
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSD176MRT • Rev. 1.0.0 17
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