The FSD176MRT is an integrated Pulse Width
Modulation (PWM) controller and SenseFET specifically
designed for offline Switch-Mode Power Supplies
(SMPS) with minimal external components. The PWM
controller includes an integrated fixed-frequency
oscillator, Under-Voltage Lockout (UVLO), LeadingEdge Blanking (LEB), optimized gate driver, internal
soft-start, temperature-compensated precise current
sources for loop compensation, and self-protection
circuitry. Compared with a discrete MOSFET and PWM
controller solution, the FSD176MRT can reduce total
cost, component count, size, and weight; while
simultaneously increasing efficiency, productivity, and
system reliability. This device provides a basic platform
for cost-effective design of a flyback converter.
September 2011
Applications
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
(2)
(4)
Frame
Open
(5)
Output Power Table
Operating
Part Number Package
FSD176MRTUDTU
FSD176MRTLDTU
Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230V
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 Drain
2 GND
3 VCC
4 FB
5 NC No Connection
6 V
SenseFET Drain. High-voltage power SenseFET drain connection.
Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, which provides the internal operating
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
should be placed between this pin and GND. If the voltage of this pin reaches 7V, the overload
protection triggers, which shuts down the FPS.
Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.
At startup, the internal high-voltage current source supplies internal bias and charges the
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
V
V
STR
V
Drain Pin Voltage 650 V
DS
V
V
CC
V
Feedback Pin Voltage
FB
I
Drain Current Pulsed 12.8 A
DM
I
Continuous Switching Drain Current
DS
EAS Single Pulsed Avalanche Energy
PD
T
J
T
Storage Temperature
STG
ESD
Notes:
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D
and junction temperature (see Figure 4. ).
7. L=45mH, starting TJ=25C.
8. Infinite cooling condition (refer to the SEMI G30-88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Pin Voltage 650 V
STR
Pin Voltage 26 V
CC
12.0 V
Total Power Dissipation (TC=25C)
-0.3
T
=25C
(6)
C
TC=100C
(7)
390 mJ
(8)
6.4 A
4.0 A
50 W
Maximum Junction Temperature 150
Operating Junction Temperature
Electrostatic
Discharge Capability
Human Body Model, JESD22-A114 4.5
Charged Device Model, JESD22-C101 2.0
(9)
-40
-55
+125
+150
MAX
C
C
C
kV
=0.74)
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol Parameter Value Unit
JA Junction-to-Ambient Thermal Impedance
JC Junction-to-Case Thermal Impedance
Notes:
10. Free standing without heat sink under natural convection condition, per JEDEC 51-2 and 1-10.
11. Infinite cooling condition per Mil Std. 883C method 1012.1.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (C
illustrated in Figure 17. When V
) connected to the VCC pin, as
Vcc
reaches 12V, the
CC
FSD176MRT begins switching and the internal highvoltage current source is disabled. The FSD176MRT
continues normal switching operation and the power is
supplied from the auxiliary transformer winding unless
V
goes below the stop voltage of 7.5V.
CC
Figure 17. Startup Block
2. Soft-Start: The internal soft-start circuit increases the
PWM comparator inverting input voltage, together with
the SenseFET current, slowly after startup. The typical
soft-start time is 15ms. The pulse width to the power
switching device is progressively increased to establish
the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased to smoothly
establish the required output voltage. This helps prevent
transformer saturation and reduces stress on the
secondary diode during startup.
3. Feedback Control: This device employs currentmode control, as shown in Figure 18. An opto-coupler
(such as the FOD817) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R
resistor makes it possible to
SENSE
control the switching duty cycle. When the reference pin
voltage of the shunt regulator exceeds the internal
reference voltage of 2.5V, the opto-coupler LED current
increases, pulling down the feedback voltage and
reducing drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
3.1 Pulse-by-Pulse Current Limit: Because currentmode control is employed, the peak current through
the SenseFET is limited by the inverting input of the
PWM comparator (V
*), as shown in Figure 18.
FB
Assuming that the 90A current source flows only
through the internal resistor (3R + R = 27k), the
cathode voltage of diode D2 is about 2.5V. Since D1 is
blocked when the feedback voltage (V
) exceeds
FB
2.5V, the maximum voltage of the cathode of D2 is
clamped at this voltage. Therefore, the peak value of
the current through the SenseFET is limited.
3.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the R
SENSE
resistor leads to incorrect feedback operation in the
current-mode PWM control. To counter this effect, the
FSD176MRT employs a leading-edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for
t
4. Protection Circuits: The FSD176MRT has several
self-protective functions, such as Overload Protection
(OLP), Abnormal Over-Current Protection (AOCP),
Output-Short Protection (OSP), Over-Voltage Protection
(OVP), and Thermal Shutdown (TSD). All the
protections are implemented as auto-restart. Once a
increasing until it reaches 7.0V, when the switching
operation is terminated, as shown in Figure 20. The
delay for shutdown is the time required to charge C
FB
from 2.5V to 7.0V with 2.0µA. A 25 ~ 50ms delay is
typical for most applications. This protection is
implemented in auto-restart mode.
fault condition is detected, switching is terminated and
the SenseFET remains off. This causes V
When V
B
B falls to the Under-Voltage Lockout (UVLO)
CC
to fall.
CC
stop voltage of 7.5V, the protection is reset and the
startup circuit charges the V
capacitor. When VCC
CC
reaches the start voltage of 12.0V, the FSD176MRT
resumes normal operation. If the fault condition is not
removed, the SenseFET remains off and V
drops to
CC
stop voltage again. In this manner, the auto-restart can
alternately enable and disable the switching of the
power SenseFET until the fault condition is eliminated.
Because these protection circuits are fully integrated
into the IC without external components, the reliability is
improved without increasing cost.
Figure 20. Overload Protection
4.2 Abnormal Over-Current Protection (AOCP):
When the secondary rectifier diodes or the
transformer pins are shorted, a steep current with
extremely high di/dt can flow through the SenseFET
during the minimum turn-on time. Overload protection
is not enough to protect the FSD176MRT in that
abnormal case; since severe current stress is
imposed on the SenseFET until OLP is triggered. The
FSD176MRT internal AOCP circuit is shown in Figure
21. When the gate turn-on signal is applied to the
power SenseFET, the AOCP block is enabled and
monitors the current through the sensing resistor. The
voltage across the resistor is compared with a preset
AOCP level. If the sensing resistor voltage is greater
than the AOCP level, the set signal is applied to the
Figure 19. Auto-Restart Protection Waveforms
4.1 Overload Protection (OLP): Overload is defined
as the load current exceeding its normal level due to
an unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, even when the SMPS is in normal
operation, the overload protection circuit can be
triggered during load transition. To avoid this
undesired operation, the overload protection circuit is
designed to trigger only after a specified time to
determine whether it is a transient situation or a true
overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current
through the SenseFET is limited and, therefore, the
maximum input power is restricted with a given input
voltage. If the output consumes more than this
maximum power, the output voltage (V
below the set voltage. This reduces the current
through the opto-coupler LED, which also reduces the
opto-coupler transistor current, thus increasing the
feedback voltage (V
). If VFB exceeds 2.5V, D1 is
FB
blocked and the 2.0µA current source starts to charge
C
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
Page 11
4.3. Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can
flow through the SenseFET during the minimum turnon time. Such a steep current brings high-voltage
stress on the drain of the SenseFET when turned off.
To protect the device from this abnormal condition,
OSP is included. It is comprised of detecting V
SenseFET turn-on time. When the V
is higher than
FB
FB
2.0V and the SenseFET turn-on time is lower than
1.0s, the FSD176MRT recognizes this condition as
an abnormal error and shuts down PWM switching
until V
reaches V
CC
again. An abnormal condition
START
output short is shown in Figure 22.
and
5. Soft Burst-Mode Operation: To minimize power
dissipation in Standby Mode, the FSD176MRT enters
Burst-Mode operation. As the load decreases, the
feedback voltage decreases. The device automatically
enters Burst Mode when the feedback voltage drops
below V
(300mV), as shown in Figure 23. At this
BURL
point, switching stops and the output voltages start to
drop at a rate dependent on standby current load. This
causes the feedback voltage to rise. Once it passes
V
(450mV), switching resumes. The feedback
BURH
voltage then falls and the process repeats. Burst Mode
alternately enables and disables switching of the
SenseFET, reducing switching loss in Standby Mode.
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor
becomes almost zero. Then V
climbs up in a similar
FB
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is triggered. Because more energy
than required is provided to the output, the output
voltage may exceed the rated voltage before the
overload protection is triggered, resulting in the
breakdown of the devices in the secondary side. To
prevent this situation, an OVP circuit is employed. In
general, the V
and the FSD176MRT uses V
monitoring the output voltage. If V
is proportional to the output voltage
CC
instead of directly
CC
exceeds 24.5V,
CC
an OVP circuit is triggered, resulting in the termination
of the switching operation. To avoid undesired
activation of OVP during normal operation, V
should
CC
be designed to be below 24.5V.
4.5 Thermal Shutdown (TSD): The SenseFET and
the control IC on a die in one package makes it easier
for the control IC to detect the over temperature of the
SenseFET. If the temperature exceeds ~140C, the
thermal shutdown is triggered and stops operation.
The FSD176MRT operates in auto-restart mode until
the temperature decreases to around 75C, when
normal operation resumes.
Figure 23. Burst-Mode Operation
6. Random Frequency Fluctuation (RFF): Fluctuating
switching frequency of an SMPS can reduce EMI by
spreading the energy over a wide frequency range. The
amount of EMI reduction is directly related to the
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by
external feedback voltage and an internal free-running
oscillator at every switching instant. This random
frequency fluctuation scatters the EMI noise around
typical switching frequency (67kHz) effectively and can
reduce the cost of the input filter included to meet the
EMI requirements (e.g. EN55022).
Figure 24. Random Frequency Fluctuation
Page 12
Typical Application Circuit
Application Input Voltage Rated Output Rated Power
LCD Monitor
Power Supply 14.0V (3.5A)
85 ~ 265V
AC
Key Design Notes:
1. The delay for overload protection is designed to be about 30ms with C105 (8.2nF). OLP time between 39ms
(12nF) and 46ms (15nF) is recommended.
2. The SMD-type capacitor (C106) must be placed as close as possible to the V
abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100nF and 220nF is
recommended.
5.0V (3A)
64W
pin to avoid malfunction by
CC
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
2.74
2.34
(0.70)
C
(1.13)
1.30
1.05
#1#6
2.19
1.27
5°
0.85
0.75
0.65
0.55
1.75
3.81
4.80
4.40
5PLCS
6PLCS
3.18
0.20AB
5°
NOTES:
A) NO PACKAGE STANDARD APPLIES.
B) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
C) DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING FILENAME : MKT-TO220E06REV2
0.61
0.46
R1.00
R1.00
#2,4,6
#1,3,5
0.05
4.90
6PLCS
4.70
C
Figure 27. 6-Lead, TO220, Fullpack, Formed
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
FSD176MRT — Green-Mode Fairchild Power Switch (FPS™)
A
16.07
15.67
8.13
7.13
3.40
3.20
(0.88)
10.36
9.96
(7.00)
1.40
1.20
#1#6
5.18
4.98
0.80
0.70
0.70
0.50
B
Ø
(5.40)
5PLCS
5PLCS
3.28
3.08
R0.55
19.97
18.97
R0.55
#1,6
18.94
17.94
R0.55
6.88
6.48
#2,4#3,5
2.74
2.34
(0.70)
(0.48)
3.06
2.46
13.05
24.00
23.00
7.15
2.19
5°
1.27
3.81
1.75
5°
4.80
4.40
0.20AB
(3.81)
7.29
6.69
NOTES:
A) NO PACKAGE STANDARD APPLIES.
B) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
C) DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING FILENAME : MKT-TO220F06REV2
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: