Datasheet FQU7N10L, FQD7N10L Datasheet (Fairchild Semiconductor)

FQD7N10L / FQU7N10L

100V LOGIC N-Channel MOSFET

December 2000

QFET

QFETQFET

FQD7N10L / FQU7N10L

TM

General Description

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation modes. These devices are well suited for low voltage applications such as high efficiency switching DC/DC converters, and DC motor control.

D

S

D-PAK

= 25°C)

C

G

D

S

= 25°C unless otherwise noted

C

= 25°C)

C

= 100°C)

C

FQD Series

- Continuous (T

- Derate above 25°C 0.2 W/°C

G

Absolute Maximum Ratings T

Symbol Parameter FQD7N10L / FQU7N10L Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

, T

T

J

STG

T

L

Drain-Source Voltage 100 V Drain Current

Drain Current - Pulsed Gate-Source Voltage ± 20 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

Features

• 5.8A, 100V, R

• Low gate charge ( typical 4.6 nC)

• Low Crss ( typical 12 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

• Low level gate drive requirments allowing direct operation from logic drives

I-PAK

FQU Series

(Note 1)

(Note 2) (Note 1) (Note 1) (Note 3)

= 0.35Ω @VGS = 10 V

DS(on)

!

G

5.8 A

3.67 A

23.2 A

50 mJ

5.8 A

2.5 mJ

6.0 V/ns

2.5 W 25 W

300 °C

!

D

!

"

" "

"

!

S

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 5.0 °C/W Thermal Resistance, Junction-to-Ambient * -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W

Rev. A2, December 2000

FQD7N10L / FQU7N10L

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter T e s t Conditions Min Typ Max Units

Off Characteristics

BV ∆BV / ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage

DSS

Breakdown Voltage Temperature

DSS

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

I

= 250 µA, Referenced to 25°C

D

V

= 100 V, VGS = 0 V

DS

V

= 80 V, TC = 125°C

DS

V

= 20 V, VDS = 0 V

GS

= -20 V, VDS = 0 V

V

GS

100 -- -- V

-- 0.1 -- V/°C

-- -- 1 µA

-- -- 10 µA

-- -- 100 nA

-- -- -100 nA

On Characteristics

V R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage Static Drain-Source

On-Resistance Forward Transconductance

V

= VGS, ID = 250 µA

DS

V

= 10 V, ID = 2.9 A

GS

= 5 V, ID = 2.9 A

V

GS

V

= 30 V, ID = 2.9 A

DS

(Note 4)

1.0 -- 2.0 V

0.275

--

0.300

0.35

0.38

-- 4.6 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance -- 55 72 pF Reverse Transfer Capacitance -- 12 15 pF

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 220 290 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 100 210 ns Turn-Off Delay Time -- 17 45 ns Turn-Off Fall Time -- 50 110 ns Total Gate Charge Gate-Source Charge -- 1.0 -- nC Gate-Drain Charge -- 2.6 -- nC

= 50 V, ID = 7.3 A,

V

DD

= 25 Ω

R

G

= 80 V, ID = 7.3 A,

V

DS

V

GS

= 5 V

(Note 4, 5)

-- 9 30 ns

-- 4.6 6.0 nC

Ω

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 2.23mH, IAS = 5.8A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 7.3A, di/dt ≤ 300A/µs, VDD ≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- 5.8 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 23.2 A

= 0 V, IS = 5.8 A

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 140 -- nC

Starting TJ = 25°C

DSS,

V

GS

= 0 V, IS = 7.3 A,

V

GS

/ dt = 100 A/µs

dI

F

-- -- 1.5 V

-- 70 -- ns

(Note 4)

Rev. A2, December 2000

Typical Characteristics

FQD7N10L / FQU7N10L

V

GS

Top : 10.0 V

8.0 V

1

10

6.0 V

5.0 V

4.5 V

4.0 V

3.5 V Bottom : 3.0 V

0

10

, Drain Current [A]

D

I

-1

10

-1

10

0

10

※

1. 250μs Pulse Test

2. T

VDS, Drain-Source Voltage [V]

1.5

1.2

0.9

],

Ω

[

0.6

DS(ON)

R

0.3

VGS = 5V

VGS = 10V

Drain-Source On-Resistance

0.0 0 5 10 15 20

ID, Drain Current [A]

Notes :

※

= 25

C

10

Note : T

1

10

℃

150

℃

1

0

10

℃

25

, Dra in Cu rrent [A]

D

I

-1

10

0246810

℃

-55

※

Notes :

1. V

= 30V

DS

2. 250μs Pulse Test

VGS , Gate - Source Voltage [V]

Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s

1

10

℃

= 25

J

0

10

℃

150

℃

, Reverse Drain Current [A]

DR

I

-1

10

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

25

※

Notes :

1. V

= 0V

GS

2. 250μs Pulse Test

VSD , So u rce-Dra in Volta ge [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

VDS = 50V

VDS = 80V

※

Note : I

600

500

400

300

200

Capacitance [pF]

100

0

-1

10

C

= Cgs + Cgd (Cds = shorted)

iss

= Cds + C

C

oss

gd

C

= C

rss

gd

※

10

1

Notes :

= 0 V

1. V

GS

2. f = 1 MH z

C

iss

C

oss

C

rss

0

10

VDS, Drain-Source Voltage [V]

12

10

8

6

4

, Gate-Source Voltage [V]

2

GS

V

0

012345678

QG, Tota l Gate Charge [n C]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Ch a ra ct eristics

= 7.3 A

D

Typical Characteristics (Continued)

FQD7N10L / FQU7N10L

1.2

1.1

1.0

, (Norm a liz e d )

DSS

BV

0.9

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

※

1. V

2. I

Notes :

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

DS(on)

DC

※

Notes :

1. T

= 25 oC

C

= 150 oC

2. T

J

3. Single Pulse

1

10

100 µs

1 ms

10 ms

2

10

1

10

0

10

, Drain Current [A]

D

I

-1

10

0

10

Operation in This Area is Limited by R

VDS, Drain-Source Voltage [V]

= 0 V

GS

= 250 μA

D

3.0

2.5

2.0

1.5

, (Normalized)

1.0

DS(ON)

R

Drain-Source On-Resistance

0.5

0.0

-100 -50 0 50 100 150 200

※

Notes :

1. V

= 5 V

GS

2. I

= 2.9 A

D

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs. Temperature

6

5

4

2

10

3

2

, Drain Current [A]

D

I

1

0

25 50 75 100 125 150

TC, Case Temperature [℃]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

D=0.5

※

0.2

0

10

0.1

0.05

0.02

(t), Therm al Response

JC

0.01

θ

-1

10

Z

-5

10

single pulse

-4

10

t

1

-3

10

-2

10

, S q u a re W av e P u ls e D u ra tio n [s ec ]

N o te s :

(t) = 5.0 ℃/W M a x .

1. Z

θ

JC

2. D u ty F a c to r, D = t

3. TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

1/t2

(t)

θ

JC

0

1

10

Figure 11. Transient Thermal Response Cur ve

Rev. A2, December 2000

12V

200nF

3mA

50K

FQD7N10L / FQU7N10L

Gate Charge Test Circuit & Waveform

V

GS

DS

5V

GS

Q

g

Q

gs

Q

gd

Charge

Same Type

Ω

300nF

V

GS

Same Type

as DUT

DUT

V

Resistive Switching Test Circuit & Waveforms

5V

10V

R

L

DUT

L

V

DD

V

DS

V

GS

R

G

V

DS

90%

10%

V

GS

t

d(on)tr

t

on

t

d(off)

t

f

t

off

Unclamped Inductive Switching Test Circuit & Waveforms

BV

DSS

L

LL

V

DS

BV

DSS

V

DSS

I

AS

DD

I

IDI

D

R

G

DUT

t

p

V

DD

1

----

E

=LI

E

=LI

AS

2

AS

(t)

I

D

t

p

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

DUT

I

SD

Driver

R

G

V

GS

+

V

DS

_

L

LL

Same Type

as DUT

• dv/dt controlled by R

•ISDcontroll ed by pulse peri od

G

FQD7N10L / FQU7N10L

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

IFM, Body Diode Forward Current

I

RM

Body Diode Reverse Current

Body Diode Recoverydv/dt

V

SD

Body Diode

Forward Voltage Drop

di/dt

10V

V

DD

Rev. A2, December 2000

Package Dimensions

FQD7N10L / FQU7N10L

DPAK

6.60 ±0.20

0.60 ±0.20

0.80 ±0.20

MAX0.96

2.30TYP

[2.30±0.20]

5.34 ±0.30 (4.34)(0.50) (0.50)

0.76 ±0.10

2.30TYP

[2.30±0.20]

2.70 ±0.20

0.70 ±0.20

6.10 ±0.20

9.50 ±0.30

±0.10

0.91

0.89 ±0.10

6.60 ±0.20 (5.34) (5.04) (1.50)

2.30 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

(0.90)

(0.70)

MIN0.55

(1.00)

9.50 ±0.30

(2XR0.25)

6.10 ±0.20

2.70 ±0.20 (0.10) (3.05)

0.76 ±0.10

FQD7N10L / FQU7N10L

Package Dimensions

(0.50) (0.50)(4.34)

0.60 ±0.20

(Continued)

6.60 ±0.20

5.34 ±0.20

IPAK

0.70 ±0.20

2.30 ±0.20

0.50 ±0.10

6.10 ±0.20

0.80 ±0.10

MAX0.96

0.76 ±0.10

2.30TYP

[2.30±0.20]

1.80 ±0.20

2.30TYP

[2.30±0.20]

16.10 ±0.30

9.30 ±0.30

0.50 ±0.10

Rev. A2, December 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™

2

E

CMOS™ FACT™ FACT Quiet Series™

®

FAST FASTr™ GTO™

HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench

®

QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6

SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. A, January 2000

Datasheet FQU7N10L, FQD7N10L Datasheet (Fairchild Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual