Datasheet FQU18N20V2, FQD18N20V2 Datasheet (Fairchild Semiconductor)

FQD18N20V2 / FQU18N20V2

200V N-Channel MOSFET

FQD18N20V2 / FQU18N20V2

TM

QFET

General Description

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well

Features

• 15A, 200V, R

• Low gate charge ( typical 20 nC)

• Low Crss ( typical 25 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

= 0.14Ω @VGS = 10 V

DS(on)

suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC mo tor control.

D

!

"

" "

"

!

S

D

GS

D-PAK

FQD Series

GSD

Absolute Maximum Ratings T

I-PAK

FQU Series

= 25°C unless otherwise noted

C

!

G

Symbol Parameter FQD18N20V2 / FQU18N20V2 Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

Drain-Source Voltage 200 V Drain Current

- Continuous (T

Drain Current - Pulsed

= 25°C)

C

= 100°C)

C

(Note 1)

15 A

9.75 A 60 A

Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

= 25°C)

C

(Note 2) (Note 1) (Note 1) (Note 3)

340 mJ

15 A

8.3 mJ

6.5 V/ns

2.5 W 83 W

- Derate above 25°C 0.67 W/°C

T

, T

J

STG

T

L

Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

300 °C

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 1.5 °C/W Thermal Resistance, Junction-to-Ambient * -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W

Rev. B1, August 2002

FQD18N20V2 / FQU18N20V2

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter T e s t Conditions Min Typ Max Units

Off Characteristics

BV

DSS

∆BV

DSS

/ ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

I

= 250 µA, Referenced to 25°C

D

V

= 200 V, VGS = 0 V

DS

V

= 160 V, TC = 125°C

DS

V

= 30 V, VDS = 0 V

GS

= -30 V, VDS = 0 V

V

GS

200 -- -- V

-- 0.25 -- V/°C

-- -- 1 µA

-- -- 10 µA

-- -- 100 nA

-- -- -100 nA

On Characteristics

V R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage Static Drain-Source

On-Resistance Forward Transconductance

V

= VGS, ID = 250 µA

DS

= 10 V, ID = 7.5 A

V

GS

= 40 V, ID = 7.5 A

V

DS

(Note 4)

3.0 -- 5.0 V

-- 0.12 0.14 Ω

-- 11 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

C

oss

C

oss

Input Capacitance Output Capacitance -- 200 260 pF Reverse Transfer Capacitance -- 25 33 pF

Output Capacitance

eff.

Effective Output Capacitance

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

V

= 160 V, VGS = 0 V,

DS

f = 1.0 MHz VDS = 0V to 160 V, VGS = 0 V

-- 830 1080 pF

-- 70 -- pF

-- 135 -- pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 133 275 ns Turn-Off Delay Time -- 38 85 ns Turn-Off Fall Time -- 62 135 ns Total Gate Charge Gate-Source Charge -- 5.6 -- nC Gate-Drain Charge -- 10 -- nC

= 100 V, ID = 18 A,

V

DD

= 25 Ω

R

G

(Note 4, 5)

= 160 V, ID = 18 A,

V

DS

V

GS

(Note 4, 5)

= 10 V

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 1.58mH, IAS = 18A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 18A, di/dt ≤ 200A/µs, VDD ≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- 15 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 60 A

= 0 V, IS = 15 A

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 1.0 -- µC

Starting TJ = 25°C

DSS,

V

GS

= 0 V, IS = 18 A,

V

GS

/ dt = 100 A/µs

dI

F

(Note 4)

-- 16 40 ns

-- 20 26 nC

-- -- 1.5 V

-- 158 -- ns

Rev. B1, August 2002

Typical Characteristics

FQD18N20V2 / FQU18N20V2

V

GS

Top : 15.0 V

10.0 V

8.0 V

1

10

7.0 V

6.5 V

6.0 V Bottom : 5.5 V

0

10

, Drain Current [A]

D

I

-1

10

-1

10

0

10

!

Notes :

1. 250#s Pulse Test = 25

2. T

C

1

10

VDS, Drain-Source Voltage [V]

Figure 1. On-Region Char act er i stic s

0.5

0.4

],

0.3

$

[

DS(ON)

0.2

R

0.1

Drain-Source On-Resistanc e

0.0 0 102030405060

VGS = 10V

VGS = 20V

ID, Drain Current [A]

!

Note : T

1

10

0

10

, Drain Current [A]

D

I

"

-1

10

45678910

"

150

"

25

"

-55

!

Note s :

1. V

= 40V

DS

2. 25 0#s Pulse Test

VGS , Gate-Source Voltage [V]

Figure 2. Transfer Characteristics

1

10

J

= 25

0

10

, Reverse Drain Current [A]

DR

"

I

-1

10

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

"

150

"

25

!

Note s :

= 0V

1. V

GS

2. 250#s Pulse Test

VSD , Source-Drain Voltage [V]

Figure 3. On-Resistance Variati on vs.

Drain Current and Gate Voltage

2500

2000

1500

1000

Capacitanc e [p F ]

500

0

-1

10

VDS, Drain-Source Voltage [V]

Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

C

= Cgs + Cgd (Cds = shorted)

iss

= Cds + C

C

oss

gd

C

= C

rss

gd

!

Notes :

= 0 V

1. V

GS

2. f = 1 MHz

C

iss

C

oss

C

rss

0

10

1

10

12

10

8

6

4

, Gate-Source Voltage [V]

GS

2

V

0

0 5 10 15 20 25

QG, Tota l G a te C h ar ge [n C ]

VDS = 40V

VDS = 100V

VDS = 160V

!

Note : I

= 18A

D

Rev. B1, August 2002

Typical Characteristics (Continued)

FQD18N20V2 / FQU18N20V2

1.2

1.1

1.0

, (Normalized)

DSS

0.9

BV

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

2

10

1

10

0

!

Notes :

10

, Drain Current [A]

D

I

-1

10

= 25 oC

1. T

C

2. T

= 150 oC

J

3. Single Pulse

0

Operation in This Ar ea is Limited by R

DS(on)

100 us

1 ms

10 ms

DC

1

10

VDS, Drain-Source Voltage [V]

3.0

2.5

2.0

1.5

, (Normalized)

1.0

DS(ON)

R

0.5

Drain-Source On-Resistance

0.0

-100 -50 0 50 100 150 200

!

1. V

2. I

Notes :

D

= 10 V

GS

= 7.5 A

!

1. V

2. I

Notes :

D

= 0 V

GS

= 250 #A

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs. Temperature

20

15

2

10

, Drain Current [A]

5

D

I

0

25 50 75 100 125 150

TC, Case Temperature ["]

Figure 9. Maximum Safe Operating Area

(t), Therm al Response Z

Figure 10. Maximum Drain Current

vs. Case Temperature

0

10

D=0.5

0.2

0.1

-1

10

0.05

0.02

0.01

JC

%

-2

10

-5

single pulse

-4

10

-3

10

-2

!

Notes :

(t) = 1.5 "/W M a x .

1 . Z

%

JC

2. D uty F a c to r, D = t 3 . TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

0

10

1/t2

%

JC

(t)

1

10

t1, Square W ave Pulse Duration [sec]

Figure 11. Transient Thermal Response Cur ve

Rev. B1, August 2002

12V

200nF

3mA

50K&

V

Gate Charge Test Circuit & Waveform

V

GS

300nF

Same Type

as DUT

DUT

V

DS

GS

10V

Resistive Switching Test Circuit & Waveforms

FQD18N20V2 / FQU18N20V2

Q

g

Q

gs

Q

gd

Charge

10V

R

L

DUT

L

V

DD

V

DS

V

GS

R

G

V

DS

90%

10%

V

GS

t

d(on)tr

t

on

t

d(off)

t

f

t

off

Unclamped Inductive Switching Test Circuit & Waveforms

BV

DSS

L

LL

V

DS

BV

DSS

V

DSS

I

AS

DD

I

IDI

D

R

G

DUT

t

p

V

DD

1

----

E

=LI

E

=LI

AS

2

AS

ID (t)

t

2

p

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Rev. B1, August 2002

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

DUT

I

SD

Driver

R

G

V

GS

+

V

DS

_

L

LL

Same Type

as DUT

• dv/dt controlled by R

•ISDcontroll ed by pulse peri od

G

FQD18N20V2 / FQU18N20V2

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

IFM, Body Diode Forward Current

I

RM

Body Diode Reverse Current

Body Diode Recoverydv/dt

V

SD

Body Diode

Forward Voltage Drop

di/dt

10V

V

DD

Rev. B1, August 2002

Package Dimensions

6.60 ±0.20

FQD18N20V2 / FQU18N20V2

DPAK

0.60 ±0.20

0.80 ±0.20

MAX0.96

2.30TYP

[2.30±0.20]

5.34 ±0.30 (4.34)(0.50) (0.50)

0.76 ±0.10

2.30TYP

[2.30±0.20]

2.70 ±0.20

0.70 ±0.20

6.10 ±0.20

9.50 ±0.30

±0.10

0.91

0.89 ±0.10

6.60 ±0.20 (5.34)

(5.04) (1.50)

2.30 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

(0.90)

(0.70)

MIN0.55

(1.00)

9.50 ±0.30

(2XR0.25)

6.10 ±0.20

2.70 ±0.20 (0.10) (3.05)

0.76 ±0.10

Dimensions in Millimeters

Rev. B1, August 2002

Package Dimensions

(Continued)

FQD18N20V2 / FQU18N20V2

IPAK

(0.50) (0.50)(4.34)

0.60 ±0.20

0.80 ±0.10

MAX0.96

0.76 ±0.10

6.60 ±0.20

5.34 ±0.20

0.70 ±0.20

1.80 ±0.20

2.30 ±0.20

0.50 ±0.10

6.10 ±0.20

16.10 ±0.30

9.30 ±0.30

2.30TYP

[2.30±0.20]

2.30TYP

[2.30±0.20]

0.50 ±0.10

Dimensions in Millimeters

Rev. B1, August 2002

TRADEMARKS

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2

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OPTOPLANAR™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I1