Page 1
August 2000
FQS4900
FQS4900
Dual N & P-Channel, Logic Level MOSFET
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
D2
D2
D1
D1
S1
G1
S2
G2
QFET
QFET
QFET QFET
Features
• N-Channel 1.3A, 60V, R
R
P-Channel -0.3A, -300V, R
R
• Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
• Fast switching
• Improved dv/dt capability
!
!
5
6
7
8
!
!
"
"
!
!
!
!
!
!
!
!
!
!
$
$
!
!
!
!
= 0.55 Ω @ VGS = 10 V
DS(on)
= 0.65 Ω @ VGS = 5 V
DS(on)
= 15.5 Ω @ VGS = -10 V
DS(on)
= 16 Ω @ VGS =- 5 V
DS(on)
#
#
4
3
2
1
TM
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter N-Channel P-Channel Units
V
DSS
I
D
I
DM
V
GSS
dv/dt Peak Diode Recovery dv/dt
P
D
T
, T
J
STG
Drain-Source Voltage 60 -300 V
Drain Current
- Continuous (T
- Continuous (T
Drain Curent - Pulsed
= 25°C)
A
= 70°C)
A
(Note 1)
1.3 -0.3 A
0.82 -0.19 A
5.2 -1.2 A
Gate-Source Voltage ± 20 V
Power Dissipation (TA = 25°C)
= 70°C)
(T
A
(Note 2)
7.0 4.5 V/ns
2.0 W
1.3 W
Operating and Storage Temperature Range -55 to +150 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θ JA
©2000 Fairchild Semiconductor International
Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
Rev. A, August 2000
Page 2
FQS4900
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Zero Gate Voltage Drain Current
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
V
GS
V
= 0 V, ID = -250 µA
GS
= 60 V, VGS = 0 V
V
DS
V
= 48 V, TC = 55°C
DS
= -300 V, VGS = 0 V
V
DS
V
= -240 V, TC = 55°C
DS
= 20 V, VDS = 0 V
V
GS
V
= -20 V, VDS = 0 V
GS
N-Ch 60 -- -- V
P-Ch -300 -- -- V
N-Ch
P-Ch
-- -- 1 µA
-- -- 10 µA
-- -- -1 µA
-- -- -10 µA
All -- -- 100 nA
All -- -- -100 nA
= 0 V, ID = 250 µA
On Characteristics
V
R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
= 4V, ID = 20 mA
DS
= 4V, ID = -20 mA
V
DS
= 10 V, ID = 0.65 A
V
GS
V
= 5 V, ID = 0.65 A
GS
V
= -10 V, ID = -0.15 A
GS
= -5 V, ID = -0.15 A
V
GS
V
= 10 V, ID = 0.65 A
DS
= -10 V, ID = -0.15 A
V
DS
N-Ch 1.0 -- 1.95 V
P-Ch -1.0 -- -1.95 V
N-Ch
P-CH
-- 0.39 0.55 Ω
-- 0.46 0.65 Ω
-- 11.2 15.5 Ω
-- 11.4 16 Ω
N-CH -- 1.7 -- S
P-CH -- 0.6 -- S
V
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
g
gs
Total Gate Charge
Gate-Source Charge
N-Channel
V
= 30 V, ID = 1.3 A,
DD
= 25 Ω
R
G
P-Channel
= -150 V, ID = -0.3 A,
V
DD
R
= 25 Ω
G
N-Channel
= 48 V, ID = 1.3 A,
V
DS
V
= 5 V
GS
P-Channel
V
= -240 V, ID = -0.3 A,
gd
Gate-Drain Charge
V
DS
GS
= -5 V
N-Ch -- 5.7 21 ns
P-Ch -- 10 30 ns
N-Ch -- 21 50 ns
P-Ch -- 25 60 ns
N-Ch -- 11 32 ns
P-Ch -- 35 80 ns
N-Ch -- 17 45 ns
P-Ch -- 47 105 ns
N-Ch -- 1.6 2.1 nC
P-Ch -- 3.6 4.7 nC
N-Ch -- 0.28 -- nC
P-Ch -- 0.42 -- nC
N-Ch -- 0.82 -- nC
P-Ch -- 2.1 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
3. Pulse Test : Pulse width ≤ 300µ s, Duty cycle ≤ 2%
4. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current
= 0 V, IS = 1.3 A
Drain-Source Diode Forward Voltage
V
GS
V
= 0 V, IS = -0.3 A
GS
N-Ch -- -- 1.3 A
P-Ch -- -- -0.3 A
N-Ch -- -- 1.5 V
P-Ch -- -- -4.0 V
Rev. A, August 2000
Page 3
Typical Characteristics : N-Channel
FQS4900
, Drain Current [A]
D
I
10
0
10
-1
-1
10
V
Top : 10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
GS
VDS, Drain-Source Voltage [V]
!
Notes :
1. 250#s Pulse Test
= 25
2. T
C
0
10
0
10
"
"
1
10
150
"
25
, Dra i n Current [A]
D
I
-1
10
024681 0
-55
VGS, Gate-Source Voltage [V]
"
!
Notes :
1. V
= 25V
DS
2. 250#s Pulse Tes t
Figure 2. Transfer Characteristics Figure 1. On-Region Char act er i stic s
2.0
1.5
],
$
[
1.0
DS(ON)
R
0.5
VGS = 5V
VGS = 10V
Drain-Source On-Resistance
!
"
Note : T
= 25
0.0
02468
J
ID, Drain Current [A]
0
10
"
150
, Reverse Drain Current [A]
DR
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
VSD, Sou r c e-Dra i n volta g e [V]
"
25
!
Notes :
= 0V
1. V
GS
2. 250#s Pulse Test
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
160
120
80
Capacitance [pF]
40
0
-1
10
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge C haracteristics
©2000 Fairchild Semiconductor International
C
C
C
C
iss
C
oss
C
rss
0
10
VDS, Drain-Source Voltage [V]
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
oss
gd
= C
rss
gd
!
Notes :
= 0 V
1. V
GS
2. f = 1 MH z
1
10
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDS = 30V
VDS = 48V
QG, Tota l Gate Cha rg e [nC]
!
Note : I
= 1.3 A
D
Rev. A, August 2000
Page 4
Typical Characteristics : N-Channel (Continued)
FQS4900
1.2
1.1
1.0
, (Norma liz e d )
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
!
1. V
2. I
Notes :
D
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area
1
10
0
10
, Drain C u rren t [A ]
-1
D
I
10
-2
10
-1
10
is Limited by R
DS(on)
1 s
10 s
DC
!
Notes :
1. T
= 25 oC
C
= 150 oC
2. T
J
3. Single Pulse
0
10
1
10
VDS, Drain-Source Voltage [V]
100 ms
GS
= 250
= 0 V
10 ms
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
0.5
#
A
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
!
Notes :
1. V
= 10 V
GS
2. I
= 0.65 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Va riation
vs. Temperature
1 ms
1.5
1.2
0.9
0.6
, Drain Current [A]
D
I
0.3
2
10
0.0
25 50 75 100 125 150
TC, Case Temperature ["]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
D=0.5
0.2
1
10
0.1
0.05
0.02
0
10
0.01
(t), Thermal Response
JC
%
Z
-1
10
-4
10
single pulse
-3
10
-2
10
-1
10
!
No te s :
1. Z
(t) = 62.5 "/W M a x .
%
JC
2. D u ty F a c to r , D = t1/t
3. TJM - TC = PDM * Z
P
DM
0
10
10
2
(t)
%
JC
t
1
t
2
1
10
2
t1, Square Wave Pulse Duration [sec]
Figure 11. Trans ient Ther m al Res pons e Cur ve
Rev. A, August 2000
Page 5
Typical Characteristics : P-Channel (Continued)
FQS4900
10
10
, Drain Current [A]
D
-I
10
0
V
Top : -10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
-3.5 V
Bottom : -3.0 V
-1
-2
-1
10
GS
-VDS, Drain-Source Voltage [V]
0
10
"
150
"
25
, Drain Current [A]
!
Notes :
1. 250#s Pulse Test
"
2. T
= 25
C
0
10
1
10
D
-I
-1
10
024681 0
"
-55
-VGS , Gate-Source Voltage [V]
!
Notes :
1. V
= -25V
DS
2. 250#s Pulse Test
Figure 2. Transfer Characteristics Fi gur e 1. O n- Regi on Characteristics
VGS = - 5V
!
Note : T
30
25
[Ω ],
20
DS(on)
R
15
Drain-Source On-Resistance
10
0.0 0.3 0.6 0.9 1.2 1.5
VGS = - 10V
-ID , Drai n Current [A]
0
10
"
, Reverse Drain Current [A]
"
= 25
J
DR
-I
-1
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
150
-VSD , Sou r c e-Drain Voltage [V]
"
25
!
Notes :
= 0V
1. V
GS
2. 250#s Pulse Tes t
Figure 3. On-Resistance V ariation vs.
Drain Current and Gate Voltage
250
200
150
100
Capacitance [pF]
50
0
-1
10
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge C haracteristics
©2000 Fairchild Semiconductor International
C
C
C
C
iss
C
oss
C
rss
0
10
VDS, Drain-Source Voltage [V]
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
oss
gd
= C
rss
gd
!
Notes :
= 0 V
1. V
GS
2. f = 1 MHz
1
10
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
6
4
, Gate-S o u rce V o ltag e [V ]
GS
2
-V
0
0123456
VDS = -60V
V
= -150V
DS
VDS = -240V
QG, Tota l Gate Cha r g e [nC]
!
Note : I
= -0.3 A
D
Rev. A, August 2000
Page 6
Typical Characteristics : P-Channel (Continued)
FQS4900
1.2
1.1
1.0
, (Norma liz e d )
DSS
!
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
1. V
2. I
Notes :
D
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
1
10
0
10
-1
10
, Drain Current [A]
D
-2
-I
10
-3
10
0
10
-VDS, Drain-Source Voltage [V]
Operation in This Area
is Limited by R
DS(on)
DC
!
Notes :
1. T
= 25 oC
C
2. T
= 150 oC
J
3. Single Pulse
1
10
10 s
10 ms
100 ms
1 s
2
10
= 0 V
GS
= -250 #A
1 ms
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
0.5
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
!
Note s :
1. V
= -10 V
GS
2. I
= -0.15 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Va riation
vs. Temperature
0.35
0.30
0.25
0.20
0.15
, Dra in Curre n t [A]
D
0.10
-I
0.05
0.00
25 50 75 100 125 150
TC, Case Temp erature ["]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
D=0.5
0.2
1
10
0.1
0.05
0.02
0
10
0.01
(t), T hermal Response
JC
%
Z
-1
10
-4
10
single pulse
-3
10
-2
10
-1
10
!
No te s :
1. Z
(t) = 62.5 "/W M a x .
%
JC
2. D u ty F a c to r , D = t1/t
3. TJM - TC = PDM * Z
P
DM
0
10
10
2
(t)
%
JC
t
1
t
2
1
10
2
t1, Square W ave Pulse Duration [sec]
Figure 11. Trans ient Ther m al Res pons e Cur ve
Rev. A, August 2000
Page 7
Gate Charge Test Circuit & Waveform
FQS4900
V
V
GS
DS
DS
5V
5V
V
V
V
V
GS
DS
DS
GS
GS
10%
10%
Q
Q
gs
gs
90%
90%
t
t
d(on)tr
d(on)tr
Q
Q
g
g
Q
Q
gd
gd
Charge
Charge
t
t
d(off)
d(off)
t
t
f
t
t
on
on
f
t
t
off
off
12V
12V
5V
5V
200nF
200nF
3mA
3mA
Same Type
50K
50K
&
&
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Page 8
Package Dimensions
8-SOP
1.55 ±0.20
0.061 ±0.008
MIN
0.004~0.001
0.1~0.25
0.56
0.022
()
FQS4900
0.006
0.15
+
-0.002
0.004
+
-0.05
0.10
0.50 ±0.20
0.020 ±0.008
#1
#4
6.00 ±0.30
0.236 ±0.012
3.95 ±0.20
0.156 ±0.008
5.72
0.225
#8
#5
5.13
1.80
0.071
0~8°
MAX
0.202
4.92 ±0.20
MAX
0.194 ±0.008
MAX0.10
MAX0.004
1.27
0.050
0.41 ±0.10
0.016 ±0.004
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Page 9
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
2
E
CMOS™
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
®
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2000 Fairchild Semiconductor International
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. A, January 2000